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/sound/soc/codecs/ak4642.c

https://bitbucket.org/Tofe/picasso-kernel
C | 571 lines | 421 code | 74 blank | 76 comment | 15 complexity | adb5b003337ad9dcdf0d78943fa1e501 MD5 | raw file
  1. /*
  2. * ak4642.c -- AK4642/AK4643 ALSA Soc Audio driver
  3. *
  4. * Copyright (C) 2009 Renesas Solutions Corp.
  5. * Kuninori Morimoto <morimoto.kuninori@renesas.com>
  6. *
  7. * Based on wm8731.c by Richard Purdie
  8. * Based on ak4535.c by Richard Purdie
  9. * Based on wm8753.c by Liam Girdwood
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License version 2 as
  13. * published by the Free Software Foundation.
  14. */
  15. /* ** CAUTION **
  16. *
  17. * This is very simple driver.
  18. * It can use headphone output / stereo input only
  19. *
  20. * AK4642 is tested.
  21. * AK4643 is tested.
  22. * AK4648 is tested.
  23. */
  24. #include <linux/delay.h>
  25. #include <linux/i2c.h>
  26. #include <linux/slab.h>
  27. #include <linux/module.h>
  28. #include <sound/soc.h>
  29. #include <sound/initval.h>
  30. #include <sound/tlv.h>
  31. #define PW_MGMT1 0x00
  32. #define PW_MGMT2 0x01
  33. #define SG_SL1 0x02
  34. #define SG_SL2 0x03
  35. #define MD_CTL1 0x04
  36. #define MD_CTL2 0x05
  37. #define TIMER 0x06
  38. #define ALC_CTL1 0x07
  39. #define ALC_CTL2 0x08
  40. #define L_IVC 0x09
  41. #define L_DVC 0x0a
  42. #define ALC_CTL3 0x0b
  43. #define R_IVC 0x0c
  44. #define R_DVC 0x0d
  45. #define MD_CTL3 0x0e
  46. #define MD_CTL4 0x0f
  47. #define PW_MGMT3 0x10
  48. #define DF_S 0x11
  49. #define FIL3_0 0x12
  50. #define FIL3_1 0x13
  51. #define FIL3_2 0x14
  52. #define FIL3_3 0x15
  53. #define EQ_0 0x16
  54. #define EQ_1 0x17
  55. #define EQ_2 0x18
  56. #define EQ_3 0x19
  57. #define EQ_4 0x1a
  58. #define EQ_5 0x1b
  59. #define FIL1_0 0x1c
  60. #define FIL1_1 0x1d
  61. #define FIL1_2 0x1e
  62. #define FIL1_3 0x1f
  63. #define PW_MGMT4 0x20
  64. #define MD_CTL5 0x21
  65. #define LO_MS 0x22
  66. #define HP_MS 0x23
  67. #define SPK_MS 0x24
  68. /* PW_MGMT1*/
  69. #define PMVCM (1 << 6) /* VCOM Power Management */
  70. #define PMMIN (1 << 5) /* MIN Input Power Management */
  71. #define PMDAC (1 << 2) /* DAC Power Management */
  72. #define PMADL (1 << 0) /* MIC Amp Lch and ADC Lch Power Management */
  73. /* PW_MGMT2 */
  74. #define HPMTN (1 << 6)
  75. #define PMHPL (1 << 5)
  76. #define PMHPR (1 << 4)
  77. #define MS (1 << 3) /* master/slave select */
  78. #define MCKO (1 << 1)
  79. #define PMPLL (1 << 0)
  80. #define PMHP_MASK (PMHPL | PMHPR)
  81. #define PMHP PMHP_MASK
  82. /* PW_MGMT3 */
  83. #define PMADR (1 << 0) /* MIC L / ADC R Power Management */
  84. /* SG_SL1 */
  85. #define MINS (1 << 6) /* Switch from MIN to Speaker */
  86. #define DACL (1 << 4) /* Switch from DAC to Stereo or Receiver */
  87. #define PMMP (1 << 2) /* MPWR pin Power Management */
  88. #define MGAIN0 (1 << 0) /* MIC amp gain*/
  89. /* TIMER */
  90. #define ZTM(param) ((param & 0x3) << 4) /* ALC Zoro Crossing TimeOut */
  91. #define WTM(param) (((param & 0x4) << 4) | ((param & 0x3) << 2))
  92. /* ALC_CTL1 */
  93. #define ALC (1 << 5) /* ALC Enable */
  94. #define LMTH0 (1 << 0) /* ALC Limiter / Recovery Level */
  95. /* MD_CTL1 */
  96. #define PLL3 (1 << 7)
  97. #define PLL2 (1 << 6)
  98. #define PLL1 (1 << 5)
  99. #define PLL0 (1 << 4)
  100. #define PLL_MASK (PLL3 | PLL2 | PLL1 | PLL0)
  101. #define BCKO_MASK (1 << 3)
  102. #define BCKO_64 BCKO_MASK
  103. #define DIF_MASK (3 << 0)
  104. #define DSP (0 << 0)
  105. #define RIGHT_J (1 << 0)
  106. #define LEFT_J (2 << 0)
  107. #define I2S (3 << 0)
  108. /* MD_CTL2 */
  109. #define FS0 (1 << 0)
  110. #define FS1 (1 << 1)
  111. #define FS2 (1 << 2)
  112. #define FS3 (1 << 5)
  113. #define FS_MASK (FS0 | FS1 | FS2 | FS3)
  114. /* MD_CTL3 */
  115. #define BST1 (1 << 3)
  116. /* MD_CTL4 */
  117. #define DACH (1 << 0)
  118. /*
  119. * Playback Volume (table 39)
  120. *
  121. * max : 0x00 : +12.0 dB
  122. * ( 0.5 dB step )
  123. * min : 0xFE : -115.0 dB
  124. * mute: 0xFF
  125. */
  126. static const DECLARE_TLV_DB_SCALE(out_tlv, -11550, 50, 1);
  127. static const struct snd_kcontrol_new ak4642_snd_controls[] = {
  128. SOC_DOUBLE_R_TLV("Digital Playback Volume", L_DVC, R_DVC,
  129. 0, 0xFF, 1, out_tlv),
  130. };
  131. static const struct snd_kcontrol_new ak4642_headphone_control =
  132. SOC_DAPM_SINGLE("Switch", PW_MGMT2, 6, 1, 0);
  133. static const struct snd_kcontrol_new ak4642_lout_mixer_controls[] = {
  134. SOC_DAPM_SINGLE("DACL", SG_SL1, 4, 1, 0),
  135. };
  136. static const struct snd_soc_dapm_widget ak4642_dapm_widgets[] = {
  137. /* Outputs */
  138. SND_SOC_DAPM_OUTPUT("HPOUTL"),
  139. SND_SOC_DAPM_OUTPUT("HPOUTR"),
  140. SND_SOC_DAPM_OUTPUT("LINEOUT"),
  141. SND_SOC_DAPM_PGA("HPL Out", PW_MGMT2, 5, 0, NULL, 0),
  142. SND_SOC_DAPM_PGA("HPR Out", PW_MGMT2, 4, 0, NULL, 0),
  143. SND_SOC_DAPM_SWITCH("Headphone Enable", SND_SOC_NOPM, 0, 0,
  144. &ak4642_headphone_control),
  145. SND_SOC_DAPM_PGA("DACH", MD_CTL4, 0, 0, NULL, 0),
  146. SND_SOC_DAPM_MIXER("LINEOUT Mixer", PW_MGMT1, 3, 0,
  147. &ak4642_lout_mixer_controls[0],
  148. ARRAY_SIZE(ak4642_lout_mixer_controls)),
  149. /* DAC */
  150. SND_SOC_DAPM_DAC("DAC", "HiFi Playback", PW_MGMT1, 2, 0),
  151. };
  152. static const struct snd_soc_dapm_route ak4642_intercon[] = {
  153. /* Outputs */
  154. {"HPOUTL", NULL, "HPL Out"},
  155. {"HPOUTR", NULL, "HPR Out"},
  156. {"LINEOUT", NULL, "LINEOUT Mixer"},
  157. {"HPL Out", NULL, "Headphone Enable"},
  158. {"HPR Out", NULL, "Headphone Enable"},
  159. {"Headphone Enable", "Switch", "DACH"},
  160. {"DACH", NULL, "DAC"},
  161. {"LINEOUT Mixer", "DACL", "DAC"},
  162. };
  163. /*
  164. * ak4642 register cache
  165. */
  166. static const u8 ak4642_reg[] = {
  167. 0x00, 0x00, 0x01, 0x00,
  168. 0x02, 0x00, 0x00, 0x00,
  169. 0xe1, 0xe1, 0x18, 0x00,
  170. 0xe1, 0x18, 0x11, 0x08,
  171. 0x00, 0x00, 0x00, 0x00,
  172. 0x00, 0x00, 0x00, 0x00,
  173. 0x00, 0x00, 0x00, 0x00,
  174. 0x00, 0x00, 0x00, 0x00,
  175. 0x00, 0x00, 0x00, 0x00,
  176. 0x00,
  177. };
  178. static const u8 ak4648_reg[] = {
  179. 0x00, 0x00, 0x01, 0x00,
  180. 0x02, 0x00, 0x00, 0x00,
  181. 0xe1, 0xe1, 0x18, 0x00,
  182. 0xe1, 0x18, 0x11, 0xb8,
  183. 0x00, 0x00, 0x00, 0x00,
  184. 0x00, 0x00, 0x00, 0x00,
  185. 0x00, 0x00, 0x00, 0x00,
  186. 0x00, 0x00, 0x00, 0x00,
  187. 0x00, 0x00, 0x00, 0x00,
  188. 0x00, 0x88, 0x88, 0x08,
  189. };
  190. static int ak4642_dai_startup(struct snd_pcm_substream *substream,
  191. struct snd_soc_dai *dai)
  192. {
  193. int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
  194. struct snd_soc_codec *codec = dai->codec;
  195. if (is_play) {
  196. /*
  197. * start headphone output
  198. *
  199. * PLL, Master Mode
  200. * Audio I/F Format :MSB justified (ADC & DAC)
  201. * Bass Boost Level : Middle
  202. *
  203. * This operation came from example code of
  204. * "ASAHI KASEI AK4642" (japanese) manual p97.
  205. */
  206. snd_soc_write(codec, L_IVC, 0x91); /* volume */
  207. snd_soc_write(codec, R_IVC, 0x91); /* volume */
  208. } else {
  209. /*
  210. * start stereo input
  211. *
  212. * PLL Master Mode
  213. * Audio I/F Format:MSB justified (ADC & DAC)
  214. * Pre MIC AMP:+20dB
  215. * MIC Power On
  216. * ALC setting:Refer to Table 35
  217. * ALC bit=“1”
  218. *
  219. * This operation came from example code of
  220. * "ASAHI KASEI AK4642" (japanese) manual p94.
  221. */
  222. snd_soc_write(codec, SG_SL1, PMMP | MGAIN0);
  223. snd_soc_write(codec, TIMER, ZTM(0x3) | WTM(0x3));
  224. snd_soc_write(codec, ALC_CTL1, ALC | LMTH0);
  225. snd_soc_update_bits(codec, PW_MGMT1, PMADL, PMADL);
  226. snd_soc_update_bits(codec, PW_MGMT3, PMADR, PMADR);
  227. }
  228. return 0;
  229. }
  230. static void ak4642_dai_shutdown(struct snd_pcm_substream *substream,
  231. struct snd_soc_dai *dai)
  232. {
  233. int is_play = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
  234. struct snd_soc_codec *codec = dai->codec;
  235. if (is_play) {
  236. } else {
  237. /* stop stereo input */
  238. snd_soc_update_bits(codec, PW_MGMT1, PMADL, 0);
  239. snd_soc_update_bits(codec, PW_MGMT3, PMADR, 0);
  240. snd_soc_update_bits(codec, ALC_CTL1, ALC, 0);
  241. }
  242. }
  243. static int ak4642_dai_set_sysclk(struct snd_soc_dai *codec_dai,
  244. int clk_id, unsigned int freq, int dir)
  245. {
  246. struct snd_soc_codec *codec = codec_dai->codec;
  247. u8 pll;
  248. switch (freq) {
  249. case 11289600:
  250. pll = PLL2;
  251. break;
  252. case 12288000:
  253. pll = PLL2 | PLL0;
  254. break;
  255. case 12000000:
  256. pll = PLL2 | PLL1;
  257. break;
  258. case 24000000:
  259. pll = PLL2 | PLL1 | PLL0;
  260. break;
  261. case 13500000:
  262. pll = PLL3 | PLL2;
  263. break;
  264. case 27000000:
  265. pll = PLL3 | PLL2 | PLL0;
  266. break;
  267. default:
  268. return -EINVAL;
  269. }
  270. snd_soc_update_bits(codec, MD_CTL1, PLL_MASK, pll);
  271. return 0;
  272. }
  273. static int ak4642_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
  274. {
  275. struct snd_soc_codec *codec = dai->codec;
  276. u8 data;
  277. u8 bcko;
  278. data = MCKO | PMPLL; /* use MCKO */
  279. bcko = 0;
  280. /* set master/slave audio interface */
  281. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  282. case SND_SOC_DAIFMT_CBM_CFM:
  283. data |= MS;
  284. bcko = BCKO_64;
  285. break;
  286. case SND_SOC_DAIFMT_CBS_CFS:
  287. break;
  288. default:
  289. return -EINVAL;
  290. }
  291. snd_soc_update_bits(codec, PW_MGMT2, MS | MCKO | PMPLL, data);
  292. snd_soc_update_bits(codec, MD_CTL1, BCKO_MASK, bcko);
  293. /* format type */
  294. data = 0;
  295. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  296. case SND_SOC_DAIFMT_LEFT_J:
  297. data = LEFT_J;
  298. break;
  299. case SND_SOC_DAIFMT_I2S:
  300. data = I2S;
  301. break;
  302. /* FIXME
  303. * Please add RIGHT_J / DSP support here
  304. */
  305. default:
  306. return -EINVAL;
  307. break;
  308. }
  309. snd_soc_update_bits(codec, MD_CTL1, DIF_MASK, data);
  310. return 0;
  311. }
  312. static int ak4642_dai_hw_params(struct snd_pcm_substream *substream,
  313. struct snd_pcm_hw_params *params,
  314. struct snd_soc_dai *dai)
  315. {
  316. struct snd_soc_codec *codec = dai->codec;
  317. u8 rate;
  318. switch (params_rate(params)) {
  319. case 7350:
  320. rate = FS2;
  321. break;
  322. case 8000:
  323. rate = 0;
  324. break;
  325. case 11025:
  326. rate = FS2 | FS0;
  327. break;
  328. case 12000:
  329. rate = FS0;
  330. break;
  331. case 14700:
  332. rate = FS2 | FS1;
  333. break;
  334. case 16000:
  335. rate = FS1;
  336. break;
  337. case 22050:
  338. rate = FS2 | FS1 | FS0;
  339. break;
  340. case 24000:
  341. rate = FS1 | FS0;
  342. break;
  343. case 29400:
  344. rate = FS3 | FS2 | FS1;
  345. break;
  346. case 32000:
  347. rate = FS3 | FS1;
  348. break;
  349. case 44100:
  350. rate = FS3 | FS2 | FS1 | FS0;
  351. break;
  352. case 48000:
  353. rate = FS3 | FS1 | FS0;
  354. break;
  355. default:
  356. return -EINVAL;
  357. break;
  358. }
  359. snd_soc_update_bits(codec, MD_CTL2, FS_MASK, rate);
  360. return 0;
  361. }
  362. static int ak4642_set_bias_level(struct snd_soc_codec *codec,
  363. enum snd_soc_bias_level level)
  364. {
  365. switch (level) {
  366. case SND_SOC_BIAS_OFF:
  367. snd_soc_write(codec, PW_MGMT1, 0x00);
  368. break;
  369. default:
  370. snd_soc_update_bits(codec, PW_MGMT1, PMVCM, PMVCM);
  371. break;
  372. }
  373. codec->dapm.bias_level = level;
  374. return 0;
  375. }
  376. static const struct snd_soc_dai_ops ak4642_dai_ops = {
  377. .startup = ak4642_dai_startup,
  378. .shutdown = ak4642_dai_shutdown,
  379. .set_sysclk = ak4642_dai_set_sysclk,
  380. .set_fmt = ak4642_dai_set_fmt,
  381. .hw_params = ak4642_dai_hw_params,
  382. };
  383. static struct snd_soc_dai_driver ak4642_dai = {
  384. .name = "ak4642-hifi",
  385. .playback = {
  386. .stream_name = "Playback",
  387. .channels_min = 1,
  388. .channels_max = 2,
  389. .rates = SNDRV_PCM_RATE_8000_48000,
  390. .formats = SNDRV_PCM_FMTBIT_S16_LE },
  391. .capture = {
  392. .stream_name = "Capture",
  393. .channels_min = 1,
  394. .channels_max = 2,
  395. .rates = SNDRV_PCM_RATE_8000_48000,
  396. .formats = SNDRV_PCM_FMTBIT_S16_LE },
  397. .ops = &ak4642_dai_ops,
  398. .symmetric_rates = 1,
  399. };
  400. static int ak4642_resume(struct snd_soc_codec *codec)
  401. {
  402. snd_soc_cache_sync(codec);
  403. return 0;
  404. }
  405. static int ak4642_probe(struct snd_soc_codec *codec)
  406. {
  407. int ret;
  408. ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_I2C);
  409. if (ret < 0) {
  410. dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
  411. return ret;
  412. }
  413. snd_soc_add_codec_controls(codec, ak4642_snd_controls,
  414. ARRAY_SIZE(ak4642_snd_controls));
  415. ak4642_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  416. return 0;
  417. }
  418. static int ak4642_remove(struct snd_soc_codec *codec)
  419. {
  420. ak4642_set_bias_level(codec, SND_SOC_BIAS_OFF);
  421. return 0;
  422. }
  423. static struct snd_soc_codec_driver soc_codec_dev_ak4642 = {
  424. .probe = ak4642_probe,
  425. .remove = ak4642_remove,
  426. .resume = ak4642_resume,
  427. .set_bias_level = ak4642_set_bias_level,
  428. .reg_cache_default = ak4642_reg, /* ak4642 reg */
  429. .reg_cache_size = ARRAY_SIZE(ak4642_reg), /* ak4642 reg */
  430. .reg_word_size = sizeof(u8),
  431. .dapm_widgets = ak4642_dapm_widgets,
  432. .num_dapm_widgets = ARRAY_SIZE(ak4642_dapm_widgets),
  433. .dapm_routes = ak4642_intercon,
  434. .num_dapm_routes = ARRAY_SIZE(ak4642_intercon),
  435. };
  436. static struct snd_soc_codec_driver soc_codec_dev_ak4648 = {
  437. .probe = ak4642_probe,
  438. .remove = ak4642_remove,
  439. .resume = ak4642_resume,
  440. .set_bias_level = ak4642_set_bias_level,
  441. .reg_cache_default = ak4648_reg, /* ak4648 reg */
  442. .reg_cache_size = ARRAY_SIZE(ak4648_reg), /* ak4648 reg */
  443. .reg_word_size = sizeof(u8),
  444. .dapm_widgets = ak4642_dapm_widgets,
  445. .num_dapm_widgets = ARRAY_SIZE(ak4642_dapm_widgets),
  446. .dapm_routes = ak4642_intercon,
  447. .num_dapm_routes = ARRAY_SIZE(ak4642_intercon),
  448. };
  449. #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
  450. static int ak4642_i2c_probe(struct i2c_client *i2c,
  451. const struct i2c_device_id *id)
  452. {
  453. return snd_soc_register_codec(&i2c->dev,
  454. (struct snd_soc_codec_driver *)id->driver_data,
  455. &ak4642_dai, 1);
  456. }
  457. static int ak4642_i2c_remove(struct i2c_client *client)
  458. {
  459. snd_soc_unregister_codec(&client->dev);
  460. return 0;
  461. }
  462. static const struct i2c_device_id ak4642_i2c_id[] = {
  463. { "ak4642", (kernel_ulong_t)&soc_codec_dev_ak4642 },
  464. { "ak4643", (kernel_ulong_t)&soc_codec_dev_ak4642 },
  465. { "ak4648", (kernel_ulong_t)&soc_codec_dev_ak4648 },
  466. { }
  467. };
  468. MODULE_DEVICE_TABLE(i2c, ak4642_i2c_id);
  469. static struct i2c_driver ak4642_i2c_driver = {
  470. .driver = {
  471. .name = "ak4642-codec",
  472. .owner = THIS_MODULE,
  473. },
  474. .probe = ak4642_i2c_probe,
  475. .remove = ak4642_i2c_remove,
  476. .id_table = ak4642_i2c_id,
  477. };
  478. #endif
  479. static int __init ak4642_modinit(void)
  480. {
  481. int ret = 0;
  482. #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
  483. ret = i2c_add_driver(&ak4642_i2c_driver);
  484. #endif
  485. return ret;
  486. }
  487. module_init(ak4642_modinit);
  488. static void __exit ak4642_exit(void)
  489. {
  490. #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
  491. i2c_del_driver(&ak4642_i2c_driver);
  492. #endif
  493. }
  494. module_exit(ak4642_exit);
  495. MODULE_DESCRIPTION("Soc AK4642 driver");
  496. MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>");
  497. MODULE_LICENSE("GPL");