1 ## ia32 opcode tables - thx to sandpile.org and a little bit of alcohol

2 ## (that also means that this potentially will contain errors)

3

46 </table>

47 <hr/><a name="_details"></a><h2>Detailed Description</h2>

48 <dl class="author"><dt><b>Author:</b></dt><dd>Alex &lt;<a href="mailto:aimmig2@hotmail.com">aimmig2@hotmail.com</a>&gt; @url <a href="http://www.sandpile.org/ia32/cpuid.htm">http://www.sandpile.org/ia32/cpuid.htm</a> for more information on what each CPUID function does and what each bit returned represents </dd></dl>

49

50 <p>Definition at line <a class="el" href="_system_architecture_8h_source.html#l00015">15</a> of file <a class="el" href="_system_architecture_8h_source.html">SystemArchitecture.h</a>.</p>

168 /* AltiVec should have been handled above */

169 /* now comes the parsing of the cpuid on x86 hardware

170 * see http://www.sandpile.org/ia32/cpuid.htm for what which bit is

171 */

172 # ifdef __SSE2__

29 /* CPUID records gathered from other machines, used to virtualize CPUID

30 * CPUID is a bundle of joy. See these to get started:

31 * - http://www.sandpile.org/x86/cpuid.htm

32 * - http://www.intel.com/content/www/us/en/processors/processor-identification-cpuid-instruction-note.html

33 * Try not to cry.

4 +++ b/src/os.cc

5 @@ -149,7 +149,16 @@ void OsLayer::GetFeatures() {

6 // http://www.sandpile.org/ia32/cpuid.htm

7 int ax, bx, cx, dx;

8 __asm__ __volatile__ (

10 /**

11 * @author Alex <aimmig2@hotmail.com>

12 * @url http://www.sandpile.org/ia32/cpuid.htm for more information on what each CPUID function does and what

13 * each bit returned represents

14 */

172 #define SMM_REVISION_ID (0x00000000 | SMM_SMBASE_RELOCATION)

173

174 // source for Intel P6 SMM save state map used: www.sandpile.org

175

176 #define SMRAM_OFFSET_CR0 0x7ffc

49 * x86 Instruction reference - simple site - [http://ref.x86asm.net/](http://ref.x86asm.net)

50 * AMD64 Programmer’s reference, Vol 3 - [https://support.amd.com/TechDocs/24594.pdf](https://support.amd.com/TechDocs/24594.pdf) (PDF)

51 * Sandpile - [http://sandpile.org](http://sandpile.org)

52 * Navigable parsed version of Intel 64 reference - [https://github.com/zneak/x86doc](https://github.com/zneak/x86doc)

53

6 // http://ref.x86asm.net/coder32-abc.html

7 // http://ref.x86asm.net/coder32.html

8 // http://www.sandpile.org/

9 // https://www-user.tu-chemnitz.de/~heha/viewchm.php/hs/x86.chm/x86.htm

10 // http://www.felixcloutier.com/x86/

28 // wrappers from cpuid.h simplify error and parameter handling. cpuid.h also has some defines and

29 // useful comments to figure out what can be queried. More comprehensive info:

30 // https://www.sandpile.org/x86/cpuid.htm

31

32 // Return the size of the XSave area on this cpu.

11 Its source code is under LGPL3 license with a "Makefile builder" and headers for following languages : C/C++, C#, Python, Delphi, PureBasic, masm32, masm64, nasm(x86 and x64), fasm(x86 and x64), GoAsm(x86 and x64).

12

13 BeaEngine has been implemented using opcode tables from the intel documentation and tables from Christian Ludloff website [www.sandpile.org](http://www.sandpile.org)

14

15 ## LICENSE

10 Its source code is under LGPL3 license with a "Makefile builder" and headers for following languages : C/C++, C#, Python, Delphi, PureBasic, masm32, masm64, nasm(x86 and x64), fasm(x86 and x64), GoAsm(x86 and x64).

11

12 BeaEngine has been implemented using opcode tables from the intel documentation and tables from Christian Ludloff website [www.sandpile.org](http://www.sandpile.org)

13

14

28

29 // https://github.com/Mysticial/Flops/blob/e571da6e94f7b6d2d1a90e87b19398c5c4de4375/version1/source/cpuid.c

30 // http://www.sandpile.org/x86/cpuid.htm

31

32 #ifndef _cpuid_c

6 void cpuid_get_features();

7

8 //As per CPU Features manual at: http://sandpile.org/ia32/cpuid.htm

9 typedef struct {

10 unsigned int stuff_I_dont_care_about: 11;

36 uint32_t abcd[4] = {0,0,0,0};

37

38 // You might want to refer to http://www.sandpile.org/x86/cpuid.htm

39

40 cpuid(abcd);

153

154 /* Decode Intel TLB and cache info descriptors */

155 //TODO : Errata workaround. http://www.sandpile.org/post/msgs/20002736.htm

156 static void decode_Intel_cache(int des, struct cpudata *cpu, int output,

157 struct _cache_table *table)

30

31 As for web links to manuals, I found out three interesting links :

32 - http://www.sandpile.org/ : the most complete one since it contains AVX3 instructions. I am also attempting to put the opcode maps into one page and perhaps I will use it to extract instructions details to make a source file to describe all x86 isntructions I need.

33 - http://www.felixcloutier.com/x86/ : this one is normally auto-generated from Intel manuals but it lacks opcode maps and AVX3 instructions.

34 - http://ref.x86asm.net : this one is probably the most informative except that it does not contain AVX+ instructions.

10

11 #References:

12 # http://www.sandpile.org/ia32/cpuid.htm

13 # http://download.intel.com/design/processor/applnots/24161831.pdf

14