/*
 * pic18f23k22.c - device specific definitions
 *
 * This file is part of the GNU PIC library for SDCC,
 * originally devised by Vangelis Rokas <vrokas AT otenet.gr>
 *
 * It has been automatically generated by inc2h-pic16.pl,
 * (c) 2007 by Raphael Neider <rneider AT web.de>
 */

#include <pic18f23k22.h>


__sfr __at (0xF38) ANSELA;
volatile __ANSELAbits_t __at (0xF38) ANSELAbits;

__sfr __at (0xF39) ANSELB;
volatile __ANSELBbits_t __at (0xF39) ANSELBbits;

__sfr __at (0xF3A) ANSELC;
volatile __ANSELCbits_t __at (0xF3A) ANSELCbits;

__sfr __at (0xF3D) PMD2;
volatile __PMD2bits_t __at (0xF3D) PMD2bits;

__sfr __at (0xF3E) PMD1;
volatile __PMD1bits_t __at (0xF3E) PMD1bits;

__sfr __at (0xF3F) PMD0;
volatile __PMD0bits_t __at (0xF3F) PMD0bits;

__sfr __at (0xF40) DACCON1;
volatile __DACCON1bits_t __at (0xF40) DACCON1bits;

__sfr __at (0xF40) VREFCON2;
volatile __VREFCON2bits_t __at (0xF40) VREFCON2bits;

__sfr __at (0xF41) DACCON0;
volatile __DACCON0bits_t __at (0xF41) DACCON0bits;

__sfr __at (0xF41) VREFCON1;
volatile __VREFCON1bits_t __at (0xF41) VREFCON1bits;

__sfr __at (0xF42) FVRCON;
volatile __FVRCONbits_t __at (0xF42) FVRCONbits;

__sfr __at (0xF42) VREFCON0;
volatile __VREFCON0bits_t __at (0xF42) VREFCON0bits;

__sfr __at (0xF43) CTMUICON;
volatile __CTMUICONbits_t __at (0xF43) CTMUICONbits;

__sfr __at (0xF43) CTMUICONH;
volatile __CTMUICONHbits_t __at (0xF43) CTMUICONHbits;

__sfr __at (0xF44) CTMUCON1;
volatile __CTMUCON1bits_t __at (0xF44) CTMUCON1bits;

__sfr __at (0xF44) CTMUCONL;
volatile __CTMUCONLbits_t __at (0xF44) CTMUCONLbits;

__sfr __at (0xF45) CTMUCON0;
volatile __CTMUCON0bits_t __at (0xF45) CTMUCON0bits;

__sfr __at (0xF45) CTMUCONH;
volatile __CTMUCONHbits_t __at (0xF45) CTMUCONHbits;

__sfr __at (0xF46) SRCON1;
volatile __SRCON1bits_t __at (0xF46) SRCON1bits;

__sfr __at (0xF47) SRCON0;
volatile __SRCON0bits_t __at (0xF47) SRCON0bits;

__sfr __at (0xF48) CCPTMRS1;
volatile __CCPTMRS1bits_t __at (0xF48) CCPTMRS1bits;

__sfr __at (0xF49) CCPTMRS0;
volatile __CCPTMRS0bits_t __at (0xF49) CCPTMRS0bits;

__sfr __at (0xF4A) T6CON;
volatile __T6CONbits_t __at (0xF4A) T6CONbits;

__sfr __at (0xF4B) PR6;

__sfr __at (0xF4C) TMR6;

__sfr __at (0xF4D) T5GCON;
volatile __T5GCONbits_t __at (0xF4D) T5GCONbits;

__sfr __at (0xF4E) T5CON;
volatile __T5CONbits_t __at (0xF4E) T5CONbits;

__sfr __at (0xF4F) TMR5L;

__sfr __at (0xF50) TMR5H;

__sfr __at (0xF51) T4CON;
volatile __T4CONbits_t __at (0xF51) T4CONbits;

__sfr __at (0xF52) PR4;

__sfr __at (0xF53) TMR4;

__sfr __at (0xF54) CCP5CON;
volatile __CCP5CONbits_t __at (0xF54) CCP5CONbits;

__sfr __at (0xF55) CCPR5;

__sfr __at (0xF55) CCPR5L;

__sfr __at (0xF56) CCPR5H;

__sfr __at (0xF57) CCP4CON;
volatile __CCP4CONbits_t __at (0xF57) CCP4CONbits;

__sfr __at (0xF58) CCPR4;

__sfr __at (0xF58) CCPR4L;

__sfr __at (0xF59) CCPR4H;

__sfr __at (0xF5A) PSTR3CON;
volatile __PSTR3CONbits_t __at (0xF5A) PSTR3CONbits;

__sfr __at (0xF5B) CCP3AS;
volatile __CCP3ASbits_t __at (0xF5B) CCP3ASbits;

__sfr __at (0xF5B) ECCP3AS;
volatile __ECCP3ASbits_t __at (0xF5B) ECCP3ASbits;

__sfr __at (0xF5C) PWM3CON;
volatile __PWM3CONbits_t __at (0xF5C) PWM3CONbits;

__sfr __at (0xF5D) CCP3CON;
volatile __CCP3CONbits_t __at (0xF5D) CCP3CONbits;

__sfr __at (0xF5E) CCPR3;

__sfr __at (0xF5E) CCPR3L;

__sfr __at (0xF5F) CCPR3H;

__sfr __at (0xF60) SLRCON;
volatile __SLRCONbits_t __at (0xF60) SLRCONbits;

__sfr __at (0xF61) WPUB;
volatile __WPUBbits_t __at (0xF61) WPUBbits;

__sfr __at (0xF62) IOCB;
volatile __IOCBbits_t __at (0xF62) IOCBbits;

__sfr __at (0xF63) PSTR2CON;
volatile __PSTR2CONbits_t __at (0xF63) PSTR2CONbits;

__sfr __at (0xF64) CCP2AS;
volatile __CCP2ASbits_t __at (0xF64) CCP2ASbits;

__sfr __at (0xF64) ECCP2AS;
volatile __ECCP2ASbits_t __at (0xF64) ECCP2ASbits;

__sfr __at (0xF65) PWM2CON;
volatile __PWM2CONbits_t __at (0xF65) PWM2CONbits;

__sfr __at (0xF66) CCP2CON;
volatile __CCP2CONbits_t __at (0xF66) CCP2CONbits;

__sfr __at (0xF67) CCPR2;

__sfr __at (0xF67) CCPR2L;

__sfr __at (0xF68) CCPR2H;

__sfr __at (0xF69) SSP2CON3;
volatile __SSP2CON3bits_t __at (0xF69) SSP2CON3bits;

__sfr __at (0xF6A) SSP2MSK;
volatile __SSP2MSKbits_t __at (0xF6A) SSP2MSKbits;

__sfr __at (0xF6B) SSP2CON2;
volatile __SSP2CON2bits_t __at (0xF6B) SSP2CON2bits;

__sfr __at (0xF6C) SSP2CON1;
volatile __SSP2CON1bits_t __at (0xF6C) SSP2CON1bits;

__sfr __at (0xF6D) SSP2STAT;
volatile __SSP2STATbits_t __at (0xF6D) SSP2STATbits;

__sfr __at (0xF6E) SSP2ADD;

__sfr __at (0xF6F) SSP2BUF;

__sfr __at (0xF70) BAUD2CON;
volatile __BAUD2CONbits_t __at (0xF70) BAUD2CONbits;

__sfr __at (0xF70) BAUDCON2;
volatile __BAUDCON2bits_t __at (0xF70) BAUDCON2bits;

__sfr __at (0xF71) RC2STA;
volatile __RC2STAbits_t __at (0xF71) RC2STAbits;

__sfr __at (0xF71) RCSTA2;
volatile __RCSTA2bits_t __at (0xF71) RCSTA2bits;

__sfr __at (0xF72) TX2STA;
volatile __TX2STAbits_t __at (0xF72) TX2STAbits;

__sfr __at (0xF72) TXSTA2;
volatile __TXSTA2bits_t __at (0xF72) TXSTA2bits;

__sfr __at (0xF73) TX2REG;

__sfr __at (0xF73) TXREG2;

__sfr __at (0xF74) RC2REG;

__sfr __at (0xF74) RCREG2;

__sfr __at (0xF75) SP2BRG;

__sfr __at (0xF75) SPBRG2;

__sfr __at (0xF76) SP2BRGH;

__sfr __at (0xF76) SPBRGH2;

__sfr __at (0xF77) CM12CON;
volatile __CM12CONbits_t __at (0xF77) CM12CONbits;

__sfr __at (0xF77) CM2CON1;
volatile __CM2CON1bits_t __at (0xF77) CM2CON1bits;

__sfr __at (0xF78) CM2CON;
volatile __CM2CONbits_t __at (0xF78) CM2CONbits;

__sfr __at (0xF78) CM2CON0;
volatile __CM2CON0bits_t __at (0xF78) CM2CON0bits;

__sfr __at (0xF79) CM1CON;
volatile __CM1CONbits_t __at (0xF79) CM1CONbits;

__sfr __at (0xF79) CM1CON0;
volatile __CM1CON0bits_t __at (0xF79) CM1CON0bits;

__sfr __at (0xF7A) PIE4;
volatile __PIE4bits_t __at (0xF7A) PIE4bits;

__sfr __at (0xF7B) PIR4;
volatile __PIR4bits_t __at (0xF7B) PIR4bits;

__sfr __at (0xF7C) IPR4;
volatile __IPR4bits_t __at (0xF7C) IPR4bits;

__sfr __at (0xF7D) PIE5;
volatile __PIE5bits_t __at (0xF7D) PIE5bits;

__sfr __at (0xF7E) PIR5;
volatile __PIR5bits_t __at (0xF7E) PIR5bits;

__sfr __at (0xF7F) IPR5;
volatile __IPR5bits_t __at (0xF7F) IPR5bits;

__sfr __at (0xF80) PORTA;
volatile __PORTAbits_t __at (0xF80) PORTAbits;

__sfr __at (0xF81) PORTB;
volatile __PORTBbits_t __at (0xF81) PORTBbits;

__sfr __at (0xF82) PORTC;
volatile __PORTCbits_t __at (0xF82) PORTCbits;

__sfr __at (0xF84) PORTE;
volatile __PORTEbits_t __at (0xF84) PORTEbits;

__sfr __at (0xF89) LATA;
volatile __LATAbits_t __at (0xF89) LATAbits;

__sfr __at (0xF8A) LATB;
volatile __LATBbits_t __at (0xF8A) LATBbits;

__sfr __at (0xF8B) LATC;
volatile __LATCbits_t __at (0xF8B) LATCbits;

__sfr __at (0xF92) DDRA;
volatile __DDRAbits_t __at (0xF92) DDRAbits;

__sfr __at (0xF92) TRISA;
volatile __TRISAbits_t __at (0xF92) TRISAbits;

__sfr __at (0xF93) DDRB;
volatile __DDRBbits_t __at (0xF93) DDRBbits;

__sfr __at (0xF93) TRISB;
volatile __TRISBbits_t __at (0xF93) TRISBbits;

__sfr __at (0xF94) DDRC;
volatile __DDRCbits_t __at (0xF94) DDRCbits;

__sfr __at (0xF94) TRISC;
volatile __TRISCbits_t __at (0xF94) TRISCbits;

__sfr __at (0xF96) TRISE;
volatile __TRISEbits_t __at (0xF96) TRISEbits;

__sfr __at (0xF9B) OSCTUNE;
volatile __OSCTUNEbits_t __at (0xF9B) OSCTUNEbits;

__sfr __at (0xF9C) HLVDCON;
volatile __HLVDCONbits_t __at (0xF9C) HLVDCONbits;

__sfr __at (0xF9C) LVDCON;
volatile __LVDCONbits_t __at (0xF9C) LVDCONbits;

__sfr __at (0xF9D) PIE1;
volatile __PIE1bits_t __at (0xF9D) PIE1bits;

__sfr __at (0xF9E) PIR1;
volatile __PIR1bits_t __at (0xF9E) PIR1bits;

__sfr __at (0xF9F) IPR1;
volatile __IPR1bits_t __at (0xF9F) IPR1bits;

__sfr __at (0xFA0) PIE2;
volatile __PIE2bits_t __at (0xFA0) PIE2bits;

__sfr __at (0xFA1) PIR2;
volatile __PIR2bits_t __at (0xFA1) PIR2bits;

__sfr __at (0xFA2) IPR2;
volatile __IPR2bits_t __at (0xFA2) IPR2bits;

__sfr __at (0xFA3) PIE3;
volatile __PIE3bits_t __at (0xFA3) PIE3bits;

__sfr __at (0xFA4) PIR3;
volatile __PIR3bits_t __at (0xFA4) PIR3bits;

__sfr __at (0xFA5) IPR3;
volatile __IPR3bits_t __at (0xFA5) IPR3bits;

__sfr __at (0xFA6) EECON1;
volatile __EECON1bits_t __at (0xFA6) EECON1bits;

__sfr __at (0xFA7) EECON2;

__sfr __at (0xFA8) EEDATA;

__sfr __at (0xFA9) EEADR;
volatile __EEADRbits_t __at (0xFA9) EEADRbits;

__sfr __at (0xFAB) RC1STA;
volatile __RC1STAbits_t __at (0xFAB) RC1STAbits;

__sfr __at (0xFAB) RCSTA;
volatile __RCSTAbits_t __at (0xFAB) RCSTAbits;

__sfr __at (0xFAB) RCSTA1;
volatile __RCSTA1bits_t __at (0xFAB) RCSTA1bits;

__sfr __at (0xFAC) TX1STA;
volatile __TX1STAbits_t __at (0xFAC) TX1STAbits;

__sfr __at (0xFAC) TXSTA;
volatile __TXSTAbits_t __at (0xFAC) TXSTAbits;

__sfr __at (0xFAC) TXSTA1;
volatile __TXSTA1bits_t __at (0xFAC) TXSTA1bits;

__sfr __at (0xFAD) TX1REG;

__sfr __at (0xFAD) TXREG;

__sfr __at (0xFAD) TXREG1;

__sfr __at (0xFAE) RC1REG;

__sfr __at (0xFAE) RCREG;

__sfr __at (0xFAE) RCREG1;

__sfr __at (0xFAF) SP1BRG;

__sfr __at (0xFAF) SPBRG;

__sfr __at (0xFAF) SPBRG1;

__sfr __at (0xFB0) SP1BRGH;

__sfr __at (0xFB0) SPBRGH;

__sfr __at (0xFB0) SPBRGH1;

__sfr __at (0xFB1) T3CON;
volatile __T3CONbits_t __at (0xFB1) T3CONbits;

__sfr __at (0xFB2) TMR3L;

__sfr __at (0xFB3) TMR3H;

__sfr __at (0xFB4) T3GCON;
volatile __T3GCONbits_t __at (0xFB4) T3GCONbits;

__sfr __at (0xFB6) ECCP1AS;
volatile __ECCP1ASbits_t __at (0xFB6) ECCP1ASbits;

__sfr __at (0xFB6) ECCPAS;
volatile __ECCPASbits_t __at (0xFB6) ECCPASbits;

__sfr __at (0xFB7) PWM1CON;
volatile __PWM1CONbits_t __at (0xFB7) PWM1CONbits;

__sfr __at (0xFB7) PWMCON;
volatile __PWMCONbits_t __at (0xFB7) PWMCONbits;

__sfr __at (0xFB8) BAUD1CON;
volatile __BAUD1CONbits_t __at (0xFB8) BAUD1CONbits;

__sfr __at (0xFB8) BAUDCON;
volatile __BAUDCONbits_t __at (0xFB8) BAUDCONbits;

__sfr __at (0xFB8) BAUDCON1;
volatile __BAUDCON1bits_t __at (0xFB8) BAUDCON1bits;

__sfr __at (0xFB8) BAUDCTL;
volatile __BAUDCTLbits_t __at (0xFB8) BAUDCTLbits;

__sfr __at (0xFB9) PSTR1CON;
volatile __PSTR1CONbits_t __at (0xFB9) PSTR1CONbits;

__sfr __at (0xFB9) PSTRCON;
volatile __PSTRCONbits_t __at (0xFB9) PSTRCONbits;

__sfr __at (0xFBA) T2CON;
volatile __T2CONbits_t __at (0xFBA) T2CONbits;

__sfr __at (0xFBB) PR2;

__sfr __at (0xFBC) TMR2;

__sfr __at (0xFBD) CCP1CON;
volatile __CCP1CONbits_t __at (0xFBD) CCP1CONbits;

__sfr __at (0xFBE) CCPR1;

__sfr __at (0xFBE) CCPR1L;

__sfr __at (0xFBF) CCPR1H;

__sfr __at (0xFC0) ADCON2;
volatile __ADCON2bits_t __at (0xFC0) ADCON2bits;

__sfr __at (0xFC1) ADCON1;
volatile __ADCON1bits_t __at (0xFC1) ADCON1bits;

__sfr __at (0xFC2) ADCON0;
volatile __ADCON0bits_t __at (0xFC2) ADCON0bits;

__sfr __at (0xFC3) ADRES;

__sfr __at (0xFC3) ADRESL;

__sfr __at (0xFC4) ADRESH;

__sfr __at (0xFC5) SSP1CON2;
volatile __SSP1CON2bits_t __at (0xFC5) SSP1CON2bits;

__sfr __at (0xFC5) SSPCON2;
volatile __SSPCON2bits_t __at (0xFC5) SSPCON2bits;

__sfr __at (0xFC6) SSP1CON1;
volatile __SSP1CON1bits_t __at (0xFC6) SSP1CON1bits;

__sfr __at (0xFC6) SSPCON1;
volatile __SSPCON1bits_t __at (0xFC6) SSPCON1bits;

__sfr __at (0xFC7) SSP1STAT;
volatile __SSP1STATbits_t __at (0xFC7) SSP1STATbits;

__sfr __at (0xFC7) SSPSTAT;
volatile __SSPSTATbits_t __at (0xFC7) SSPSTATbits;

__sfr __at (0xFC8) SSP1ADD;

__sfr __at (0xFC8) SSPADD;

__sfr __at (0xFC9) SSP1BUF;

__sfr __at (0xFC9) SSPBUF;

__sfr __at (0xFCA) SSP1MSK;
volatile __SSP1MSKbits_t __at (0xFCA) SSP1MSKbits;

__sfr __at (0xFCA) SSPMSK;
volatile __SSPMSKbits_t __at (0xFCA) SSPMSKbits;

__sfr __at (0xFCB) SSP1CON3;
volatile __SSP1CON3bits_t __at (0xFCB) SSP1CON3bits;

__sfr __at (0xFCB) SSPCON3;
volatile __SSPCON3bits_t __at (0xFCB) SSPCON3bits;

__sfr __at (0xFCC) T1GCON;
volatile __T1GCONbits_t __at (0xFCC) T1GCONbits;

__sfr __at (0xFCD) T1CON;
volatile __T1CONbits_t __at (0xFCD) T1CONbits;

__sfr __at (0xFCE) TMR1L;

__sfr __at (0xFCF) TMR1H;

__sfr __at (0xFD0) RCON;
volatile __RCONbits_t __at (0xFD0) RCONbits;

__sfr __at (0xFD1) WDTCON;
volatile __WDTCONbits_t __at (0xFD1) WDTCONbits;

__sfr __at (0xFD2) OSCCON2;
volatile __OSCCON2bits_t __at (0xFD2) OSCCON2bits;

__sfr __at (0xFD3) OSCCON;
volatile __OSCCONbits_t __at (0xFD3) OSCCONbits;

__sfr __at (0xFD5) T0CON;
volatile __T0CONbits_t __at (0xFD5) T0CONbits;

__sfr __at (0xFD6) TMR0L;

__sfr __at (0xFD7) TMR0H;

__sfr __at (0xFD8) STATUS;
volatile __STATUSbits_t __at (0xFD8) STATUSbits;

__sfr __at (0xFD9) FSR2L;

__sfr __at (0xFDA) FSR2H;

__sfr __at (0xFDB) PLUSW2;

__sfr __at (0xFDC) PREINC2;

__sfr __at (0xFDD) POSTDEC2;

__sfr __at (0xFDE) POSTINC2;

__sfr __at (0xFDF) INDF2;

__sfr __at (0xFE0) BSR;

__sfr __at (0xFE1) FSR1L;

__sfr __at (0xFE2) FSR1H;

__sfr __at (0xFE3) PLUSW1;

__sfr __at (0xFE4) PREINC1;

__sfr __at (0xFE5) POSTDEC1;

__sfr __at (0xFE6) POSTINC1;

__sfr __at (0xFE7) INDF1;

__sfr __at (0xFE8) WREG;

__sfr __at (0xFE9) FSR0L;

__sfr __at (0xFEA) FSR0H;

__sfr __at (0xFEB) PLUSW0;

__sfr __at (0xFEC) PREINC0;

__sfr __at (0xFED) POSTDEC0;

__sfr __at (0xFEE) POSTINC0;

__sfr __at (0xFEF) INDF0;

__sfr __at (0xFF0) INTCON3;
volatile __INTCON3bits_t __at (0xFF0) INTCON3bits;

__sfr __at (0xFF1) INTCON2;
volatile __INTCON2bits_t __at (0xFF1) INTCON2bits;

__sfr __at (0xFF2) INTCON;
volatile __INTCONbits_t __at (0xFF2) INTCONbits;

__sfr __at (0xFF3) PROD;

__sfr __at (0xFF3) PRODL;

__sfr __at (0xFF4) PRODH;

__sfr __at (0xFF5) TABLAT;

__sfr __at (0xFF6) TBLPTR;

__sfr __at (0xFF6) TBLPTRL;

__sfr __at (0xFF7) TBLPTRH;

__sfr __at (0xFF8) TBLPTRU;

__sfr __at (0xFF9) PC;

__sfr __at (0xFF9) PCL;

__sfr __at (0xFFA) PCLATH;

__sfr __at (0xFFB) PCLATU;

__sfr __at (0xFFC) STKPTR;
volatile __STKPTRbits_t __at (0xFFC) STKPTRbits;

__sfr __at (0xFFD) TOS;

__sfr __at (0xFFD) TOSL;

__sfr __at (0xFFE) TOSH;

__sfr __at (0xFFF) TOSU;