/drivers/media/video/samsung/fimc/fimc_capture.c

https://github.com/dastin1015/android_kernel_samsung_smdk4210 · C · 3475 lines · 2789 code · 511 blank · 175 comment · 619 complexity · d33bd73fb31f967958d3b8e70bb8acec MD5 · raw file

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  1. /* linux/drivers/media/video/samsung/fimc_capture.c
  2. *
  3. * Copyright (c) 2010 Samsung Electronics Co., Ltd.
  4. * http://www.samsung.com/
  5. *
  6. * V4L2 Capture device support file for Samsung Camera Interface (FIMC) driver
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #include <linux/slab.h>
  13. #include <linux/bootmem.h>
  14. #include <linux/string.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/videodev2.h>
  17. #include <linux/videodev2_exynos_media.h>
  18. #include <linux/videodev2_exynos_camera.h>
  19. #include <linux/clk.h>
  20. #include <linux/mm.h>
  21. #include <linux/dma-mapping.h>
  22. #include <linux/io.h>
  23. #include <linux/uaccess.h>
  24. #include <plat/media.h>
  25. #include <plat/clock.h>
  26. #include <plat/fimc.h>
  27. #include <linux/delay.h>
  28. #include <asm/cacheflush.h>
  29. #include <linux/pm_qos_params.h>
  30. #include "fimc.h"
  31. static struct pm_qos_request_list bus_qos_pm_qos_req;
  32. static const struct v4l2_fmtdesc capture_fmts[] = {
  33. {
  34. .index = 0,
  35. .type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
  36. .flags = FORMAT_FLAGS_PACKED,
  37. .description = "RGB-5-6-5",
  38. .pixelformat = V4L2_PIX_FMT_RGB565,
  39. }, {
  40. .index = 1,
  41. .type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
  42. .flags = FORMAT_FLAGS_PACKED,
  43. .description = "RGB-8-8-8, unpacked 24 bpp",
  44. .pixelformat = V4L2_PIX_FMT_RGB32,
  45. }, {
  46. .index = 2,
  47. .type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
  48. .flags = FORMAT_FLAGS_PACKED,
  49. .description = "YUV 4:2:2 packed, YCbYCr",
  50. .pixelformat = V4L2_PIX_FMT_YUYV,
  51. }, {
  52. .index = 3,
  53. .type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
  54. .flags = FORMAT_FLAGS_PACKED,
  55. .description = "YUV 4:2:2 packed, CbYCrY",
  56. .pixelformat = V4L2_PIX_FMT_UYVY,
  57. }, {
  58. .index = 4,
  59. .type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
  60. .flags = FORMAT_FLAGS_PACKED,
  61. .description = "YUV 4:2:2 packed, CrYCbY",
  62. .pixelformat = V4L2_PIX_FMT_VYUY,
  63. }, {
  64. .index = 5,
  65. .type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
  66. .flags = FORMAT_FLAGS_PACKED,
  67. .description = "YUV 4:2:2 packed, YCrYCb",
  68. .pixelformat = V4L2_PIX_FMT_YVYU,
  69. }, {
  70. .index = 6,
  71. .type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
  72. .flags = FORMAT_FLAGS_PLANAR,
  73. .description = "YUV 4:2:2 planar, Y/Cb/Cr",
  74. .pixelformat = V4L2_PIX_FMT_YUV422P,
  75. }, {
  76. .index = 7,
  77. .type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
  78. .flags = FORMAT_FLAGS_PLANAR,
  79. .description = "YUV 4:2:0 planar, Y/CbCr",
  80. .pixelformat = V4L2_PIX_FMT_NV12,
  81. }, {
  82. .index = 8,
  83. .type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
  84. .flags = FORMAT_FLAGS_PLANAR,
  85. .description = "YUV 4:2:0 planar, Y/CbCr, Tiled",
  86. .pixelformat = V4L2_PIX_FMT_NV12T,
  87. }, {
  88. .index = 9,
  89. .type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
  90. .flags = FORMAT_FLAGS_PLANAR,
  91. .description = "YUV 4:2:0 planar, Y/CrCb",
  92. .pixelformat = V4L2_PIX_FMT_NV21,
  93. }, {
  94. .index = 10,
  95. .type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
  96. .flags = FORMAT_FLAGS_PLANAR,
  97. .description = "YUV 4:2:2 planar, Y/CbCr",
  98. .pixelformat = V4L2_PIX_FMT_NV16,
  99. }, {
  100. .index = 11,
  101. .type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
  102. .flags = FORMAT_FLAGS_PLANAR,
  103. .description = "YUV 4:2:2 planar, Y/CrCb",
  104. .pixelformat = V4L2_PIX_FMT_NV61,
  105. }, {
  106. .index = 12,
  107. .type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
  108. .flags = FORMAT_FLAGS_PLANAR,
  109. .description = "YUV 4:2:0 planar, Y/Cb/Cr",
  110. .pixelformat = V4L2_PIX_FMT_YUV420,
  111. }, {
  112. .index = 13,
  113. .type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
  114. .flags = FORMAT_FLAGS_PLANAR,
  115. .description = "YUV 4:2:0 planar, Y/Cr/Cb",
  116. .pixelformat = V4L2_PIX_FMT_YVU420,
  117. }, {
  118. .index = 14,
  119. .type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
  120. .description = "JPEG encoded data",
  121. .pixelformat = V4L2_PIX_FMT_JPEG,
  122. }, {
  123. .index = 15,
  124. .type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
  125. .description = "Interleaved data",
  126. .pixelformat = V4L2_PIX_FMT_INTERLEAVED,
  127. },
  128. };
  129. static const struct v4l2_queryctrl fimc_controls[] = {
  130. {
  131. .id = V4L2_CID_ROTATION,
  132. .type = V4L2_CTRL_TYPE_BOOLEAN,
  133. .name = "Roataion",
  134. .minimum = 0,
  135. .maximum = 270,
  136. .step = 90,
  137. .default_value = 0,
  138. }, {
  139. .id = V4L2_CID_HFLIP,
  140. .type = V4L2_CTRL_TYPE_BOOLEAN,
  141. .name = "Horizontal Flip",
  142. .minimum = 0,
  143. .maximum = 1,
  144. .step = 1,
  145. .default_value = 0,
  146. }, {
  147. .id = V4L2_CID_VFLIP,
  148. .type = V4L2_CTRL_TYPE_BOOLEAN,
  149. .name = "Vertical Flip",
  150. .minimum = 0,
  151. .maximum = 1,
  152. .step = 1,
  153. .default_value = 0,
  154. }, {
  155. .id = V4L2_CID_PADDR_Y,
  156. .type = V4L2_CTRL_TYPE_BOOLEAN,
  157. .name = "Physical address Y",
  158. .minimum = 0,
  159. .maximum = 1,
  160. .step = 1,
  161. .default_value = 0,
  162. .flags = V4L2_CTRL_FLAG_READ_ONLY,
  163. }, {
  164. .id = V4L2_CID_PADDR_CB,
  165. .type = V4L2_CTRL_TYPE_BOOLEAN,
  166. .name = "Physical address Cb",
  167. .minimum = 0,
  168. .maximum = 1,
  169. .step = 1,
  170. .default_value = 0,
  171. .flags = V4L2_CTRL_FLAG_READ_ONLY,
  172. }, {
  173. .id = V4L2_CID_PADDR_CR,
  174. .type = V4L2_CTRL_TYPE_BOOLEAN,
  175. .name = "Physical address Cr",
  176. .minimum = 0,
  177. .maximum = 1,
  178. .step = 1,
  179. .default_value = 0,
  180. .flags = V4L2_CTRL_FLAG_READ_ONLY,
  181. }, {
  182. .id = V4L2_CID_PADDR_CBCR,
  183. .type = V4L2_CTRL_TYPE_BOOLEAN,
  184. .name = "Physical address CbCr",
  185. .minimum = 0,
  186. .maximum = 1,
  187. .step = 1,
  188. .default_value = 0,
  189. .flags = V4L2_CTRL_FLAG_READ_ONLY,
  190. }, {
  191. .id = V4L2_CID_CACHEABLE,
  192. .type = V4L2_CTRL_TYPE_BOOLEAN,
  193. .name = "Cacheable",
  194. .minimum = 0,
  195. .maximum = 1,
  196. .step = 1,
  197. .default_value = 0,
  198. },
  199. };
  200. #ifdef CONFIG_MACH_GC1
  201. static bool leave_power;
  202. #endif
  203. #ifndef CONFIG_VIDEO_FIMC_MIPI
  204. void s3c_csis_start(int csis_id, int lanes, int settle, \
  205. int align, int width, int height, int pixel_format) {}
  206. void s3c_csis_stop(int csis_id) {}
  207. void s3c_csis_enable_pktdata(int csis_id, bool enable) {}
  208. #endif
  209. static int fimc_init_camera(struct fimc_control *ctrl)
  210. {
  211. struct fimc_global *fimc = get_fimc_dev();
  212. struct s3c_platform_fimc *pdata;
  213. struct s3c_platform_camera *cam;
  214. int ret = 0, retry_cnt = 0;
  215. #if (defined(CONFIG_EXYNOS_DEV_PD) && defined(CONFIG_PM_RUNTIME))
  216. struct platform_device *pdev = to_platform_device(ctrl->dev);
  217. #endif
  218. pdata = to_fimc_plat(ctrl->dev);
  219. cam = ctrl->cam;
  220. /* do nothing if already initialized */
  221. if (ctrl->cam->initialized)
  222. return 0;
  223. #if (defined(CONFIG_EXYNOS_DEV_PD) && defined(CONFIG_PM_RUNTIME))
  224. if (ctrl->power_status == FIMC_POWER_OFF) {
  225. pm_runtime_get_sync(&pdev->dev);
  226. }
  227. #endif
  228. /*
  229. * WriteBack mode doesn't need to set clock and power,
  230. * but it needs to set source width, height depend on LCD resolution.
  231. */
  232. if ((cam->id == CAMERA_WB) || (cam->id == CAMERA_WB_B)) {
  233. ret = s3cfb_direct_ioctl(0, S3CFB_GET_LCD_WIDTH,
  234. (unsigned long)&cam->width);
  235. if (ret) {
  236. fimc_err("fail to get LCD size\n");
  237. #if (defined(CONFIG_EXYNOS_DEV_PD) && defined(CONFIG_PM_RUNTIME))
  238. pm_runtime_put_sync(&pdev->dev);
  239. #endif
  240. return ret;
  241. }
  242. ret = s3cfb_direct_ioctl(0, S3CFB_GET_LCD_HEIGHT,
  243. (unsigned long)&cam->height);
  244. if (ret) {
  245. fimc_err("fail to get LCD size\n");
  246. #if (defined(CONFIG_EXYNOS_DEV_PD) && defined(CONFIG_PM_RUNTIME))
  247. pm_runtime_put_sync(&pdev->dev);
  248. #endif
  249. return ret;
  250. }
  251. cam->window.width = cam->width;
  252. cam->window.height = cam->height;
  253. cam->initialized = 1;
  254. return ret;
  255. }
  256. retry:
  257. /* set rate for mclk */
  258. #ifndef CONFIG_MACH_GC1
  259. if ((clk_get_rate(cam->clk)) && (fimc->mclk_status == CAM_MCLK_OFF)) {
  260. #else
  261. if ((clk_get_rate(cam->clk)) && (fimc->mclk_status == CAM_MCLK_OFF)
  262. && !leave_power) {
  263. #endif
  264. clk_set_rate(cam->clk, cam->clk_rate);
  265. clk_enable(cam->clk);
  266. fimc->mclk_status = CAM_MCLK_ON;
  267. fimc_info1("clock for camera: %d\n", cam->clk_rate);
  268. }
  269. /* enable camera power if needed */
  270. if (cam->cam_power) {
  271. #ifndef CONFIG_MACH_GC1
  272. ret = cam->cam_power(1);
  273. #else
  274. if (!leave_power)
  275. ret = cam->cam_power(1);
  276. leave_power = false;
  277. #endif
  278. if (unlikely(ret < 0)) {
  279. fimc_err("\nfail to power on\n");
  280. if (fimc->mclk_status == CAM_MCLK_ON) {
  281. clk_disable(ctrl->cam->clk);
  282. fimc->mclk_status = CAM_MCLK_OFF;
  283. }
  284. #if (defined(CONFIG_EXYNOS_DEV_PD) && defined(CONFIG_PM_RUNTIME))
  285. pm_runtime_put_sync(&pdev->dev);
  286. #endif
  287. return ret;
  288. }
  289. }
  290. #ifndef CONFIG_MACH_GC1
  291. /* "0" argument means preview init for s5k4ea */
  292. ret = v4l2_subdev_call(cam->sd, core, init, 0);
  293. #endif
  294. /* Retry camera power-up if first i2c fails. */
  295. if (unlikely(ret < 0)) {
  296. if (cam->cam_power)
  297. cam->cam_power(0);
  298. if (fimc->mclk_status == CAM_MCLK_ON) {
  299. clk_disable(ctrl->cam->clk);
  300. fimc->mclk_status = CAM_MCLK_OFF;
  301. }
  302. if (retry_cnt++ < 3) {
  303. msleep(100);
  304. fimc_err("Retry power on(%d/3)\n\n", retry_cnt);
  305. goto retry;
  306. } else {
  307. fimc_err("Camera power/init failed!!!!\n\n");
  308. #if (defined(CONFIG_EXYNOS_DEV_PD) && defined(CONFIG_PM_RUNTIME))
  309. if (ctrl->power_status == FIMC_POWER_ON) {
  310. pm_runtime_put_sync(&pdev->dev);
  311. }
  312. #endif
  313. }
  314. } else {
  315. /* Apply things to interface register */
  316. fimc_hwset_reset(ctrl);
  317. cam->initialized = 1;
  318. }
  319. return ret;
  320. }
  321. static int fimc_camera_get_jpeg_memsize(struct fimc_control *ctrl)
  322. {
  323. int ret = 0;
  324. struct v4l2_control cam_ctrl;
  325. cam_ctrl.id = V4L2_CID_CAM_JPEG_MEMSIZE;
  326. ret = v4l2_subdev_call(ctrl->cam->sd, core, g_ctrl, &cam_ctrl);
  327. if (ret < 0) {
  328. fimc_err("%s: Subdev doesn't support JEPG encoding.\n", \
  329. __func__);
  330. return 0;
  331. }
  332. return cam_ctrl.value;
  333. }
  334. static int fimc_capture_scaler_info(struct fimc_control *ctrl)
  335. {
  336. struct fimc_scaler *sc = &ctrl->sc;
  337. struct v4l2_rect *window = &ctrl->cam->window;
  338. int tx, ty, sx, sy;
  339. struct s3c_platform_fimc *pdata = to_fimc_plat(ctrl->dev);
  340. int rot = 0;
  341. if (!ctrl->cam->use_isp) {
  342. sx = window->width;
  343. sy = window->height;
  344. } else {
  345. sx = ctrl->is.fmt.width;
  346. sy = ctrl->is.fmt.height;
  347. }
  348. sc->real_width = sx;
  349. sc->real_height = sy;
  350. rot = fimc_mapping_rot_flip(ctrl->cap->rotate, ctrl->cap->flip);
  351. if (rot & FIMC_ROT) {
  352. tx = ctrl->cap->fmt.height;
  353. ty = ctrl->cap->fmt.width;
  354. } else {
  355. tx = ctrl->cap->fmt.width;
  356. ty = ctrl->cap->fmt.height;
  357. }
  358. fimc_dbg("%s: CamOut (%d, %d), TargetOut (%d, %d)\n",
  359. __func__, sx, sy, tx, ty);
  360. if (sx <= 0 || sy <= 0) {
  361. fimc_err("%s: invalid source size\n", __func__);
  362. return -EINVAL;
  363. }
  364. if (tx <= 0 || ty <= 0) {
  365. fimc_err("%s: invalid target size\n", __func__);
  366. return -EINVAL;
  367. }
  368. fimc_get_scaler_factor(sx, tx, &sc->pre_hratio, &sc->hfactor);
  369. fimc_get_scaler_factor(sy, ty, &sc->pre_vratio, &sc->vfactor);
  370. if (sx == sy) {
  371. if (sx*10/tx >= 15 && sx*10/tx < 20) {
  372. sc->pre_hratio = 2;
  373. sc->hfactor = 1;
  374. }
  375. if (sy*10/ty >= 15 && sy*10/ty < 20) {
  376. sc->pre_vratio = 2;
  377. sc->vfactor = 1;
  378. }
  379. }
  380. sc->pre_dst_width = sx / sc->pre_hratio;
  381. sc->pre_dst_height = sy / sc->pre_vratio;
  382. if (pdata->hw_ver >= 0x50) {
  383. sc->main_hratio = (sx << 14) / (tx << sc->hfactor);
  384. sc->main_vratio = (sy << 14) / (ty << sc->vfactor);
  385. } else {
  386. sc->main_hratio = (sx << 8) / (tx << sc->hfactor);
  387. sc->main_vratio = (sy << 8) / (ty << sc->vfactor);
  388. }
  389. sc->scaleup_h = (tx >= sx) ? 1 : 0;
  390. sc->scaleup_v = (ty >= sy) ? 1 : 0;
  391. return 0;
  392. }
  393. static int fimc_capture_change_scaler_info(struct fimc_control *ctrl)
  394. {
  395. struct fimc_scaler *sc = &ctrl->sc;
  396. struct v4l2_rect *window = &ctrl->cam->window;
  397. int tx, ty, sx, sy;
  398. struct s3c_platform_fimc *pdata = to_fimc_plat(ctrl->dev);
  399. int rot = 0;
  400. if (!ctrl->cam->use_isp) {
  401. sx = window->width;
  402. sy = window->height;
  403. } else {
  404. sx = ctrl->is.zoom_in_width;
  405. sy = ctrl->is.zoom_in_height;
  406. }
  407. sc->real_width = sx;
  408. sc->real_height = sy;
  409. rot = fimc_mapping_rot_flip(ctrl->cap->rotate, ctrl->cap->flip);
  410. if (rot & FIMC_ROT) {
  411. tx = ctrl->cap->fmt.height;
  412. ty = ctrl->cap->fmt.width;
  413. } else {
  414. tx = ctrl->cap->fmt.width;
  415. ty = ctrl->cap->fmt.height;
  416. }
  417. fimc_dbg("%s: CamOut (%d, %d), TargetOut (%d, %d)\n",
  418. __func__, sx, sy, tx, ty);
  419. if (sx <= 0 || sy <= 0) {
  420. fimc_err("%s: invalid source size\n", __func__);
  421. return -EINVAL;
  422. }
  423. if (tx <= 0 || ty <= 0) {
  424. fimc_err("%s: invalid target size\n", __func__);
  425. return -EINVAL;
  426. }
  427. fimc_get_scaler_factor(sx, tx, &sc->pre_hratio, &sc->hfactor);
  428. fimc_get_scaler_factor(sy, ty, &sc->pre_vratio, &sc->vfactor);
  429. sc->pre_dst_width = sx / sc->pre_hratio;
  430. sc->pre_dst_height = sy / sc->pre_vratio;
  431. if (pdata->hw_ver >= 0x50) {
  432. sc->main_hratio = (sx << 14) / (tx << sc->hfactor);
  433. sc->main_vratio = (sy << 14) / (ty << sc->vfactor);
  434. } else {
  435. sc->main_hratio = (sx << 8) / (tx << sc->hfactor);
  436. sc->main_vratio = (sy << 8) / (ty << sc->vfactor);
  437. }
  438. sc->scaleup_h = (tx >= sx) ? 1 : 0;
  439. sc->scaleup_v = (ty >= sy) ? 1 : 0;
  440. return 0;
  441. }
  442. int fimc_start_zoom_capture(struct fimc_control *ctrl)
  443. {
  444. fimc_dbg("%s\n", __func__);
  445. fimc_hwset_start_scaler(ctrl);
  446. fimc_hwset_enable_capture(ctrl, ctrl->sc.bypass);
  447. fimc_hwset_disable_frame_end_irq(ctrl);
  448. return 0;
  449. }
  450. int fimc_stop_zoom_capture(struct fimc_control *ctrl)
  451. {
  452. fimc_dbg("%s\n", __func__);
  453. if (!ctrl->cam) {
  454. fimc_err("%s: No capture device.\n", __func__);
  455. return -ENODEV;
  456. }
  457. if (!ctrl->cap) {
  458. fimc_err("%s: No cappure format.\n", __func__);
  459. return -ENODEV;
  460. }
  461. if (ctrl->cap->lastirq) {
  462. fimc_hwset_enable_lastirq(ctrl);
  463. fimc_hwset_disable_capture(ctrl);
  464. fimc_hwset_disable_lastirq(ctrl);
  465. } else {
  466. fimc_hwset_disable_capture(ctrl);
  467. fimc_hwset_enable_frame_end_irq(ctrl);
  468. }
  469. fimc_hwset_stop_scaler(ctrl);
  470. return 0;
  471. }
  472. static int fimc_add_inqueue(struct fimc_control *ctrl, int i)
  473. {
  474. struct fimc_capinfo *cap = ctrl->cap;
  475. struct fimc_buf_set *tmp_buf;
  476. struct list_head *count;
  477. /* PINGPONG_2ADDR_MODE Only */
  478. list_for_each(count, &cap->inq) {
  479. tmp_buf = list_entry(count, struct fimc_buf_set, list);
  480. /* skip list_add_tail if already buffer is in cap->inq list*/
  481. if (tmp_buf->id == i)
  482. return 0;
  483. }
  484. list_add_tail(&cap->bufs[i].list, &cap->inq);
  485. return 0;
  486. }
  487. static int fimc_add_outqueue(struct fimc_control *ctrl, int i)
  488. {
  489. struct fimc_capinfo *cap = ctrl->cap;
  490. struct fimc_buf_set *buf;
  491. unsigned int mask = 0x2;
  492. /* PINGPONG_2ADDR_MODE Only */
  493. /* pair_buf_index stands for pair index of i. (0<->2) (1<->3) */
  494. int pair_buf_index = (i^mask);
  495. /* FIMC have 4 h/w registers */
  496. if (i < 0 || i >= FIMC_PHYBUFS) {
  497. fimc_err("%s: invalid queue index : %d\n", __func__, i);
  498. return -ENOENT;
  499. }
  500. if (list_empty(&cap->inq))
  501. return -ENOENT;
  502. buf = list_first_entry(&cap->inq, struct fimc_buf_set, list);
  503. /* pair index buffer should be allocated first */
  504. cap->outq[pair_buf_index] = buf->id;
  505. fimc_hwset_output_address(ctrl, buf, pair_buf_index);
  506. cap->outq[i] = buf->id;
  507. fimc_hwset_output_address(ctrl, buf, i);
  508. list_del(&buf->list);
  509. return 0;
  510. }
  511. int fimc_g_parm(struct file *file, void *fh, struct v4l2_streamparm *a)
  512. {
  513. struct fimc_control *ctrl = ((struct fimc_prv_data *)fh)->ctrl;
  514. int ret = 0;
  515. fimc_dbg("%s\n", __func__);
  516. /* WriteBack doesn't have subdev_call */
  517. if ((ctrl->cam->id == CAMERA_WB) || (ctrl->cam->id == CAMERA_WB_B))
  518. return 0;
  519. mutex_lock(&ctrl->v4l2_lock);
  520. ret = v4l2_subdev_call(ctrl->cam->sd, video, g_parm, a);
  521. mutex_unlock(&ctrl->v4l2_lock);
  522. return ret;
  523. }
  524. int fimc_s_parm(struct file *file, void *fh, struct v4l2_streamparm *a)
  525. {
  526. struct fimc_control *ctrl = ((struct fimc_prv_data *)fh)->ctrl;
  527. struct s3c_platform_fimc *pdata = to_fimc_plat(ctrl->dev);
  528. int ret = 0;
  529. int new_fps = a->parm.capture.timeperframe.denominator /
  530. a->parm.capture.timeperframe.numerator;
  531. fimc_info2("%s fimc%d, %d\n", __func__, ctrl->id, new_fps);
  532. /* WriteBack doesn't have subdev_call */
  533. if ((ctrl->cam->id == CAMERA_WB) || (ctrl->cam->id == CAMERA_WB_B))
  534. return 0;
  535. mutex_lock(&ctrl->v4l2_lock);
  536. if (ctrl->cam->sd && fimc_cam_use)
  537. ret = v4l2_subdev_call(ctrl->cam->sd, video, s_parm, a);
  538. else if (ctrl->is.sd && fimc_cam_use)
  539. ret = v4l2_subdev_call(ctrl->is.sd, video, s_parm, a);
  540. mutex_unlock(&ctrl->v4l2_lock);
  541. return ret;
  542. }
  543. /* Enumerate controls */
  544. int fimc_queryctrl(struct file *file, void *fh, struct v4l2_queryctrl *qc)
  545. {
  546. struct fimc_control *ctrl = ((struct fimc_prv_data *)fh)->ctrl;
  547. int i, ret;
  548. fimc_dbg("%s\n", __func__);
  549. for (i = 0; i < ARRAY_SIZE(fimc_controls); i++) {
  550. if (fimc_controls[i].id == qc->id) {
  551. memcpy(qc, &fimc_controls[i], sizeof(struct v4l2_queryctrl));
  552. return 0;
  553. }
  554. }
  555. mutex_lock(&ctrl->v4l2_lock);
  556. ret = v4l2_subdev_call(ctrl->cam->sd, core, queryctrl, qc);
  557. mutex_unlock(&ctrl->v4l2_lock);
  558. return ret;
  559. }
  560. /* Menu control items */
  561. int fimc_querymenu(struct file *file, void *fh, struct v4l2_querymenu *qm)
  562. {
  563. struct fimc_control *ctrl = ((struct fimc_prv_data *)fh)->ctrl;
  564. int ret = 0;
  565. fimc_dbg("%s\n", __func__);
  566. mutex_lock(&ctrl->v4l2_lock);
  567. ret = v4l2_subdev_call(ctrl->cam->sd, core, querymenu, qm);
  568. mutex_unlock(&ctrl->v4l2_lock);
  569. return ret;
  570. }
  571. int fimc_enum_input(struct file *file, void *fh, struct v4l2_input *inp)
  572. {
  573. struct fimc_global *fimc = get_fimc_dev();
  574. struct fimc_control *ctrl = ((struct fimc_prv_data *)fh)->ctrl;
  575. fimc_dbg("%s: index %d\n", __func__, inp->index);
  576. if (inp->index >= FIMC_MAXCAMS) {
  577. fimc_err("%s: invalid input index, received = %d\n",
  578. __func__, inp->index);
  579. return -EINVAL;
  580. }
  581. if (!fimc->camera_isvalid[inp->index])
  582. return -EINVAL;
  583. mutex_lock(&ctrl->v4l2_lock);
  584. if (fimc->camera[inp->index]->use_isp && !(fimc->camera[inp->index]->info))
  585. strcpy(inp->name, "ISP Camera");
  586. else
  587. strcpy(inp->name, fimc->camera[inp->index]->info->type);
  588. inp->type = V4L2_INPUT_TYPE_CAMERA;
  589. mutex_unlock(&ctrl->v4l2_lock);
  590. return 0;
  591. }
  592. int fimc_g_input(struct file *file, void *fh, unsigned int *i)
  593. {
  594. struct fimc_control *ctrl = ((struct fimc_prv_data *)fh)->ctrl;
  595. struct fimc_global *fimc = get_fimc_dev();
  596. /* In case of isueing g_input before s_input */
  597. if (!ctrl->cam) {
  598. fimc_err("no camera device selected yet. do VIDIOC_S_INPUT first\n");
  599. return -ENODEV;
  600. }
  601. mutex_lock(&ctrl->v4l2_lock);
  602. *i = (unsigned int) fimc->active_camera;
  603. mutex_unlock(&ctrl->v4l2_lock);
  604. fimc_dbg("%s: index %d\n", __func__, *i);
  605. return 0;
  606. }
  607. int fimc_release_subdev(struct fimc_control *ctrl)
  608. {
  609. struct fimc_global *fimc = get_fimc_dev();
  610. struct i2c_client *client;
  611. struct s3c_platform_fimc *pdata = to_fimc_plat(ctrl->dev);
  612. int ret;
  613. if (ctrl->cam->sd && fimc_cam_use) {
  614. fimc_dbg("%s called\n", __func__);
  615. /* WriteBack doesn't need clock setting */
  616. if ((ctrl->cam->id == CAMERA_WB) ||
  617. (ctrl->cam->id == CAMERA_WB_B)) {
  618. ctrl->cam->initialized = 0;
  619. ctrl->cam = NULL;
  620. fimc->active_camera = -1;
  621. return 0;
  622. }
  623. client = v4l2_get_subdevdata(ctrl->cam->sd);
  624. i2c_unregister_device(client);
  625. ctrl->cam->sd = NULL;
  626. #ifndef CONFIG_MACH_GC1
  627. if (ctrl->cam->cam_power)
  628. #else
  629. if (ctrl->cam->cam_power && !leave_power)
  630. #endif
  631. ctrl->cam->cam_power(0);
  632. /* shutdown the MCLK */
  633. #ifndef CONFIG_MACH_GC1
  634. if (fimc->mclk_status == CAM_MCLK_ON) {
  635. #else
  636. if (fimc->mclk_status == CAM_MCLK_ON && !leave_power) {
  637. #endif
  638. clk_disable(ctrl->cam->clk);
  639. fimc->mclk_status = CAM_MCLK_OFF;
  640. }
  641. ctrl->cam->initialized = 0;
  642. ctrl->cam = NULL;
  643. fimc->active_camera = -1;
  644. } else if (ctrl->cam->sd) {
  645. ctrl->cam->initialized = 0;
  646. ctrl->cam = NULL;
  647. fimc->active_camera = -1;
  648. }
  649. if (ctrl->flite_sd && fimc_cam_use) {
  650. ret = v4l2_subdev_call(ctrl->flite_sd, core, s_power, 0);
  651. if (ret)
  652. fimc_err("s_power failed: %d", ret);
  653. ctrl->flite_sd = NULL;
  654. }
  655. return 0;
  656. }
  657. static int fimc_configure_subdev(struct fimc_control *ctrl)
  658. {
  659. struct i2c_adapter *i2c_adap;
  660. struct i2c_board_info *i2c_info;
  661. struct i2c_client *client;
  662. struct v4l2_subdev *sd;
  663. unsigned short addr;
  664. char *name;
  665. int ret = 0;
  666. i2c_adap = i2c_get_adapter(ctrl->cam->get_i2c_busnum());
  667. if (!i2c_adap) {
  668. fimc_err("subdev i2c_adapter missing-skip registration\n");
  669. return -ENODEV;
  670. }
  671. i2c_info = ctrl->cam->info;
  672. if (!i2c_info) {
  673. fimc_err("%s: subdev i2c board info missing\n", __func__);
  674. return -ENODEV;
  675. }
  676. name = i2c_info->type;
  677. if (!name) {
  678. fimc_err("subdev i2c driver name missing-skip registration\n");
  679. return -ENODEV;
  680. }
  681. addr = i2c_info->addr;
  682. if (!addr) {
  683. fimc_err("subdev i2c address missing-skip registration\n");
  684. return -ENODEV;
  685. }
  686. /*
  687. * NOTE: first time subdev being registered,
  688. * s_config is called and try to initialize subdev device
  689. * but in this point, we are not giving MCLK and power to subdev
  690. * so nothing happens but pass platform data through
  691. */
  692. sd = v4l2_i2c_new_subdev_board(&ctrl->v4l2_dev, i2c_adap,
  693. i2c_info, &addr);
  694. if (!sd) {
  695. fimc_err("%s: v4l2 subdev board registering failed\n",
  696. __func__);
  697. }
  698. /* Assign subdev to proper camera device pointer */
  699. ctrl->cam->sd = sd;
  700. if (!ctrl->cam->initialized) {
  701. ret = fimc_init_camera(ctrl);
  702. if (ret < 0) {
  703. fimc_err("%s: fail to initialize subdev\n", __func__);
  704. #ifndef CONFIG_MACH_GC1
  705. client = v4l2_get_subdevdata(sd);
  706. i2c_unregister_device(client);
  707. ctrl->cam->sd = NULL;
  708. #endif
  709. return ret;
  710. }
  711. }
  712. return 0;
  713. }
  714. static int flite_register_callback(struct device *dev, void *p)
  715. {
  716. struct v4l2_subdev **sd_list = p;
  717. struct v4l2_subdev *sd = NULL;
  718. sd = dev_get_drvdata(dev);
  719. if (sd) {
  720. struct platform_device *pdev = v4l2_get_subdev_hostdata(sd);
  721. *(sd_list + pdev->id) = sd;
  722. }
  723. return 0; /* non-zero value stops iteration */
  724. }
  725. static struct v4l2_subdev *exynos_flite_get_subdev(int id)
  726. {
  727. const char *module_name = "exynos-fimc-lite";
  728. struct device_driver *drv;
  729. struct v4l2_subdev *sd[FLITE_MAX_NUM] = {NULL,};
  730. int ret;
  731. drv = driver_find(module_name, &platform_bus_type);
  732. if (!drv) {
  733. request_module(module_name);
  734. drv = driver_find(module_name, &platform_bus_type);
  735. }
  736. if (!drv)
  737. return ERR_PTR(-ENODEV);
  738. ret = driver_for_each_device(drv, NULL, &sd[0],
  739. flite_register_callback);
  740. put_driver(drv);
  741. return ret ? NULL : sd[id];
  742. }
  743. int fimc_subdev_attatch(struct fimc_control *ctrl)
  744. {
  745. int ret = 0;
  746. struct s3c_platform_fimc *pdata = to_fimc_plat(ctrl->dev);
  747. ctrl->flite_sd = exynos_flite_get_subdev(ctrl->cam->flite_id);
  748. if (IS_ERR_OR_NULL(ctrl->flite_sd)) {
  749. ctrl->flite_sd = NULL;
  750. return PTR_ERR(ctrl->flite_sd);
  751. } else {
  752. if (fimc_cam_use) {
  753. ret = v4l2_subdev_call(ctrl->flite_sd, core, s_power, 1);
  754. if (ret)
  755. fimc_err("s_power failed: %d", ret);
  756. }
  757. }
  758. return 0;
  759. }
  760. static int fimc_is_register_callback(struct device *dev, void *p)
  761. {
  762. struct v4l2_subdev **sd = p;
  763. *sd = dev_get_drvdata(dev);
  764. if (!*sd)
  765. return -EINVAL;
  766. return 0; /* non-zero value stops iteration */
  767. }
  768. int fimc_is_release_subdev(struct fimc_control *ctrl)
  769. {
  770. int ret;
  771. struct fimc_global *fimc = get_fimc_dev();
  772. struct s3c_platform_fimc *pdata = to_fimc_plat(ctrl->dev);
  773. if (ctrl->is.sd && ctrl->cam && fimc_cam_use) {
  774. if (ctrl->cam->cam_power)
  775. ctrl->cam->cam_power(0);
  776. /* shutdown the MCLK */
  777. if (fimc->mclk_status == CAM_MCLK_ON) {
  778. clk_disable(ctrl->cam->clk);
  779. fimc->mclk_status = CAM_MCLK_OFF;
  780. }
  781. ret = v4l2_subdev_call(ctrl->is.sd, core, s_power, 0);
  782. if (ret < 0) {
  783. fimc_dbg("FIMC-IS init failed");
  784. return -ENODEV;
  785. }
  786. v4l2_device_unregister_subdev(ctrl->is.sd);
  787. ctrl->is.sd = NULL;
  788. ctrl->cam->initialized = 0;
  789. ctrl->cam = NULL;
  790. fimc->active_camera = -1;
  791. } else if (ctrl->is.sd && ctrl->cam) {
  792. ctrl->is.sd = NULL;
  793. ctrl->cam->initialized = 0;
  794. ctrl->cam = NULL;
  795. fimc->active_camera = -1;
  796. }
  797. return 0;
  798. }
  799. static struct v4l2_subdev *fimc_is_get_subdev(int id)
  800. {
  801. const char *module_name = "exynos4-fimc-is";
  802. struct device_driver *drv;
  803. struct v4l2_subdev *sd = NULL;
  804. int ret;
  805. drv = driver_find(module_name, &platform_bus_type);
  806. if (!drv) {
  807. request_module(module_name);
  808. drv = driver_find(module_name, &platform_bus_type);
  809. }
  810. if (!drv)
  811. return ERR_PTR(-ENODEV);
  812. ret = driver_for_each_device(drv, NULL, &sd,
  813. fimc_is_register_callback);
  814. put_driver(drv);
  815. return ret ? NULL : sd;
  816. }
  817. static int fimc_is_init_cam(struct fimc_control *ctrl)
  818. {
  819. struct fimc_global *fimc = get_fimc_dev();
  820. struct s3c_platform_camera *cam;
  821. int ret = 0;
  822. #if (defined(CONFIG_EXYNOS_DEV_PD) && defined(CONFIG_PM_RUNTIME))
  823. struct platform_device *pdev = to_platform_device(ctrl->dev);
  824. #endif
  825. cam = ctrl->cam;
  826. /* Do noting if already initialized */
  827. if (ctrl->cam->initialized)
  828. return 0;
  829. #if (defined(CONFIG_EXYNOS_DEV_PD) && defined(CONFIG_PM_RUNTIME))
  830. if (ctrl->power_status == FIMC_POWER_OFF)
  831. pm_runtime_get_sync(&pdev->dev);
  832. #endif
  833. /* set rate for mclk */
  834. if ((clk_get_rate(cam->clk)) && (fimc->mclk_status == CAM_MCLK_OFF)) {
  835. clk_set_rate(cam->clk, cam->clk_rate);
  836. clk_enable(cam->clk);
  837. fimc->mclk_status = CAM_MCLK_ON;
  838. fimc_info1("clock for camera (FIMC-IS): %d\n", cam->clk_rate);
  839. }
  840. /* enable camera power if needed */
  841. if (cam->cam_power) {
  842. ret = cam->cam_power(1);
  843. if (unlikely(ret < 0))
  844. fimc_err("\nfail to power on\n");
  845. }
  846. /* Retry camera power-up if first i2c fails. */
  847. if (unlikely(ret < 0)) {
  848. if (cam->cam_power)
  849. cam->cam_power(0);
  850. if (fimc->mclk_status == CAM_MCLK_ON) {
  851. clk_disable(ctrl->cam->clk);
  852. fimc->mclk_status = CAM_MCLK_OFF;
  853. }
  854. fimc_err("Camera power/init failed!!!!\n\n");
  855. #if (defined(CONFIG_EXYNOS_DEV_PD) && defined(CONFIG_PM_RUNTIME))
  856. if (ctrl->power_status == FIMC_POWER_ON)
  857. pm_runtime_put_sync(&pdev->dev);
  858. #endif
  859. } else {
  860. /* Apply things to interface register */
  861. fimc_hwset_reset(ctrl);
  862. cam->initialized = 1;
  863. }
  864. return ret;
  865. }
  866. int fimc_s_input(struct file *file, void *fh, unsigned int i)
  867. {
  868. struct fimc_global *fimc = get_fimc_dev();
  869. struct fimc_control *ctrl = ((struct fimc_prv_data *)fh)->ctrl;
  870. struct fimc_capinfo *cap = ctrl->cap;
  871. struct s3c_platform_fimc *pdata = to_fimc_plat(ctrl->dev);
  872. int ret = 0;
  873. #if (defined(CONFIG_EXYNOS_DEV_PD) && defined(CONFIG_PM_RUNTIME))
  874. struct platform_device *pdev = to_platform_device(ctrl->dev);
  875. #endif
  876. fimc_dbg("%s: index %d\n", __func__, i);
  877. if (i >= FIMC_MAXCAMS) {
  878. fimc_err("%s: invalid input index\n", __func__);
  879. return -EINVAL;
  880. }
  881. if (!fimc->camera_isvalid[i])
  882. return -EINVAL;
  883. if (fimc->camera[i]->sd && fimc_cam_use) {
  884. fimc_err("%s: Camera already in use.\n", __func__);
  885. return -EBUSY;
  886. }
  887. mutex_lock(&ctrl->v4l2_lock);
  888. /* If ctrl->cam is not NULL, there is one subdev already registered.
  889. * We need to unregister that subdev first. */
  890. if (i != fimc->active_camera) {
  891. fimc_info1("\n\nfimc_s_input activating subdev\n");
  892. if (ctrl->cam && (ctrl->cam->sd || ctrl->flite_sd))
  893. fimc_release_subdev(ctrl);
  894. else if (ctrl->is.sd)
  895. fimc_is_release_subdev(ctrl);
  896. ctrl->cam = fimc->camera[i];
  897. if ((ctrl->cam->id != CAMERA_WB) && (ctrl->cam->id !=
  898. CAMERA_WB_B) && (!ctrl->cam->use_isp) && fimc_cam_use) {
  899. ret = fimc_configure_subdev(ctrl);
  900. if (ret < 0) {
  901. #ifdef CONFIG_MACH_GC1
  902. if (ret == -ENOSYS) {
  903. /* return no error If firmware is bad.
  904. Because F/W update app should access the sensor through HAL instance */
  905. fimc_err("%s: please update the F/W\n", __func__);
  906. } else {
  907. ctrl->cam = NULL;
  908. mutex_unlock(&ctrl->v4l2_lock);
  909. fimc_err("%s: Could not register camera" \
  910. " sensor with V4L2.\n", __func__);
  911. return -ENODEV;
  912. }
  913. #else
  914. ctrl->cam = NULL;
  915. mutex_unlock(&ctrl->v4l2_lock);
  916. fimc_err("%s: Could not register camera" \
  917. " sensor with V4L2.\n", __func__);
  918. return -ENODEV;
  919. #endif
  920. }
  921. }
  922. fimc->active_camera = i;
  923. fimc_info2("fimc_s_input activated subdev = %d\n", i);
  924. }
  925. if (!fimc_cam_use) {
  926. if (i == fimc->active_camera) {
  927. ctrl->cam = fimc->camera[i];
  928. fimc_info2("fimc_s_input activating subdev FIMC%d\n",
  929. ctrl->id);
  930. } else {
  931. mutex_unlock(&ctrl->v4l2_lock);
  932. return -EINVAL;
  933. }
  934. #if (defined(CONFIG_EXYNOS_DEV_PD) && defined(CONFIG_PM_RUNTIME))
  935. #ifdef CONFIG_DRM_EXYNOS_FIMD_WB
  936. if ((ctrl->cam->id != CAMERA_WB) &&
  937. (ctrl->cam->id != CAMERA_WB_B) &&
  938. (ctrl->power_status == FIMC_POWER_OFF)) {
  939. #else
  940. if (ctrl->power_status == FIMC_POWER_OFF) {
  941. #endif
  942. pm_runtime_get_sync(&pdev->dev);
  943. }
  944. fimc_hwset_reset(ctrl);
  945. #endif
  946. }
  947. if (ctrl->cam->use_isp) {
  948. /* fimc-lite attatch */
  949. ret = fimc_subdev_attatch(ctrl);
  950. if (ret) {
  951. fimc_err("subdev_attatch failed\n");
  952. mutex_unlock(&ctrl->v4l2_lock);
  953. return -ENODEV;
  954. }
  955. /* fimc-is attatch */
  956. ctrl->is.sd = fimc_is_get_subdev(i);
  957. if (IS_ERR_OR_NULL(ctrl->is.sd)) {
  958. fimc_err("fimc-is subdev_attatch failed\n");
  959. mutex_unlock(&ctrl->v4l2_lock);
  960. return -ENODEV;
  961. }
  962. ctrl->is.fmt.width = ctrl->cam->width;
  963. ctrl->is.fmt.height = ctrl->cam->height;
  964. ctrl->is.frame_count = 0;
  965. if (fimc_cam_use) {
  966. ret = fimc_is_init_cam(ctrl);
  967. if (ret < 0) {
  968. fimc_dbg("FIMC-IS init clock failed");
  969. mutex_unlock(&ctrl->v4l2_lock);
  970. return -ENODEV;
  971. }
  972. ret = v4l2_subdev_call(ctrl->is.sd, core, s_power, 1);
  973. if (ret < 0) {
  974. fimc_err("FIMC-IS init s_power failed");
  975. mutex_unlock(&ctrl->v4l2_lock);
  976. return -ENODEV;
  977. }
  978. ret = v4l2_subdev_call(ctrl->is.sd, core, load_fw);
  979. if (ret < 0) {
  980. fimc_err("FIMC-IS init load_fw failed");
  981. mutex_unlock(&ctrl->v4l2_lock);
  982. if (!cap) {
  983. cap = kzalloc(sizeof(*cap), GFP_KERNEL);
  984. if (!cap) {
  985. fimc_err("%s: no memory for "
  986. "capture device info\n", __func__);
  987. return -ENOMEM;
  988. }
  989. /* assign to ctrl */
  990. ctrl->cap = cap;
  991. }
  992. return -ENODEV;
  993. }
  994. ret = v4l2_subdev_call(ctrl->is.sd, core, init, ctrl->cam->sensor_index);
  995. if (ret < 0) {
  996. fimc_err("FIMC-IS init failed");
  997. mutex_unlock(&ctrl->v4l2_lock);
  998. if (!cap) {
  999. cap = kzalloc(sizeof(*cap), GFP_KERNEL);
  1000. if (!cap) {
  1001. fimc_err("%s: no memory for "
  1002. "capture device info\n", __func__);
  1003. return -ENOMEM;
  1004. }
  1005. /* assign to ctrl */
  1006. ctrl->cap = cap;
  1007. }
  1008. return -ENODEV;
  1009. }
  1010. }
  1011. }
  1012. /*
  1013. * The first time alloc for struct cap_info, and will be
  1014. * released at the file close.
  1015. * Anyone has better idea to do this?
  1016. */
  1017. if (!cap) {
  1018. cap = kzalloc(sizeof(*cap), GFP_KERNEL);
  1019. if (!cap) {
  1020. fimc_err("%s: no memory for "
  1021. "capture device info\n", __func__);
  1022. return -ENOMEM;
  1023. }
  1024. /* assign to ctrl */
  1025. ctrl->cap = cap;
  1026. #if (defined(CONFIG_EXYNOS_DEV_PD) && defined(CONFIG_PM_RUNTIME))
  1027. if (ctrl->power_status == FIMC_POWER_OFF)
  1028. pm_runtime_get_sync(&pdev->dev);
  1029. #endif
  1030. } else {
  1031. memset(cap, 0, sizeof(*cap));
  1032. }
  1033. mutex_unlock(&ctrl->v4l2_lock);
  1034. return 0;
  1035. }
  1036. int fimc_enum_fmt_vid_capture(struct file *file, void *fh,
  1037. struct v4l2_fmtdesc *f)
  1038. {
  1039. struct fimc_control *ctrl = ((struct fimc_prv_data *)fh)->ctrl;
  1040. int i = f->index;
  1041. fimc_dbg("%s\n", __func__);
  1042. if (i >= ARRAY_SIZE(capture_fmts)) {
  1043. fimc_err("%s: There is no support format index %d\n", __func__, i);
  1044. return -EINVAL;
  1045. }
  1046. mutex_lock(&ctrl->v4l2_lock);
  1047. memset(f, 0, sizeof(*f));
  1048. memcpy(f, &capture_fmts[i], sizeof(*f));
  1049. mutex_unlock(&ctrl->v4l2_lock);
  1050. return 0;
  1051. }
  1052. #ifdef CONFIG_SLP_DMABUF
  1053. /*
  1054. * figures out the depth of requested format
  1055. */
  1056. static int fimc_fmt_depth_mplane(struct fimc_control *ctrl,
  1057. struct v4l2_format *f, int depth[])
  1058. {
  1059. int ret = 0;
  1060. /* handles only supported pixelformats */
  1061. switch (f->fmt.pix_mp.pixelformat) {
  1062. case V4L2_PIX_FMT_NV12:
  1063. case V4L2_PIX_FMT_NV12T:
  1064. case V4L2_PIX_FMT_NV21:
  1065. f->fmt.pix_mp.num_planes = 2;
  1066. depth[0] = 8;
  1067. depth[1] = 4;
  1068. break;
  1069. case V4L2_PIX_FMT_YUV420:
  1070. case V4L2_PIX_FMT_YVU420:
  1071. f->fmt.pix_mp.num_planes = 3;
  1072. depth[0] = 8;
  1073. depth[1] = 2;
  1074. depth[2] = 2;
  1075. break;
  1076. case V4L2_PIX_FMT_JPEG:
  1077. case V4L2_PIX_FMT_INTERLEAVED:
  1078. f->fmt.pix_mp.num_planes = 1;
  1079. depth[0] = -1;
  1080. fimc_dbg("Compressed format.\n");
  1081. break;
  1082. default:
  1083. fimc_dbg("why am I here?\n");
  1084. ret = -EINVAL;
  1085. break;
  1086. }
  1087. return ret;
  1088. }
  1089. static int fimc_g_fmt_vid_capture_mplane(struct fimc_control *ctrl,
  1090. struct v4l2_format *f)
  1091. {
  1092. int depth[VIDEO_MAX_PLANES];
  1093. int ret;
  1094. int i;
  1095. /*
  1096. * Note that expecting format only can be with
  1097. * available output format from FIMC
  1098. * Following items should be handled in driver
  1099. * bytesperline = width * depth / 8
  1100. * sizeimage = bytesperline * height
  1101. */
  1102. f->fmt.pix_mp.pixelformat = ctrl->cap->fmt.pixelformat;
  1103. f->fmt.pix_mp.width = ctrl->cap->fmt.width;
  1104. f->fmt.pix_mp.height = ctrl->cap->fmt.height;
  1105. ret = fimc_fmt_depth_mplane(ctrl, f, depth);
  1106. if (ret < 0) {
  1107. fimc_err("Invaild format\n");
  1108. return ret;
  1109. }
  1110. for (i = 0; i < f->fmt.pix_mp.num_planes; ++i) {
  1111. f->fmt.pix_mp.plane_fmt[i].bytesperline = (f->fmt.pix_mp.width *
  1112. depth[i]) >> 3;
  1113. f->fmt.pix_mp.plane_fmt[i].sizeimage =
  1114. (f->fmt.pix_mp.plane_fmt[i].bytesperline *
  1115. f->fmt.pix_mp.width);
  1116. }
  1117. return 0;
  1118. }
  1119. #endif
  1120. int fimc_g_fmt_vid_capture(struct file *file, void *fh, struct v4l2_format *f)
  1121. {
  1122. struct fimc_control *ctrl = ((struct fimc_prv_data *)fh)->ctrl;
  1123. fimc_dbg("%s\n", __func__);
  1124. if (!ctrl->cap) {
  1125. fimc_err("%s: no capture device info\n", __func__);
  1126. return -EINVAL;
  1127. }
  1128. mutex_lock(&ctrl->v4l2_lock);
  1129. #ifdef CONFIG_SLP_DMABUF
  1130. if (V4L2_TYPE_IS_MULTIPLANAR(f->type))
  1131. if (fimc_g_fmt_vid_capture_mplane(ctrl, f) < 0) {
  1132. mutex_unlock(&ctrl->v4l2_lock);
  1133. return -EINVAL;
  1134. }
  1135. else {
  1136. memset(&f->fmt.pix, 0, sizeof(f->fmt.pix));
  1137. memcpy(&f->fmt.pix, &ctrl->cap->fmt, sizeof(f->fmt.pix));
  1138. }
  1139. #else
  1140. memset(&f->fmt.pix, 0, sizeof(f->fmt.pix));
  1141. memcpy(&f->fmt.pix, &ctrl->cap->fmt, sizeof(f->fmt.pix));
  1142. #endif
  1143. mutex_unlock(&ctrl->v4l2_lock);
  1144. return 0;
  1145. }
  1146. /*
  1147. * Check for whether the requested format
  1148. * can be streamed out from FIMC
  1149. * depends on FIMC node
  1150. */
  1151. static int fimc_fmt_avail(struct fimc_control *ctrl,
  1152. struct v4l2_pix_format *f)
  1153. {
  1154. int i;
  1155. /*
  1156. * TODO: check for which FIMC is used.
  1157. * Available fmt should be varied for each FIMC
  1158. */
  1159. for (i = 0; i < ARRAY_SIZE(capture_fmts); i++) {
  1160. if (capture_fmts[i].pixelformat == f->pixelformat)
  1161. return 0;
  1162. }
  1163. fimc_info1("Not supported pixelformat requested\n");
  1164. return -1;
  1165. }
  1166. /*
  1167. * figures out the depth of requested format
  1168. */
  1169. static int fimc_fmt_depth(struct fimc_control *ctrl, struct v4l2_pix_format *f)
  1170. {
  1171. int err, depth = 0;
  1172. /* First check for available format or not */
  1173. err = fimc_fmt_avail(ctrl, f);
  1174. if (err < 0)
  1175. return -1;
  1176. /* handles only supported pixelformats */
  1177. switch (f->pixelformat) {
  1178. case V4L2_PIX_FMT_RGB32:
  1179. depth = 32;
  1180. fimc_dbg("32bpp\n");
  1181. break;
  1182. case V4L2_PIX_FMT_RGB565:
  1183. case V4L2_PIX_FMT_YUYV:
  1184. case V4L2_PIX_FMT_UYVY:
  1185. case V4L2_PIX_FMT_VYUY:
  1186. case V4L2_PIX_FMT_YVYU:
  1187. case V4L2_PIX_FMT_YUV422P:
  1188. case V4L2_PIX_FMT_NV16:
  1189. case V4L2_PIX_FMT_NV61:
  1190. depth = 16;
  1191. fimc_dbg("16bpp\n");
  1192. break;
  1193. case V4L2_PIX_FMT_NV12:
  1194. case V4L2_PIX_FMT_NV12T:
  1195. case V4L2_PIX_FMT_NV21:
  1196. case V4L2_PIX_FMT_YUV420:
  1197. case V4L2_PIX_FMT_YVU420:
  1198. depth = 12;
  1199. fimc_dbg("12bpp\n");
  1200. break;
  1201. case V4L2_PIX_FMT_JPEG:
  1202. case V4L2_PIX_FMT_INTERLEAVED:
  1203. depth = -1;
  1204. fimc_dbg("Compressed format.\n");
  1205. break;
  1206. default:
  1207. fimc_dbg("why am I here?\n");
  1208. break;
  1209. }
  1210. return depth;
  1211. }
  1212. int fimc_s_fmt_vid_private(struct file *file, void *fh, struct v4l2_format *f)
  1213. {
  1214. struct fimc_control *ctrl = ((struct fimc_prv_data *)fh)->ctrl;
  1215. struct s3c_platform_fimc *pdata = to_fimc_plat(ctrl->dev);
  1216. struct v4l2_mbus_framefmt *mbus_fmt;
  1217. int ret = 0;
  1218. fimc_dbg("%s\n", __func__);
  1219. if (ctrl->cam->sd) {
  1220. struct v4l2_pix_format *pix = &f->fmt.pix;
  1221. int depth;
  1222. fimc_info1("%s %d:\n", __func__, __LINE__);
  1223. mbus_fmt = &ctrl->cap->mbus_fmt;
  1224. mbus_fmt->width = pix->width;
  1225. mbus_fmt->height = pix->height;
  1226. #ifdef CONFIG_MACH_P4NOTE
  1227. /* Unfortuntely, we have to use pix->field (not pix->priv) since
  1228. * pix.field is already used in the below else condtion statement
  1229. * (in case that sub-devices are not registered)
  1230. */
  1231. mbus_fmt->field = pix->field;
  1232. #endif
  1233. #if defined(CONFIG_MACH_GC1)
  1234. mbus_fmt->field = pix->priv;
  1235. #endif
  1236. printk(KERN_INFO "%s mbus_fmt->width = %d, height = %d,\n",
  1237. __func__,mbus_fmt->width ,mbus_fmt->height);
  1238. depth = fimc_fmt_depth(ctrl, pix);
  1239. if (depth == 0) {
  1240. fimc_err("%s: Invalid pixel format\n", __func__);
  1241. return -EINVAL;
  1242. } else if (depth < 0) { /* JPEG */
  1243. mbus_fmt->code = V4L2_MBUS_FMT_JPEG_1X8;
  1244. mbus_fmt->colorspace = V4L2_COLORSPACE_JPEG;
  1245. } else {
  1246. mbus_fmt->code = V4L2_MBUS_FMT_VYUY8_2X8;
  1247. }
  1248. if (fimc_cam_use) {
  1249. ret = v4l2_subdev_call(ctrl->cam->sd, video,
  1250. s_mbus_fmt, mbus_fmt);
  1251. if (ret) {
  1252. fimc_err("%s: fail to s_mbus_fmt\n", __func__);
  1253. return ret;
  1254. }
  1255. }
  1256. return 0;
  1257. } else {
  1258. mbus_fmt = kzalloc(sizeof(*mbus_fmt), GFP_KERNEL);
  1259. if (!mbus_fmt) {
  1260. fimc_err("%s: no memory for "
  1261. "mbus_fmt\n", __func__);
  1262. return -ENOMEM;
  1263. }
  1264. ctrl->is.fmt.width = f->fmt.pix.width;
  1265. ctrl->is.fmt.height = f->fmt.pix.height;
  1266. ctrl->is.fmt.pixelformat = f->fmt.pix.pixelformat;
  1267. mbus_fmt->width = f->fmt.pix.width;
  1268. mbus_fmt->height = f->fmt.pix.height;
  1269. mbus_fmt->code = V4L2_MBUS_FMT_YUYV8_2X8; /*dummy*/
  1270. mbus_fmt->field = f->fmt.pix.field;
  1271. mbus_fmt->colorspace = V4L2_COLORSPACE_SRGB;
  1272. printk(KERN_INFO "%s mbus_fmt->width = %d, height = %d, \n",
  1273. __func__,mbus_fmt->width ,mbus_fmt->height);
  1274. if (fimc_cam_use)
  1275. ret = v4l2_subdev_call(ctrl->is.sd, video,
  1276. s_mbus_fmt, mbus_fmt);
  1277. kfree(mbus_fmt);
  1278. return ret;
  1279. }
  1280. return -EINVAL;
  1281. }
  1282. int fimc_s_fmt_vid_capture(struct file *file, void *fh, struct v4l2_format *f)
  1283. {
  1284. struct fimc_control *ctrl = ((struct fimc_prv_data *)fh)->ctrl;
  1285. struct fimc_capinfo *cap = ctrl->cap;
  1286. struct s3c_platform_fimc *pdata = to_fimc_plat(ctrl->dev);
  1287. int ret = 0;
  1288. int depth;
  1289. struct v4l2_control is_ctrl;
  1290. is_ctrl.id = 0;
  1291. is_ctrl.value = 0;
  1292. printk(KERN_INFO "%s\n", __func__);
  1293. if (!ctrl->cap) {
  1294. fimc_err("%s: No capture structure." \
  1295. "you have to call s_input first.\n", __func__);
  1296. return -ENODEV;
  1297. }
  1298. /* rotaton, flip, dtp_mode, movie_mode and vt_mode,
  1299. * sensor_output_width,height should be maintained.(by TN) */
  1300. memset(cap, 0, sizeof(*cap) - sizeof(u32) * 7);
  1301. mutex_lock(&ctrl->v4l2_lock);
  1302. memset(&cap->fmt, 0, sizeof(cap->fmt));
  1303. #ifdef CONFIG_SLP_DMABUF
  1304. if (V4L2_TYPE_IS_MULTIPLANAR(f->type)) {
  1305. cap->fmt.pixelformat = f->fmt.pix_mp.pixelformat;
  1306. cap->fmt.width = f->fmt.pix_mp.width;
  1307. cap->fmt.height = f->fmt.pix_mp.height;
  1308. cap->fmt.pixelformat = f->fmt.pix_mp.pixelformat;
  1309. } else
  1310. memcpy(&cap->fmt, &f->fmt.pix, sizeof(cap->fmt));
  1311. #else
  1312. memcpy(&cap->fmt, &f->fmt.pix, sizeof(cap->fmt));
  1313. #endif
  1314. /*
  1315. * Note that expecting format only can be with
  1316. * available output format from FIMC
  1317. * Following items should be handled in driver
  1318. * bytesperline = width * depth / 8
  1319. * sizeimage = bytesperline * height
  1320. */
  1321. /* This function may return 0 or -1 in case of error,
  1322. * hence need to check here.
  1323. */
  1324. depth = fimc_fmt_depth(ctrl, &cap->fmt);
  1325. if (depth == 0) {
  1326. mutex_unlock(&ctrl->v4l2_lock);
  1327. fimc_err("%s: Invalid pixel format\n", __func__);
  1328. return -EINVAL;
  1329. } else if (depth < 0) {
  1330. /*
  1331. * When the pixelformat is JPEG,
  1332. * the application is requesting for data
  1333. * in JPEG compressed format
  1334. */
  1335. cap->fmt.colorspace = V4L2_COLORSPACE_JPEG;
  1336. } else {
  1337. cap->fmt.bytesperline = (cap->fmt.width * depth) >> 3;
  1338. cap->fmt.sizeimage = (cap->fmt.bytesperline * cap->fmt.height);
  1339. }
  1340. if (cap->fmt.pixelformat == V4L2_PIX_FMT_JPEG ||
  1341. cap->fmt.pixelformat == V4L2_PIX_FMT_INTERLEAVED) {
  1342. ctrl->sc.bypass = 1;
  1343. cap->lastirq = 0;
  1344. fimc_info1("fimc_s_fmt_vid_capture V4L2_COLORSPACE_JPEG or INTERLEAVED\n");
  1345. } else {
  1346. #ifdef CONFIG_MACH_GC1
  1347. /*
  1348. Fimc scaler input Hsize is restricted to 4224 pixels.
  1349. So, GC1 has to bypass fimc scaler to use more than 12M YUV.
  1350. */
  1351. if (cap->fmt.width > ctrl->limit->pre_dst_w)
  1352. ctrl->sc.bypass = 1;
  1353. else
  1354. ctrl->sc.bypass = 0;
  1355. #else
  1356. ctrl->sc.bypass = 0;
  1357. #endif
  1358. cap->lastirq = 0;
  1359. }
  1360. printk(KERN_INFO "fimc%d s_fmt width = %d, height = %d\n", ctrl->id, \
  1361. cap->fmt.width, cap->fmt.height);
  1362. /* WriteBack doesn't have subdev_call */
  1363. if (ctrl->cam->id == CAMERA_WB || ctrl->cam->id == CAMERA_WB_B) {
  1364. mutex_unlock(&ctrl->v4l2_lock);
  1365. return 0;
  1366. }
  1367. if (ctrl->is.sd && fimc_cam_use) {
  1368. ctrl->is.mbus_fmt.code = V4L2_MBUS_FMT_SGRBG10_1X10;
  1369. is_ctrl.id = V4L2_CID_IS_GET_SENSOR_WIDTH;
  1370. is_ctrl.value = 0;
  1371. v4l2_subdev_call(ctrl->is.sd, core, g_ctrl, &is_ctrl);
  1372. ctrl->is.fmt.width = ctrl->is.mbus_fmt.width = is_ctrl.value;
  1373. is_ctrl.id = V4L2_CID_IS_GET_SENSOR_HEIGHT;
  1374. is_ctrl.value = 0;
  1375. v4l2_subdev_call(ctrl->is.sd, core, g_ctrl, &is_ctrl);
  1376. ctrl->is.fmt.height = ctrl->is.mbus_fmt.height = is_ctrl.value;
  1377. /* default offset values */
  1378. ctrl->is.offset_x = 16;
  1379. ctrl->is.offset_y = 12;
  1380. }
  1381. fimc_hwset_reset(ctrl);
  1382. mutex_unlock(&ctrl->v4l2_lock);
  1383. printk(KERN_INFO "%s -- FIMC%d\n", __func__, ctrl->id);
  1384. return ret;
  1385. }
  1386. int fimc_try_fmt_vid_capture(struct file *file, void *fh, struct v4l2_format *f)
  1387. {
  1388. /* Not implement */
  1389. return -ENOTTY;
  1390. }
  1391. static int fimc_alloc_buffers(struct fimc_control *ctrl,
  1392. int plane, int size, int align, int bpp, int use_paddingbuf, int pad_size)
  1393. {
  1394. struct fimc_capinfo *cap = ctrl->cap;
  1395. int i, j;
  1396. int plane_length[4] = {0, };
  1397. #ifdef CONFIG_VIDEO_SAMSUNG_USE_DMA_MEM
  1398. int alloc_size, err;
  1399. struct cma_info mem_info;
  1400. #endif
  1401. switch (plane) {
  1402. case 1:
  1403. if (align) {
  1404. plane_length[0] = PAGE_ALIGN((size*bpp) >> 3);
  1405. plane_length[1] = 0;
  1406. plane_length[2] = 0;
  1407. } else {
  1408. plane_length[0] = (size*bpp) >> 3;
  1409. plane_length[1] = 0;
  1410. plane_length[2] = 0;
  1411. }
  1412. break;
  1413. /* In case of 2, only NV12 and NV12T is supported. */
  1414. case 2:
  1415. if (align) {
  1416. plane_length[0] = PAGE_ALIGN((size*8) >> 3);
  1417. plane_length[1] = PAGE_ALIGN((size*(bpp-8)) >> 3);
  1418. plane_length[2] = 0;
  1419. fimc_info2("plane_length[0] = %d, plane_length[1] = %d\n" \
  1420. , plane_length[0], plane_length[1]);
  1421. } else {
  1422. plane_length[0] = ((size*8) >> 3);
  1423. plane_length[1] = ((size*(bpp-8)) >> 3);
  1424. plane_length[2] = 0;
  1425. fimc_info2("plane_length[0] = %d, plane_length[1] = %d\n" \
  1426. , plane_length[0], plane_length[1]);
  1427. }
  1428. break;
  1429. /* In case of 3
  1430. * YUV422 : 8 / 4 / 4 (bits)
  1431. * YUV420 : 8 / 2 / 2 (bits)
  1432. * 3rd plane have to consider page align for mmap */
  1433. case 3:
  1434. if (align) {
  1435. plane_length[0] = (size*8) >> 3;
  1436. plane_length[1] = (size*((bpp-8)/2)) >> 3;
  1437. plane_length[2] = PAGE_ALIGN((size*bpp)>>3) - plane_length[0]
  1438. - plane_length[1];
  1439. } else {
  1440. plane_length[0] = (size*8) >> 3;
  1441. plane_length[1] = (size*((bpp-8)/2)) >> 3;
  1442. plane_length[2] = ((size*bpp)>>3) - plane_length[0]
  1443. - plane_length[1];
  1444. }
  1445. break;
  1446. default:
  1447. fimc_err("impossible!\n");
  1448. return -ENOMEM;
  1449. }
  1450. if (use_paddingbuf) {
  1451. plane_length[plane] = pad_size;
  1452. cap->pktdata_plane = plane;
  1453. } else
  1454. plane_length[plane] = 0;
  1455. #ifdef CONFIG_VIDEO_SAMSUNG_USE_DMA_MEM
  1456. if (align) {
  1457. alloc_size = (ALIGN(plane_length[0], align) +
  1458. ALIGN(plane_length[1], align)
  1459. + ALIGN(plane_length[2], align))
  1460. * cap->nr_bufs;
  1461. } else {
  1462. alloc_size = (plane_length[0] + plane_length[1] +
  1463. plane_length[2]) * cap->nr_bufs;
  1464. }
  1465. err = cma_info(&mem_info, ctrl->dev, 0);
  1466. printk(KERN_DEBUG "%s : [cma_info] start_addr : 0x%x, end_addr : 0x%x, "
  1467. "total_size : 0x%x, free_size : 0x%x req_size : 0x%x\n",
  1468. __func__, mem_info.lower_bound, mem_info.upper_bound,
  1469. mem_info.total_size, mem_info.free_size, alloc_size);
  1470. if (err || (mem_info.free_size < alloc_size)) {
  1471. fimc_err("%s: get cma info failed\n", __func__);
  1472. ctrl->mem.size = 0;
  1473. ctrl->mem.base = 0;
  1474. return -ENOMEM;
  1475. } else {
  1476. ctrl->mem.size = alloc_size;
  1477. ctrl->mem.base = (dma_addr_t)cma_alloc
  1478. (ctrl->dev, ctrl->cma_name, (size_t) alloc_size, align);
  1479. }
  1480. ctrl->mem.curr = ctrl->mem.base;
  1481. #endif
  1482. for (i = 0; i < cap->nr_bufs; i++) {
  1483. for (j = 0; j < plane; j++) {
  1484. cap->bufs[i].length[j] = plane_length[j];
  1485. fimc_dma_alloc(ctrl, &cap->bufs[i], j, align);
  1486. if (!cap->bufs[i].base[j])
  1487. goto err_alloc;
  1488. }
  1489. if (use_paddingbuf) {
  1490. cap->bufs[i].length[plane] = plane_length[plane];
  1491. fimc_dma_alloc(ctrl, &cap->bufs[i], plane, align);
  1492. cap->bufs[i].vaddr_pktdata = phys_to_virt(cap->bufs[i].base[plane]);
  1493. /* printk(KERN_INFO "pktdata address = 0x%x, 0x%x\n"
  1494. ,cap->bufs[i].base[1], cap->bufs[i].vaddr_pktdata ); */
  1495. if (!cap->bufs[i].base[plane])
  1496. goto err_alloc;
  1497. }
  1498. cap->bufs[i].state = VIDEOBUF_PREPARED;
  1499. }
  1500. return 0;
  1501. err_alloc:
  1502. for (i = 0; i < cap->nr_bufs; i++) {
  1503. for (j = 0; j < plane; j++) {
  1504. if (cap->bufs[i].base[j])
  1505. fimc_dma_free(ctrl, &cap->bufs[i], j);
  1506. }
  1507. if (use_paddingbuf) {
  1508. if (cap->bufs[i].base[plane])
  1509. fimc_dma_free(ctrl, &cap->bufs[i], plane);
  1510. }
  1511. memset(&cap->bufs[i], 0, sizeof(cap->bufs[i]));
  1512. }
  1513. return -ENOMEM;
  1514. }
  1515. static void fimc_free_buffers(struct fimc_control *ctrl)
  1516. {
  1517. struct fimc_capinfo *cap;
  1518. int i;
  1519. if (ctrl && ctrl->cap)
  1520. cap = ctrl->cap;
  1521. else
  1522. return;
  1523. for (i = 0; i < FIMC_PHYBUFS; i++) {
  1524. memset(&cap->bufs[i], 0, sizeof(cap->bufs[i]));
  1525. cap->bufs[i].state = VIDEOBUF_NEEDS_INIT;
  1526. }
  1527. ctrl->mem.curr = ctrl->mem.base;
  1528. }
  1529. #ifdef CONFIG_SLP_DMABUF
  1530. static int fimc_set_cap_num_plane(struct fimc_control *ctrl)
  1531. {
  1532. struct fimc_capinfo *cap = ctrl->cap;
  1533. switch (cap->fmt.pixelformat) {
  1534. case V4L2_PIX_FMT_RGB32: /* fall through */
  1535. case V4L2_PIX_FMT_RGB565: /* fall through */
  1536. case V4L2_PIX_FMT_YUYV: /* fall through */
  1537. case V4L2_PIX_FMT_UYVY: /* fall through */
  1538. case V4L2_PIX_FMT_VYUY: /* fall through */
  1539. case V4L2_PIX_FMT_YVYU: /* fall through */
  1540. case V4L2_PIX_FMT_NV16: /* fall through */
  1541. case V4L2_PIX_FMT_NV61: /* fall through */
  1542. case V4L2_PIX_FMT_JPEG:
  1543. case V4L2_PIX_FMT_INTERLEAVED:
  1544. return PLANE_1;
  1545. case V4L2_PIX_FMT_NV21:
  1546. case V4L2_PIX_FMT_NV12:
  1547. case V4L2_PIX_FMT_NV12T:
  1548. return PLANE_2;
  1549. case V4L2_PIX_FMT_YUV422P: /* fall through */
  1550. case V4L2_PIX_FMT_YUV420:
  1551. case V4L2_PIX_FMT_YVU420:
  1552. return PLANE_3;
  1553. default:
  1554. fimc_err("%s: Undefined format\n", __func__);
  1555. break;
  1556. }
  1557. return 0;
  1558. }
  1559. #endif
  1560. int fimc_reqbufs_capture_mmap(void *fh, struct v4l2_requestbuffers *b)
  1561. {
  1562. struct fimc_control *ctrl = fh;
  1563. struct fimc_capinfo *cap = ctrl->cap;
  1564. struct s3c_platform_fimc *pdata = to_fimc_plat(ctrl->dev);
  1565. #if (defined(CONFIG_EXYNOS_DEV_PD) && defined(CONFIG_PM_RUNTIME))
  1566. struct platform_device *pdev = to_platform_device(ctrl->dev);
  1567. #endif
  1568. int ret = 0, i;
  1569. int bpp = 0;
  1570. int size = 0;
  1571. if (!cap) {
  1572. fimc_err("%s: no capture device info\n", __func__);
  1573. return -ENODEV;
  1574. }
  1575. mutex_lock(&ctrl->v4l2_lock);
  1576. /* A count value of zero frees all buffers */
  1577. if ((b->count == 0) || (b->count >= FIMC_CAPBUFS)) {
  1578. /* aborting or finishing any DMA in progress */
  1579. if (ctrl->status == FIMC_STREAMON)
  1580. fimc_streamoff_capture(fh);
  1581. for (i = 0; i < FIMC_CAPBUFS; i++) {
  1582. fimc_dma_free(ctrl, &ctrl->cap->bufs[i], 0);
  1583. fimc_dma_free(ctrl, &ctrl->cap->bufs[i], 1);
  1584. fimc_dma_free(ctrl, &ctrl->cap->bufs[i], 2);
  1585. }
  1586. #ifdef CONFIG_VIDEO_SAMSUNG_USE_DMA_MEM
  1587. if (ctrl->mem.base) {
  1588. cma_free(ctrl->mem.base);
  1589. ctrl->mem.base = 0;
  1590. ctrl->mem.size = 0;
  1591. }
  1592. #endif
  1593. mutex_unlock(&ctrl->v4l2_lock);
  1594. return 0;
  1595. }
  1596. /* free previous buffers */
  1597. if ((cap->nr_bufs >= 0) && (cap->nr_bufs < FIMC_CAPBUFS)) {
  1598. fimc_info1("%s : remained previous buffer count is %d\n", __func__,
  1599. cap->nr_bufs);
  1600. for (i = 0; i < cap->nr_bufs; i++) {
  1601. fimc_dma_free(ctrl, &cap->bufs[i], 0);
  1602. fimc_dma_free(ctrl, &cap->bufs[i], 1);
  1603. fimc_dma_free(ctrl, &cap->bufs[i], 2);
  1604. fimc_dma_free(ctrl, &cap->bufs[i], 3);
  1605. }
  1606. #ifdef CONFIG_VIDEO_SAMSUNG_USE_DMA_MEM
  1607. if (ctrl->mem.base) {
  1608. cma_free(ctrl->mem.base);
  1609. ctrl->mem.base = 0;
  1610. ctrl->mem.size = 0;
  1611. }
  1612. #endif
  1613. }
  1614. fimc_free_buffers(ctrl);
  1615. cap->nr_bufs = b->count;
  1616. if (pdata->hw_ver >= 0x51) {
  1617. #if (defined(CONFIG_EXYNOS_DEV_PD) && defined(CONFIG_PM_RUNTIME))
  1618. if (ctrl->power_status == FIMC_POWER_OFF) {
  1619. pm_runtime_get_sync(&pdev->dev);
  1620. }
  1621. #endif
  1622. fimc_hw_reset_output_buf_sequence(ctrl);
  1623. for (i = 0; i < cap->nr_bufs; i++) {
  1624. fimc_hwset_output_buf_sequence(ctrl, i, 1);
  1625. cap->bufs[i].id = i;
  1626. cap->bufs[i].state = VIDEOBUF_NEEDS_INIT;
  1627. /* initialize list */
  1628. INIT_LIST_HEAD(&cap->bufs[i].list);
  1629. }
  1630. fimc_info1("%s: requested %d buffers\n", __func__, b->count);
  1631. fimc_info1("%s: sequence[%d]\n", __func__,
  1632. fimc_hwget_output_buf_sequence(ctrl));
  1633. INIT_LIST_HEAD(&cap->outgoing_q);
  1634. }
  1635. if (pdata->hw_ver < 0x51) {
  1636. INIT_LIST_HEAD(&cap->inq);
  1637. for (i = 0; i < cap->nr_bufs; i++) {
  1638. cap->bufs[i].id = i;
  1639. cap->bufs[i].state = VIDEOBUF_NEEDS_INIT;
  1640. /* initialize list */
  1641. INIT_LIST_HEAD(&cap->bufs[i].list);
  1642. }
  1643. }
  1644. if (cap->pktdata_enable)
  1645. cap->pktdata_size = 0x1000;
  1646. bpp = fimc_fmt_depth(ctrl, &cap->fmt);
  1647. switch (cap->fmt.pixelformat) {
  1648. case V4L2_PIX_FMT_RGB32: /* fall through */
  1649. case V4L2_PIX_FMT_RGB565: /* fall through */
  1650. case V4L2_PIX_FMT_YUYV: /* fall through */
  1651. case V4L2_PIX_FMT_UYVY: /* fall through */
  1652. case V4L2_PIX_FMT_VYUY: /* fall through */
  1653. case V4L2_PIX_FMT_YVYU: /* fall through */
  1654. case V4L2_PIX_FMT_NV16: /* fall through */
  1655. case V4L2_PIX_FMT_NV61: /* fall through */
  1656. fimc_info1("%s : 1plane\n", __func__);
  1657. ret = fimc_alloc_buffers(ctrl, 1,
  1658. cap->fmt.width * cap->fmt.height, SZ_4K, bpp, cap->pktdata_enable, cap->pktdata_size);
  1659. break;
  1660. case V4L2_PIX_FMT_NV21:
  1661. fimc_info1("%s : 2plane for NV21 w %d h %d\n", __func__,
  1662. cap->fmt.width, cap->fmt.height);
  1663. ret = fimc_alloc_buffers(ctrl, 2,
  1664. cap->fmt.width * cap->fmt.height, 0, bpp, cap->pktdata_enable, cap->pktdata_size);
  1665. break;
  1666. case V4L2_PIX_FMT_NV12:
  1667. fimc_info1("%s : 2plane for NV12\n", __func__);
  1668. ret = fimc_alloc_buffers(ctrl, 2,
  1669. cap->fmt.width * cap->fmt.height, SZ_64K, bpp, cap->pktdata_enable, cap->pktdata_size);
  1670. break;
  1671. case V4L2_PIX_FMT_NV12T:
  1672. fimc_info1("%s : 2plane for NV12T\n", __func__);
  1673. ret = fimc_alloc_buffers(ctrl, 2,
  1674. ALIGN(cap->fmt.width, 128) * ALIGN(cap->fmt.height, 32),
  1675. SZ_64K, bpp, cap->pktdata_enable, cap->pktdata_size);
  1676. break;
  1677. case V4L2_PIX_FMT_YUV422P: /* fall through */
  1678. case V4L2_PIX_FMT_YUV420:
  1679. case V4L2_PIX_FMT_YVU420:
  1680. fimc_info1("%s : 3plane\n", __func__);
  1681. ret = fimc_alloc_buffers(ctrl, 3,
  1682. cap->fmt.width * cap->fmt.height, 0, bpp, cap->pktdata_enable, cap->pktdata_size);
  1683. break;
  1684. case V4L2_PIX_FMT_JPEG:
  1685. fimc_info1("%s : JPEG 1plane\n", __func__);
  1686. size = fimc_camera_get_jpeg_memsize(ctrl);
  1687. fimc_info2("%s : JPEG 1plane size = %x\n", __func__, size);
  1688. ret = fimc_alloc_buffers(ctrl, 1, size, 0, 8, cap->pktdata_enable, cap->pktdata_size);
  1689. break;
  1690. case V4L2_PIX_FMT_INTERLEAVED:
  1691. fimc_info1("%s : Interleaved Format\n", __func__);
  1692. size = fimc_camera_get_jpeg_memsize(ctrl); /*0xA00000*/
  1693. fimc_info2("%s : Interleaved size = %x\n", __func__, size);
  1694. ret = fimc