PageRenderTime 50ms CodeModel.GetById 23ms RepoModel.GetById 0ms app.codeStats 0ms

/drivers/mmc/host/sdricoh_cs.c

https://bitbucket.org/evzijst/linux
C | 573 lines | 418 code | 86 blank | 69 comment | 59 complexity | 11eea3a75396c27726b8dd86390ee89b MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
  1. /*
  2. * sdricoh_cs.c - driver for Ricoh Secure Digital Card Readers that can be
  3. * found on some Ricoh RL5c476 II cardbus bridge
  4. *
  5. * Copyright (C) 2006 - 2008 Sascha Sommer <saschasommer@freenet.de>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; either version 2 of the License, or
  10. * (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20. *
  21. */
  22. /*
  23. #define DEBUG
  24. #define VERBOSE_DEBUG
  25. */
  26. #include <linux/delay.h>
  27. #include <linux/highmem.h>
  28. #include <linux/module.h>
  29. #include <linux/pci.h>
  30. #include <linux/ioport.h>
  31. #include <linux/scatterlist.h>
  32. #include <pcmcia/cistpl.h>
  33. #include <pcmcia/ds.h>
  34. #include <linux/io.h>
  35. #include <linux/mmc/host.h>
  36. #define DRIVER_NAME "sdricoh_cs"
  37. static unsigned int switchlocked;
  38. /* i/o region */
  39. #define SDRICOH_PCI_REGION 0
  40. #define SDRICOH_PCI_REGION_SIZE 0x1000
  41. /* registers */
  42. #define R104_VERSION 0x104
  43. #define R200_CMD 0x200
  44. #define R204_CMD_ARG 0x204
  45. #define R208_DATAIO 0x208
  46. #define R20C_RESP 0x20c
  47. #define R21C_STATUS 0x21c
  48. #define R2E0_INIT 0x2e0
  49. #define R2E4_STATUS_RESP 0x2e4
  50. #define R2F0_RESET 0x2f0
  51. #define R224_MODE 0x224
  52. #define R226_BLOCKSIZE 0x226
  53. #define R228_POWER 0x228
  54. #define R230_DATA 0x230
  55. /* flags for the R21C_STATUS register */
  56. #define STATUS_CMD_FINISHED 0x00000001
  57. #define STATUS_TRANSFER_FINISHED 0x00000004
  58. #define STATUS_CARD_INSERTED 0x00000020
  59. #define STATUS_CARD_LOCKED 0x00000080
  60. #define STATUS_CMD_TIMEOUT 0x00400000
  61. #define STATUS_READY_TO_READ 0x01000000
  62. #define STATUS_READY_TO_WRITE 0x02000000
  63. #define STATUS_BUSY 0x40000000
  64. /* timeouts */
  65. #define INIT_TIMEOUT 100
  66. #define CMD_TIMEOUT 100000
  67. #define TRANSFER_TIMEOUT 100000
  68. #define BUSY_TIMEOUT 32767
  69. /* list of supported pcmcia devices */
  70. static const struct pcmcia_device_id pcmcia_ids[] = {
  71. /* vendor and device strings followed by their crc32 hashes */
  72. PCMCIA_DEVICE_PROD_ID12("RICOH", "Bay1Controller", 0xd9f522ed,
  73. 0xc3901202),
  74. PCMCIA_DEVICE_PROD_ID12("RICOH", "Bay Controller", 0xd9f522ed,
  75. 0xace80909),
  76. PCMCIA_DEVICE_NULL,
  77. };
  78. MODULE_DEVICE_TABLE(pcmcia, pcmcia_ids);
  79. /* mmc privdata */
  80. struct sdricoh_host {
  81. struct device *dev;
  82. struct mmc_host *mmc; /* MMC structure */
  83. unsigned char __iomem *iobase;
  84. struct pci_dev *pci_dev;
  85. int app_cmd;
  86. };
  87. /***************** register i/o helper functions *****************************/
  88. static inline unsigned int sdricoh_readl(struct sdricoh_host *host,
  89. unsigned int reg)
  90. {
  91. unsigned int value = readl(host->iobase + reg);
  92. dev_vdbg(host->dev, "rl %x 0x%x\n", reg, value);
  93. return value;
  94. }
  95. static inline void sdricoh_writel(struct sdricoh_host *host, unsigned int reg,
  96. unsigned int value)
  97. {
  98. writel(value, host->iobase + reg);
  99. dev_vdbg(host->dev, "wl %x 0x%x\n", reg, value);
  100. }
  101. static inline unsigned int sdricoh_readw(struct sdricoh_host *host,
  102. unsigned int reg)
  103. {
  104. unsigned int value = readw(host->iobase + reg);
  105. dev_vdbg(host->dev, "rb %x 0x%x\n", reg, value);
  106. return value;
  107. }
  108. static inline void sdricoh_writew(struct sdricoh_host *host, unsigned int reg,
  109. unsigned short value)
  110. {
  111. writew(value, host->iobase + reg);
  112. dev_vdbg(host->dev, "ww %x 0x%x\n", reg, value);
  113. }
  114. static inline unsigned int sdricoh_readb(struct sdricoh_host *host,
  115. unsigned int reg)
  116. {
  117. unsigned int value = readb(host->iobase + reg);
  118. dev_vdbg(host->dev, "rb %x 0x%x\n", reg, value);
  119. return value;
  120. }
  121. static int sdricoh_query_status(struct sdricoh_host *host, unsigned int wanted,
  122. unsigned int timeout){
  123. unsigned int loop;
  124. unsigned int status = 0;
  125. struct device *dev = host->dev;
  126. for (loop = 0; loop < timeout; loop++) {
  127. status = sdricoh_readl(host, R21C_STATUS);
  128. sdricoh_writel(host, R2E4_STATUS_RESP, status);
  129. if (status & wanted)
  130. break;
  131. }
  132. if (loop == timeout) {
  133. dev_err(dev, "query_status: timeout waiting for %x\n", wanted);
  134. return -ETIMEDOUT;
  135. }
  136. /* do not do this check in the loop as some commands fail otherwise */
  137. if (status & 0x7F0000) {
  138. dev_err(dev, "waiting for status bit %x failed\n", wanted);
  139. return -EINVAL;
  140. }
  141. return 0;
  142. }
  143. static int sdricoh_mmc_cmd(struct sdricoh_host *host, unsigned char opcode,
  144. unsigned int arg)
  145. {
  146. unsigned int status;
  147. int result = 0;
  148. unsigned int loop = 0;
  149. /* reset status reg? */
  150. sdricoh_writel(host, R21C_STATUS, 0x18);
  151. /* fill parameters */
  152. sdricoh_writel(host, R204_CMD_ARG, arg);
  153. sdricoh_writel(host, R200_CMD, (0x10000 << 8) | opcode);
  154. /* wait for command completion */
  155. if (opcode) {
  156. for (loop = 0; loop < CMD_TIMEOUT; loop++) {
  157. status = sdricoh_readl(host, R21C_STATUS);
  158. sdricoh_writel(host, R2E4_STATUS_RESP, status);
  159. if (status & STATUS_CMD_FINISHED)
  160. break;
  161. }
  162. /* don't check for timeout in the loop it is not always
  163. reset correctly
  164. */
  165. if (loop == CMD_TIMEOUT || status & STATUS_CMD_TIMEOUT)
  166. result = -ETIMEDOUT;
  167. }
  168. return result;
  169. }
  170. static int sdricoh_reset(struct sdricoh_host *host)
  171. {
  172. dev_dbg(host->dev, "reset\n");
  173. sdricoh_writel(host, R2F0_RESET, 0x10001);
  174. sdricoh_writel(host, R2E0_INIT, 0x10000);
  175. if (sdricoh_readl(host, R2E0_INIT) != 0x10000)
  176. return -EIO;
  177. sdricoh_writel(host, R2E0_INIT, 0x10007);
  178. sdricoh_writel(host, R224_MODE, 0x2000000);
  179. sdricoh_writel(host, R228_POWER, 0xe0);
  180. /* status register ? */
  181. sdricoh_writel(host, R21C_STATUS, 0x18);
  182. return 0;
  183. }
  184. static int sdricoh_blockio(struct sdricoh_host *host, int read,
  185. u8 *buf, int len)
  186. {
  187. int size;
  188. u32 data = 0;
  189. /* wait until the data is available */
  190. if (read) {
  191. if (sdricoh_query_status(host, STATUS_READY_TO_READ,
  192. TRANSFER_TIMEOUT))
  193. return -ETIMEDOUT;
  194. sdricoh_writel(host, R21C_STATUS, 0x18);
  195. /* read data */
  196. while (len) {
  197. data = sdricoh_readl(host, R230_DATA);
  198. size = min(len, 4);
  199. len -= size;
  200. while (size) {
  201. *buf = data & 0xFF;
  202. buf++;
  203. data >>= 8;
  204. size--;
  205. }
  206. }
  207. } else {
  208. if (sdricoh_query_status(host, STATUS_READY_TO_WRITE,
  209. TRANSFER_TIMEOUT))
  210. return -ETIMEDOUT;
  211. sdricoh_writel(host, R21C_STATUS, 0x18);
  212. /* write data */
  213. while (len) {
  214. size = min(len, 4);
  215. len -= size;
  216. while (size) {
  217. data >>= 8;
  218. data |= (u32)*buf << 24;
  219. buf++;
  220. size--;
  221. }
  222. sdricoh_writel(host, R230_DATA, data);
  223. }
  224. }
  225. if (len)
  226. return -EIO;
  227. return 0;
  228. }
  229. static void sdricoh_request(struct mmc_host *mmc, struct mmc_request *mrq)
  230. {
  231. struct sdricoh_host *host = mmc_priv(mmc);
  232. struct mmc_command *cmd = mrq->cmd;
  233. struct mmc_data *data = cmd->data;
  234. struct device *dev = host->dev;
  235. unsigned char opcode = cmd->opcode;
  236. int i;
  237. dev_dbg(dev, "=============================\n");
  238. dev_dbg(dev, "sdricoh_request opcode=%i\n", opcode);
  239. sdricoh_writel(host, R21C_STATUS, 0x18);
  240. /* MMC_APP_CMDs need some special handling */
  241. if (host->app_cmd) {
  242. opcode |= 64;
  243. host->app_cmd = 0;
  244. } else if (opcode == 55)
  245. host->app_cmd = 1;
  246. /* read/write commands seem to require this */
  247. if (data) {
  248. sdricoh_writew(host, R226_BLOCKSIZE, data->blksz);
  249. sdricoh_writel(host, R208_DATAIO, 0);
  250. }
  251. cmd->error = sdricoh_mmc_cmd(host, opcode, cmd->arg);
  252. /* read response buffer */
  253. if (cmd->flags & MMC_RSP_PRESENT) {
  254. if (cmd->flags & MMC_RSP_136) {
  255. /* CRC is stripped so we need to do some shifting. */
  256. for (i = 0; i < 4; i++) {
  257. cmd->resp[i] =
  258. sdricoh_readl(host,
  259. R20C_RESP + (3 - i) * 4) << 8;
  260. if (i != 3)
  261. cmd->resp[i] |=
  262. sdricoh_readb(host, R20C_RESP +
  263. (3 - i) * 4 - 1);
  264. }
  265. } else
  266. cmd->resp[0] = sdricoh_readl(host, R20C_RESP);
  267. }
  268. /* transfer data */
  269. if (data && cmd->error == 0) {
  270. dev_dbg(dev, "transfer: blksz %i blocks %i sg_len %i "
  271. "sg length %i\n", data->blksz, data->blocks,
  272. data->sg_len, data->sg->length);
  273. /* enter data reading mode */
  274. sdricoh_writel(host, R21C_STATUS, 0x837f031e);
  275. for (i = 0; i < data->blocks; i++) {
  276. size_t len = data->blksz;
  277. u8 *buf;
  278. struct page *page;
  279. int result;
  280. page = sg_page(data->sg);
  281. buf = kmap(page) + data->sg->offset + (len * i);
  282. result =
  283. sdricoh_blockio(host,
  284. data->flags & MMC_DATA_READ, buf, len);
  285. kunmap(page);
  286. flush_dcache_page(page);
  287. if (result) {
  288. dev_err(dev, "sdricoh_request: cmd %i "
  289. "block transfer failed\n", cmd->opcode);
  290. cmd->error = result;
  291. break;
  292. } else
  293. data->bytes_xfered += len;
  294. }
  295. sdricoh_writel(host, R208_DATAIO, 1);
  296. if (sdricoh_query_status(host, STATUS_TRANSFER_FINISHED,
  297. TRANSFER_TIMEOUT)) {
  298. dev_err(dev, "sdricoh_request: transfer end error\n");
  299. cmd->error = -EINVAL;
  300. }
  301. }
  302. /* FIXME check busy flag */
  303. mmc_request_done(mmc, mrq);
  304. dev_dbg(dev, "=============================\n");
  305. }
  306. static void sdricoh_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
  307. {
  308. struct sdricoh_host *host = mmc_priv(mmc);
  309. dev_dbg(host->dev, "set_ios\n");
  310. if (ios->power_mode == MMC_POWER_ON) {
  311. sdricoh_writel(host, R228_POWER, 0xc0e0);
  312. if (ios->bus_width == MMC_BUS_WIDTH_4) {
  313. sdricoh_writel(host, R224_MODE, 0x2000300);
  314. sdricoh_writel(host, R228_POWER, 0x40e0);
  315. } else {
  316. sdricoh_writel(host, R224_MODE, 0x2000340);
  317. }
  318. } else if (ios->power_mode == MMC_POWER_UP) {
  319. sdricoh_writel(host, R224_MODE, 0x2000320);
  320. sdricoh_writel(host, R228_POWER, 0xe0);
  321. }
  322. }
  323. static int sdricoh_get_ro(struct mmc_host *mmc)
  324. {
  325. struct sdricoh_host *host = mmc_priv(mmc);
  326. unsigned int status;
  327. status = sdricoh_readl(host, R21C_STATUS);
  328. sdricoh_writel(host, R2E4_STATUS_RESP, status);
  329. /* some notebooks seem to have the locked flag switched */
  330. if (switchlocked)
  331. return !(status & STATUS_CARD_LOCKED);
  332. return (status & STATUS_CARD_LOCKED);
  333. }
  334. static struct mmc_host_ops sdricoh_ops = {
  335. .request = sdricoh_request,
  336. .set_ios = sdricoh_set_ios,
  337. .get_ro = sdricoh_get_ro,
  338. };
  339. /* initialize the control and register it to the mmc framework */
  340. static int sdricoh_init_mmc(struct pci_dev *pci_dev,
  341. struct pcmcia_device *pcmcia_dev)
  342. {
  343. int result = 0;
  344. void __iomem *iobase = NULL;
  345. struct mmc_host *mmc = NULL;
  346. struct sdricoh_host *host = NULL;
  347. struct device *dev = &pcmcia_dev->dev;
  348. /* map iomem */
  349. if (pci_resource_len(pci_dev, SDRICOH_PCI_REGION) !=
  350. SDRICOH_PCI_REGION_SIZE) {
  351. dev_dbg(dev, "unexpected pci resource len\n");
  352. return -ENODEV;
  353. }
  354. iobase =
  355. pci_iomap(pci_dev, SDRICOH_PCI_REGION, SDRICOH_PCI_REGION_SIZE);
  356. if (!iobase) {
  357. dev_err(dev, "unable to map iobase\n");
  358. return -ENODEV;
  359. }
  360. /* check version? */
  361. if (readl(iobase + R104_VERSION) != 0x4000) {
  362. dev_dbg(dev, "no supported mmc controller found\n");
  363. result = -ENODEV;
  364. goto err;
  365. }
  366. /* allocate privdata */
  367. mmc = pcmcia_dev->priv =
  368. mmc_alloc_host(sizeof(struct sdricoh_host), &pcmcia_dev->dev);
  369. if (!mmc) {
  370. dev_err(dev, "mmc_alloc_host failed\n");
  371. result = -ENOMEM;
  372. goto err;
  373. }
  374. host = mmc_priv(mmc);
  375. host->iobase = iobase;
  376. host->dev = dev;
  377. host->pci_dev = pci_dev;
  378. mmc->ops = &sdricoh_ops;
  379. /* FIXME: frequency and voltage handling is done by the controller
  380. */
  381. mmc->f_min = 450000;
  382. mmc->f_max = 24000000;
  383. mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
  384. mmc->caps |= MMC_CAP_4_BIT_DATA;
  385. mmc->max_seg_size = 1024 * 512;
  386. mmc->max_blk_size = 512;
  387. /* reset the controller */
  388. if (sdricoh_reset(host)) {
  389. dev_dbg(dev, "could not reset\n");
  390. result = -EIO;
  391. goto err;
  392. }
  393. result = mmc_add_host(mmc);
  394. if (!result) {
  395. dev_dbg(dev, "mmc host registered\n");
  396. return 0;
  397. }
  398. err:
  399. if (iobase)
  400. pci_iounmap(pci_dev, iobase);
  401. if (mmc)
  402. mmc_free_host(mmc);
  403. return result;
  404. }
  405. /* search for supported mmc controllers */
  406. static int sdricoh_pcmcia_probe(struct pcmcia_device *pcmcia_dev)
  407. {
  408. struct pci_dev *pci_dev = NULL;
  409. dev_info(&pcmcia_dev->dev, "Searching MMC controller for pcmcia device"
  410. " %s %s ...\n", pcmcia_dev->prod_id[0], pcmcia_dev->prod_id[1]);
  411. /* search pci cardbus bridge that contains the mmc controller */
  412. /* the io region is already claimed by yenta_socket... */
  413. while ((pci_dev =
  414. pci_get_device(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476,
  415. pci_dev))) {
  416. /* try to init the device */
  417. if (!sdricoh_init_mmc(pci_dev, pcmcia_dev)) {
  418. dev_info(&pcmcia_dev->dev, "MMC controller found\n");
  419. return 0;
  420. }
  421. }
  422. dev_err(&pcmcia_dev->dev, "No MMC controller was found.\n");
  423. return -ENODEV;
  424. }
  425. static void sdricoh_pcmcia_detach(struct pcmcia_device *link)
  426. {
  427. struct mmc_host *mmc = link->priv;
  428. dev_dbg(&link->dev, "detach\n");
  429. /* remove mmc host */
  430. if (mmc) {
  431. struct sdricoh_host *host = mmc_priv(mmc);
  432. mmc_remove_host(mmc);
  433. pci_iounmap(host->pci_dev, host->iobase);
  434. pci_dev_put(host->pci_dev);
  435. mmc_free_host(mmc);
  436. }
  437. pcmcia_disable_device(link);
  438. }
  439. #ifdef CONFIG_PM
  440. static int sdricoh_pcmcia_suspend(struct pcmcia_device *link)
  441. {
  442. struct mmc_host *mmc = link->priv;
  443. dev_dbg(&link->dev, "suspend\n");
  444. mmc_suspend_host(mmc);
  445. return 0;
  446. }
  447. static int sdricoh_pcmcia_resume(struct pcmcia_device *link)
  448. {
  449. struct mmc_host *mmc = link->priv;
  450. dev_dbg(&link->dev, "resume\n");
  451. sdricoh_reset(mmc_priv(mmc));
  452. mmc_resume_host(mmc);
  453. return 0;
  454. }
  455. #else
  456. #define sdricoh_pcmcia_suspend NULL
  457. #define sdricoh_pcmcia_resume NULL
  458. #endif
  459. static struct pcmcia_driver sdricoh_driver = {
  460. .name = DRIVER_NAME,
  461. .probe = sdricoh_pcmcia_probe,
  462. .remove = sdricoh_pcmcia_detach,
  463. .id_table = pcmcia_ids,
  464. .suspend = sdricoh_pcmcia_suspend,
  465. .resume = sdricoh_pcmcia_resume,
  466. };
  467. /*****************************************************************************\
  468. * *
  469. * Driver init/exit *
  470. * *
  471. \*****************************************************************************/
  472. static int __init sdricoh_drv_init(void)
  473. {
  474. return pcmcia_register_driver(&sdricoh_driver);
  475. }
  476. static void __exit sdricoh_drv_exit(void)
  477. {
  478. pcmcia_unregister_driver(&sdricoh_driver);
  479. }
  480. module_init(sdricoh_drv_init);
  481. module_exit(sdricoh_drv_exit);
  482. module_param(switchlocked, uint, 0444);
  483. MODULE_AUTHOR("Sascha Sommer <saschasommer@freenet.de>");
  484. MODULE_DESCRIPTION("Ricoh PCMCIA Secure Digital Interface driver");
  485. MODULE_LICENSE("GPL");
  486. MODULE_PARM_DESC(switchlocked, "Switch the cards locked status."
  487. "Use this when unlocked cards are shown readonly (default 0)");