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/Documentation/devicetree/bindings/clock/clock-bindings.txt

https://bitbucket.org/emiliolopez/linux
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Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
  1. This binding is a work-in-progress, and are based on some experimental
  2. work by benh[1].
  3. Sources of clock signal can be represented by any node in the device
  4. tree. Those nodes are designated as clock providers. Clock consumer
  5. nodes use a phandle and clock specifier pair to connect clock provider
  6. outputs to clock inputs. Similar to the gpio specifiers, a clock
  7. specifier is an array of zero, one or more cells identifying the clock
  8. output on a device. The length of a clock specifier is defined by the
  9. value of a #clock-cells property in the clock provider node.
  10. [1] http://patchwork.ozlabs.org/patch/31551/
  11. ==Clock providers==
  12. Required properties:
  13. #clock-cells: Number of cells in a clock specifier; Typically 0 for nodes
  14. with a single clock output and 1 for nodes with multiple
  15. clock outputs.
  16. Optional properties:
  17. clock-output-names: Recommended to be a list of strings of clock output signal
  18. names indexed by the first cell in the clock specifier.
  19. However, the meaning of clock-output-names is domain
  20. specific to the clock provider, and is only provided to
  21. encourage using the same meaning for the majority of clock
  22. providers. This format may not work for clock providers
  23. using a complex clock specifier format. In those cases it
  24. is recommended to omit this property and create a binding
  25. specific names property.
  26. Clock consumer nodes must never directly reference
  27. the provider's clock-output-names property.
  28. For example:
  29. oscillator {
  30. #clock-cells = <1>;
  31. clock-output-names = "ckil", "ckih";
  32. };
  33. - this node defines a device with two clock outputs, the first named
  34. "ckil" and the second named "ckih". Consumer nodes always reference
  35. clocks by index. The names should reflect the clock output signal
  36. names for the device.
  37. clock-indices: If the identifying number for the clocks in the node
  38. is not linear from zero, then this allows the mapping of
  39. identifiers into the clock-output-names array.
  40. For example, if we have two clocks <&oscillator 1> and <&oscillator 3>:
  41. oscillator {
  42. compatible = "myclocktype";
  43. #clock-cells = <1>;
  44. clock-indices = <1>, <3>;
  45. clock-output-names = "clka", "clkb";
  46. }
  47. This ensures we do not have any empty strings in clock-output-names
  48. ==Clock consumers==
  49. Required properties:
  50. clocks: List of phandle and clock specifier pairs, one pair
  51. for each clock input to the device. Note: if the
  52. clock provider specifies '0' for #clock-cells, then
  53. only the phandle portion of the pair will appear.
  54. Optional properties:
  55. clock-names: List of clock input name strings sorted in the same
  56. order as the clocks property. Consumers drivers
  57. will use clock-names to match clock input names
  58. with clocks specifiers.
  59. clock-ranges: Empty property indicating that child nodes can inherit named
  60. clocks from this node. Useful for bus nodes to provide a
  61. clock to their children.
  62. For example:
  63. device {
  64. clocks = <&osc 1>, <&ref 0>;
  65. clock-names = "baud", "register";
  66. };
  67. This represents a device with two clock inputs, named "baud" and "register".
  68. The baud clock is connected to output 1 of the &osc device, and the register
  69. clock is connected to output 0 of the &ref.
  70. ==Example==
  71. /* external oscillator */
  72. osc: oscillator {
  73. compatible = "fixed-clock";
  74. #clock-cells = <1>;
  75. clock-frequency = <32678>;
  76. clock-output-names = "osc";
  77. };
  78. /* phase-locked-loop device, generates a higher frequency clock
  79. * from the external oscillator reference */
  80. pll: pll@4c000 {
  81. compatible = "vendor,some-pll-interface"
  82. #clock-cells = <1>;
  83. clocks = <&osc 0>;
  84. clock-names = "ref";
  85. reg = <0x4c000 0x1000>;
  86. clock-output-names = "pll", "pll-switched";
  87. };
  88. /* UART, using the low frequency oscillator for the baud clock,
  89. * and the high frequency switched PLL output for register
  90. * clocking */
  91. uart@a000 {
  92. compatible = "fsl,imx-uart";
  93. reg = <0xa000 0x1000>;
  94. interrupts = <33>;
  95. clocks = <&osc 0>, <&pll 1>;
  96. clock-names = "baud", "register";
  97. };
  98. This DT fragment defines three devices: an external oscillator to provide a
  99. low-frequency reference clock, a PLL device to generate a higher frequency
  100. clock signal, and a UART.
  101. * The oscillator is fixed-frequency, and provides one clock output, named "osc".
  102. * The PLL is both a clock provider and a clock consumer. It uses the clock
  103. signal generated by the external oscillator, and provides two output signals
  104. ("pll" and "pll-switched").
  105. * The UART has its baud clock connected the external oscillator and its
  106. register clock connected to the PLL clock (the "pll-switched" signal)
  107. ==Assigned clock parents and rates==
  108. Some platforms may require initial configuration of default parent clocks
  109. and clock frequencies. Such a configuration can be specified in a device tree
  110. node through assigned-clocks, assigned-clock-parents and assigned-clock-rates
  111. properties. The assigned-clock-parents property should contain a list of parent
  112. clocks in the form of a phandle and clock specifier pair and the
  113. assigned-clock-rates property should contain a list of frequencies in Hz. Both
  114. these properties should correspond to the clocks listed in the assigned-clocks
  115. property.
  116. To skip setting parent or rate of a clock its corresponding entry should be
  117. set to 0, or can be omitted if it is not followed by any non-zero entry.
  118. uart@a000 {
  119. compatible = "fsl,imx-uart";
  120. reg = <0xa000 0x1000>;
  121. ...
  122. clocks = <&osc 0>, <&pll 1>;
  123. clock-names = "baud", "register";
  124. assigned-clocks = <&clkcon 0>, <&pll 2>;
  125. assigned-clock-parents = <&pll 2>;
  126. assigned-clock-rates = <0>, <460800>;
  127. };
  128. In this example the <&pll 2> clock is set as parent of clock <&clkcon 0> and
  129. the <&pll 2> clock is assigned a frequency value of 460800 Hz.
  130. Configuring a clock's parent and rate through the device node that consumes
  131. the clock can be done only for clocks that have a single user. Specifying
  132. conflicting parent or rate configuration in multiple consumer nodes for
  133. a shared clock is forbidden.
  134. Configuration of common clocks, which affect multiple consumer devices can
  135. be similarly specified in the clock provider node.