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/tags/sdcc-260-pre2/sdcc/sim/ucsim/z80.src/z80.cc

#
C++ | 629 lines | 449 code | 95 blank | 85 comment | 59 complexity | e6b83702599509b4c855e61b060db2f1 MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, LGPL-2.1, GPL-3.0 
    

  1. /*
    2. 

  2.  * Simulator of microcontrollers (z80.cc)
    3. 

  3.  *
    4. 

  4.  * some z80 code base from Karl Bongers karl@turbobit.com
    5. 

  5.  * 
    6. 

  6.  * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
    7. 

  7.  * 
    8. 

  8.  * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
    9. 

  9.  *
    10. 

  10.  */
    11. 

  11. 

  12. /* This file is part of microcontroller simulator: ucsim.
    13. 

    14. 

  14. UCSIM is free software; you can redistribute it and/or modify
    15. 

  15. it under the terms of the GNU General Public License as published by
    16. 

  16. the Free Software Foundation; either version 2 of the License, or
    17. 

  17. (at your option) any later version.
    18. 

    19. 

  19. UCSIM is distributed in the hope that it will be useful,
    20. 

  20. but WITHOUT ANY WARRANTY; without even the implied warranty of
    21. 

  21. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    22. 

  22. GNU General Public License for more details.
    23. 

    24. 

  24. You should have received a copy of the GNU General Public License
    25. 

  25. along with UCSIM; see the file COPYING.  If not, write to the Free
    26. 

  26. Software Foundation, 59 Temple Place - Suite 330, Boston, MA
    27. 

  27. 02111-1307, USA. */
    28. 

  28. /*@1@*/
    29. 

  29. 

  30. #include "ddconfig.h"
    31. 

  31. 

  32. #include <stdarg.h> /* for va_list */
    33. 

  33. #include <stdio.h>
    34. 

  34. #include <stdlib.h>
    35. 

  35. #include <ctype.h>
    36. 

  36. #include "i_string.h"
    37. 

  37. 

  38. // prj
    39. 

  39. #include "pobjcl.h"
    40. 

  40. 

  41. // sim
    42. 

  42. #include "simcl.h"
    43. 

  43. 

  44. // local
    45. 

  45. #include "z80cl.h"
    46. 

  46. #include "glob.h"
    47. 

  47. #include "regsz80.h"
    48. 

  48. 

  49. #define uint32 t_addr
    50. 

  50. #define uint8 unsigned char
    51. 

  51. #define int8 char
    52. 

  52. 

  53. /*******************************************************************/
    54. 

  54. 

  55. 

  56. /*
    57. 

  57.  * Base type of Z80 controllers
    58. 

  58.  */
    59. 

  59. 

  60. cl_z80::cl_z80(class cl_sim *asim):
    61. 

  61.   cl_uc(asim)
    62. 

  62. {
    63. 

  63.   type= CPU_Z80;
    64. 

  64. }
    65. 

  65. 

  66. int
    67. 

  67. cl_z80::init(void)
    68. 

  68. {
    69. 

  69.   cl_uc::init(); /* Memories now exist */
    70. 

  70. 

  71.   rom= address_space(MEM_ROM_ID);
    72. 

  72. //  ram= mem(MEM_XRAM);
    73. 

  73.   ram= rom;
    74. 

  74. 

  75.   // zero out ram(this is assumed in regression tests)
    76. 

  76.   for (int i=0x8000; i<0x10000; i++) {
    77. 

  77.     ram->set((t_addr) i, 0);
    78. 

  78.   }
    79. 

  79. 

  80.   return(0);
    81. 

  81. }
    82. 

  82. 

  83. char *
    84. 

  84. cl_z80::id_string(void)
    85. 

  85. {
    86. 

  86.   return("unspecified Z80");
    87. 

  87. }
    88. 

  88. 

  89. 

  90. /*
    91. 

  91.  * Making elements of the controller
    92. 

  92.  */
    93. 

  93. /*
    94. 

  94. t_addr
    95. 

  95. cl_z80::get_mem_size(enum mem_class type)
    96. 

  96. {
    97. 

  97.   switch(type)
    98. 

  98.     {
    99. 

  99.     case MEM_ROM: return(0x10000);
    100. 

  100.     case MEM_XRAM: return(0x10000);
    101. 

  101.     default: return(0);
    102. 

  102.     }
    103. 

  103.  return(cl_uc::get_mem_size(type));
    104. 

  104. }
    105. 

  105. */
    106. 

  106. 

  107. void
    108. 

  108. cl_z80::mk_hw_elements(void)
    109. 

  109. {
    110. 

  110.   //class cl_base *o;
    111. 

  111.   /* t_uc::mk_hw() does nothing */
    112. 

  112. }
    113. 

  113. 

  114. void
    115. 

  115. cl_z80::make_memories(void)
    116. 

  116. {
    117. 

  117.   class cl_address_space *as;
    118. 

  118. 

  119.   as= new cl_address_space("rom", 0, 0x10000, 8);
    120. 

  120.   as->init();
    121. 

  121.   address_spaces->add(as);
    122. 

  122. 

  123.   class cl_address_decoder *ad;
    124. 

  124.   class cl_memory_chip *chip;
    125. 

  125. 

  126.   chip= new cl_memory_chip("rom_chip", 0x10000, 8);
    127. 

  127.   chip->init();
    128. 

  128.   memchips->add(chip);
    129. 

  129.   ad= new cl_address_decoder(as= address_space("rom"), chip, 0, 0xffff, 0);
    130. 

  130.   ad->init();
    131. 

  131.   as->decoders->add(ad);
    132. 

  132.   ad->activate(0);
    133. 

  133. }
    134. 

  134. 

  135. 

  136. /*
    137. 

  137.  * Help command interpreter
    138. 

  138.  */
    139. 

  139. 

  140. struct dis_entry *
    141. 

  141. cl_z80::dis_tbl(void)
    142. 

  142. {
    143. 

  143.   return(disass_z80);
    144. 

  144. }
    145. 

  145. 

  146. /*struct name_entry *
    147. 

  147. cl_z80::sfr_tbl(void)
    148. 

  148. {
    149. 

  149.   return(0);
    150. 

  150. }*/
    151. 

  151. 

  152. /*struct name_entry *
    153. 

  153. cl_z80::bit_tbl(void)
    154. 

  154. {
    155. 

  155.   //FIXME
    156. 

  156.   return(0);
    157. 

  157. }*/
    158. 

  158. 

  159. int
    160. 

  160. cl_z80::inst_length(t_addr addr)
    161. 

  161. {
    162. 

  162.   int len = 0;
    163. 

  163.   char *s;
    164. 

  164. 

  165.   s = get_disasm_info(addr, &len, NULL, NULL);
    166. 

  166. 

  167.   return len;
    168. 

  168. }
    169. 

  169. 

  170. int
    171. 

  171. cl_z80::inst_branch(t_addr addr)
    172. 

  172. {
    173. 

  173.   int b;
    174. 

  174.   char *s;
    175. 

  175. 

  176.   s = get_disasm_info(addr, NULL, &b, NULL);
    177. 

  177. 

  178.   return b;
    179. 

  179. }
    180. 

  180. 

  181. int
    182. 

  182. cl_z80::longest_inst(void)
    183. 

  183. {
    184. 

  184.   return 4;
    185. 

  185. }
    186. 

  186. 

  187. 

  188. char *
    189. 

  189. cl_z80::get_disasm_info(t_addr addr,
    190. 

  190.                         int *ret_len,
    191. 

  191.                         int *ret_branch,
    192. 

  192.                         int *immed_offset)
    193. 

  193. {
    194. 

  194.   char *b = NULL;
    195. 

  195.   uint code;
    196. 

  196.   int len = 0;
    197. 

  197.   int immed_n = 0;
    198. 

  198.   int i;
    199. 

  199.   int start_addr = addr;
    200. 

  200.   struct dis_entry *dis_e;
    201. 

  201. 

  202.   code= get_mem(MEM_ROM_ID, addr++);
    203. 

  203.   dis_e = NULL;
    204. 

  204. 

  205.   switch(code) {
    206. 

  206.     case 0xcb:  /* ESC code to lots of op-codes, all 2-byte */
    207. 

  207.       code= get_mem(MEM_ROM_ID, addr++);
    208. 

  208.       i= 0;
    209. 

  209.       while ((code & disass_z80_cb[i].mask) != disass_z80_cb[i].code &&
    210. 

  210.         disass_z80_cb[i].mnemonic)
    211. 

  211.         i++;
    212. 

  212.       dis_e = &disass_z80_cb[i];
    213. 

  213.       b= disass_z80_cb[i].mnemonic;
    214. 

  214.       if (b != NULL)
    215. 

  215.         len += (disass_z80_cb[i].length + 1);
    216. 

  216.     break;
    217. 

  217. 

  218.     case 0xed: /* ESC code to about 80 opcodes of various lengths */
    219. 

  219.       code= get_mem(MEM_ROM_ID, addr++);
    220. 

  220.       i= 0;
    221. 

  221.       while ((code & disass_z80_ed[i].mask) != disass_z80_ed[i].code &&
    222. 

  222.         disass_z80_ed[i].mnemonic)
    223. 

  223.         i++;
    224. 

  224.       dis_e = &disass_z80_ed[i];
    225. 

  225.       b= disass_z80_ed[i].mnemonic;
    226. 

  226.       if (b != NULL)
    227. 

  227.         len += (disass_z80_ed[i].length + 1);
    228. 

  228.     break;
    229. 

  229. 

  230.     case 0xdd: /* ESC codes,about 284, vary lengths, IX centric */
    231. 

  231.       code= get_mem(MEM_ROM_ID, addr++);
    232. 

  232.       if (code == 0xcb) {
    233. 

  233.         immed_n = 2;
    234. 

  234.         addr++;  // pass up immed data
    235. 

  235.         code= get_mem(MEM_ROM_ID, addr++);
    236. 

  236.         i= 0;
    237. 

  237.         while ((code & disass_z80_ddcb[i].mask) != disass_z80_ddcb[i].code &&
    238. 

  238.           disass_z80_ddcb[i].mnemonic)
    239. 

  239.           i++;
    240. 

  240.         dis_e = &disass_z80_ddcb[i];
    241. 

  241.         b= disass_z80_ddcb[i].mnemonic;
    242. 

  242.         if (b != NULL)
    243. 

  243.           len += (disass_z80_ddcb[i].length + 2);
    244. 

  244.       } else {
    245. 

  245.         i= 0;
    246. 

  246.         while ((code & disass_z80_dd[i].mask) != disass_z80_dd[i].code &&
    247. 

  247.           disass_z80_dd[i].mnemonic)
    248. 

  248.           i++;
    249. 

  249.         dis_e = &disass_z80_dd[i];
    250. 

  250.         b= disass_z80_dd[i].mnemonic;
    251. 

  251.         if (b != NULL)
    252. 

  252.           len += (disass_z80_dd[i].length + 1);
    253. 

  253.       }
    254. 

  254.     break;
    255. 

  255. 

  256.     case 0xfd: /* ESC codes,sme as dd but IY centric */
    257. 

  257.       code= get_mem(MEM_ROM_ID, addr++);
    258. 

  258.       if (code == 0xcb) {
    259. 

  259.         immed_n = 2;
    260. 

  260.         addr++;  // pass up immed data
    261. 

  261.         code= get_mem(MEM_ROM_ID, addr++);
    262. 

  262.         i= 0;
    263. 

  263.         while ((code & disass_z80_fdcb[i].mask) != disass_z80_fdcb[i].code &&
    264. 

  264.           disass_z80_fdcb[i].mnemonic)
    265. 

  265.           i++;
    266. 

  266.         dis_e = &disass_z80_fdcb[i];
    267. 

  267.         b= disass_z80_fdcb[i].mnemonic;
    268. 

  268.         if (b != NULL)
    269. 

  269.           len += (disass_z80_fdcb[i].length + 2);
    270. 

  270.       } else {
    271. 

  271.         i= 0;
    272. 

  272.         while ((code & disass_z80_fd[i].mask) != disass_z80_fd[i].code &&
    273. 

  273.           disass_z80_fd[i].mnemonic)
    274. 

  274.           i++;
    275. 

  275.         dis_e = &disass_z80_fd[i];
    276. 

  276.         b= disass_z80_fd[i].mnemonic;
    277. 

  277.         if (b != NULL)
    278. 

  278.           len += (disass_z80_fd[i].length + 1);
    279. 

  279.       }
    280. 

  280.     break;
    281. 

  281. 

  282.     default:
    283. 

  283.       i= 0;
    284. 

  284.       while ((code & disass_z80[i].mask) != disass_z80[i].code &&
    285. 

  285.              disass_z80[i].mnemonic)
    286. 

  286.         i++;
    287. 

  287.       dis_e = &disass_z80[i];
    288. 

  288.       b= disass_z80[i].mnemonic;
    289. 

  289.       if (b != NULL)
    290. 

  290.         len += (disass_z80[i].length);
    291. 

  291.     break;
    292. 

  292.   }
    293. 

  293. 

  294. 

  295.   if (ret_branch) {
    296. 

  296.     *ret_branch = dis_e->branch;
    297. 

  297.   }
    298. 

  298. 

  299.   if (immed_offset) {
    300. 

  300.     if (immed_n > 0)
    301. 

  301.          *immed_offset = immed_n;
    302. 

  302.     else *immed_offset = (addr - start_addr);
    303. 

  303.   }
    304. 

  304. 

  305.   if (len == 0)
    306. 

  306.     len = 1;
    307. 

  307. 

  308.   if (ret_len)
    309. 

  309.     *ret_len = len;
    310. 

  310. 

  311.   return b;
    312. 

  312. }
    313. 

  313. 

  314. char *
    315. 

  315. cl_z80::disass(t_addr addr, char *sep)
    316. 

  316. {
    317. 

  317.   char work[256], temp[20];
    318. 

  318.   char *buf, *p, *b, *t;
    319. 

  319.   int len = 0;
    320. 

  320.   int immed_offset = 0;
    321. 

  321. 

  322.   p= work;
    323. 

  323. 

  324.   b = get_disasm_info(addr, &len, NULL, &immed_offset);
    325. 

  325.   
    326. 

  326.   if (b == NULL) {
    327. 

  327.     buf= (char*)malloc(30);
    328. 

  328.     strcpy(buf, "UNKNOWN/INVALID");
    329. 

  329.     return(buf);
    330. 

  330.   }
    331. 

  331. 

  332.   while (*b)
    333. 

  333.     {
    334. 

  334.       if (*b == '%')
    335. 

  335. 	{
    336. 

  336. 	  b++;
    337. 

  337. 	  switch (*(b++))
    338. 

  338. 	    {
    339. 

  339. 	    case 'd': // d    jump relative target, signed? byte immediate operand
    340. 

  340. 	      sprintf(temp, "#%d", (char)get_mem(MEM_ROM_ID, addr+immed_offset));
    341. 

  341. 	      ++immed_offset;
    342. 

  342. 	      break;
    343. 

  343. 	    case 'w': // w    word immediate operand
    344. 

  344. 	      sprintf(temp, "#0x%04x",
    345. 

  345. 	         (uint)((get_mem(MEM_ROM_ID, addr+immed_offset)) |
    346. 

  346. 	                (get_mem(MEM_ROM_ID, addr+immed_offset+1)<<8)) );
    347. 

  347. 	      ++immed_offset;
    348. 

  348. 	      ++immed_offset;
    349. 

  349. 	      break;
    350. 

  350. 	    case 'b': // b    byte immediate operand
    351. 

  351. 	      sprintf(temp, "#0x%02x", (uint)get_mem(MEM_ROM_ID, addr+immed_offset));
    352. 

  352. 	      ++immed_offset;
    353. 

  353. 	      break;
    354. 

  354. 	    default:
    355. 

  355. 	      strcpy(temp, "?");
    356. 

  356. 	      break;
    357. 

  357. 	    }
    358. 

  358. 	  t= temp;
    359. 

  359. 	  while (*t)
    360. 

  360. 	    *(p++)= *(t++);
    361. 

  361. 	}
    362. 

  362.       else
    363. 

  363. 	*(p++)= *(b++);
    364. 

  364.     }
    365. 

  365.   *p= '\0';
    366. 

  366. 

  367.   p= strchr(work, ' ');
    368. 

  368.   if (!p)
    369. 

  369.     {
    370. 

  370.       buf= strdup(work);
    371. 

  371.       return(buf);
    372. 

  372.     }
    373. 

  373.   if (sep == NULL)
    374. 

  374.     buf= (char *)malloc(6+strlen(p)+1);
    375. 

  375.   else
    376. 

  376.     buf= (char *)malloc((p-work)+strlen(sep)+strlen(p)+1);
    377. 

  377.   for (p= work, b= buf; *p != ' '; p++, b++)
    378. 

  378.     *b= *p;
    379. 

  379.   p++;
    380. 

  380.   *b= '\0';
    381. 

  381.   if (sep == NULL)
    382. 

  382.     {
    383. 

  383.       while (strlen(buf) < 6)
    384. 

  384. 	strcat(buf, " ");
    385. 

  385.     }
    386. 

  386.   else
    387. 

  387.     strcat(buf, sep);
    388. 

  388.   strcat(buf, p);
    389. 

  389.   return(buf);
    390. 

  390. }
    391. 

  391. 

  392. 

  393. void
    394. 

  394. cl_z80::print_regs(class cl_console *con)
    395. 

  395. {
    396. 

  396.   con->dd_printf("SZ-A--P-C  Flags= 0x%02x %3d %c  ",
    397. 

  397. 		 regs.F, regs.F, isprint(regs.F)?regs.F:'.');
    398. 

  398.   con->dd_printf("A= 0x%02x %3d %c\n",
    399. 

  399. 		 regs.A, regs.A, isprint(regs.A)?regs.A:'.');
    400. 

  400.   con->dd_printf("%c%c-%c--%c-%c\n",
    401. 

  401. 		 (regs.F&BIT_S)?'1':'0',
    402. 

  402. 		 (regs.F&BIT_Z)?'1':'0',
    403. 

  403. 		 (regs.F&BIT_A)?'1':'0',
    404. 

  404. 		 (regs.F&BIT_P)?'1':'0',
    405. 

  405. 		 (regs.F&BIT_C)?'1':'0');
    406. 

  406.   con->dd_printf("BC= 0x%04x [BC]= %02x %3d %c  ",
    407. 

  407. 		 regs.BC, ram->get(regs.BC), ram->get(regs.BC),
    408. 

  408. 		 isprint(ram->get(regs.BC))?ram->get(regs.BC):'.');
    409. 

  409.   con->dd_printf("DE= 0x%04x [DE]= %02x %3d %c  ",
    410. 

  410. 		 regs.DE, ram->get(regs.DE), ram->get(regs.DE),
    411. 

  411. 		 isprint(ram->get(regs.DE))?ram->get(regs.DE):'.');
    412. 

  412.   con->dd_printf("HL= 0x%04x [HL]= %02x %3d %c\n",
    413. 

  413. 		 regs.HL, ram->get(regs.HL), ram->get(regs.HL),
    414. 

  414. 		 isprint(ram->get(regs.HL))?ram->get(regs.HL):'.');
    415. 

  415.   con->dd_printf("IX= 0x%04x [IX]= %02x %3d %c  ",
    416. 

  416. 		 regs.IX, ram->get(regs.IX), ram->get(regs.IX),
    417. 

  417. 		 isprint(ram->get(regs.IX))?ram->get(regs.IX):'.');
    418. 

  418.   con->dd_printf("IY= 0x%04x [IY]= %02x %3d %c  ",
    419. 

  419. 		 regs.IY, ram->get(regs.IY), ram->get(regs.IY),
    420. 

  420. 		 isprint(ram->get(regs.IY))?ram->get(regs.IY):'.');
    421. 

  421.   con->dd_printf("SP= 0x%04x [SP]= %02x %3d %c\n",
    422. 

  422. 		 regs.SP, ram->get(regs.SP), ram->get(regs.SP),
    423. 

  423. 		 isprint(ram->get(regs.SP))?ram->get(regs.SP):'.');
    424. 

  424.   
    425. 

  425.   print_disass(PC, con);
    426. 

  426. }
    427. 

  427. 

  428. /*
    429. 

  429.  * Execution
    430. 

  430.  */
    431. 

  431. 

  432. int
    433. 

  433. cl_z80::exec_inst(void)
    434. 

  434. {
    435. 

  435.   t_mem code;
    436. 

  436. 

  437.   if (fetch(&code))
    438. 

  438.     return(resBREAKPOINT);
    439. 

  439.   tick(1);
    440. 

  440.   switch (code)
    441. 

  441.     {
    442. 

  442.     case 0x00: return(inst_nop(code));
    443. 

  443.     case 0x01: case 0x02: case 0x06: return(inst_ld(code));
    444. 

  444.     case 0x03: case 0x04: return(inst_inc(code));
    445. 

  445.     case 0x05: return(inst_dec(code));
    446. 

  446.     case 0x07: return(inst_rlca(code));
    447. 

  447. 

  448.     case 0x08: return(inst_ex(code));
    449. 

  449.     case 0x09: return(inst_add(code));
    450. 

  450.     case 0x0a: case 0x0e: return(inst_ld(code));
    451. 

  451.     case 0x0b: case 0x0d: return(inst_dec(code));
    452. 

  452.     case 0x0c: return(inst_inc(code));
    453. 

  453.     case 0x0f: return(inst_rrca(code));
    454. 

  454. 

  455. 

  456.     case 0x10: return(inst_djnz(code));
    457. 

  457.     case 0x11: case 0x12: case 0x16: return(inst_ld(code));
    458. 

  458.     case 0x13: case 0x14: return(inst_inc(code));
    459. 

  459.     case 0x15: return(inst_dec(code));
    460. 

  460.     case 0x17: return(inst_rla(code));
    461. 

  461. 

  462.     case 0x18: return(inst_jr(code));
    463. 

  463.     case 0x19: return(inst_add(code));
    464. 

  464.     case 0x1a: case 0x1e: return(inst_ld(code));
    465. 

  465.     case 0x1b: case 0x1d: return(inst_dec(code));
    466. 

  466.     case 0x1c: return(inst_inc(code));
    467. 

  467.     case 0x1f: return(inst_rra(code));
    468. 

  468. 

  469. 

  470.     case 0x20: return(inst_jr(code));
    471. 

  471.     case 0x21: case 0x22: case 0x26: return(inst_ld(code));
    472. 

  472.     case 0x23: case 0x24: return(inst_inc(code));
    473. 

  473.     case 0x25: return(inst_dec(code));
    474. 

  474.     case 0x27: return(inst_daa(code));
    475. 

  475. 

  476.     case 0x28: return(inst_jr(code));
    477. 

  477.     case 0x29: return(inst_add(code));
    478. 

  478.     case 0x2a: case 0x2e: return(inst_ld(code));
    479. 

  479.     case 0x2b: case 0x2d: return(inst_dec(code));
    480. 

  480.     case 0x2c: return(inst_inc(code));
    481. 

  481.     case 0x2f: return(inst_cpl(code));
    482. 

  482. 

  483. 

  484.     case 0x30: return(inst_jr(code));
    485. 

  485.     case 0x31: case 0x32: case 0x36: return(inst_ld(code));
    486. 

  486.     case 0x33: case 0x34: return(inst_inc(code));
    487. 

  487.     case 0x35: return(inst_dec(code));
    488. 

  488.     case 0x37: return(inst_scf(code));
    489. 

  489. 

  490.     case 0x38: return(inst_jr(code));
    491. 

  491.     case 0x39: return(inst_add(code));
    492. 

  492.     case 0x3a: case 0x3e: return(inst_ld(code));
    493. 

  493.     case 0x3b: case 0x3d: return(inst_dec(code));
    494. 

  494.     case 0x3c: return(inst_inc(code));
    495. 

  495.     case 0x3f: return(inst_ccf(code));
    496. 

  496. 

  497.     case 0x40: case 0x41: case 0x42: case 0x43: case 0x44: case 0x45: case 0x46: case 0x47:
    498. 

  498.     case 0x48: case 0x49: case 0x4a: case 0x4b: case 0x4c: case 0x4d: case 0x4e: case 0x4f:
    499. 

  499.       return(inst_ld(code));
    500. 

  500. 

  501.     case 0x50: case 0x51: case 0x52: case 0x53: case 0x54: case 0x55: case 0x56: case 0x57:
    502. 

  502.     case 0x58: case 0x59: case 0x5a: case 0x5b: case 0x5c: case 0x5d: case 0x5e: case 0x5f:
    503. 

  503.       return(inst_ld(code));
    504. 

  504. 

  505.     case 0x60: case 0x61: case 0x62: case 0x63: case 0x64: case 0x65: case 0x66: case 0x67:
    506. 

  506.     case 0x68: case 0x69: case 0x6a: case 0x6b: case 0x6c: case 0x6d: case 0x6e: case 0x6f:
    507. 

  507.       return(inst_ld(code));
    508. 

  508. 

  509.     case 0x70: case 0x71: case 0x72: case 0x73: case 0x74: case 0x75: case 0x77:
    510. 

  510.     case 0x78: case 0x79: case 0x7a: case 0x7b: case 0x7c: case 0x7d: case 0x7e: case 0x7f:
    511. 

  511.       return(inst_ld(code));
    512. 

  512.     case 0x76: 
    513. 

  513.       return(inst_halt(code));
    514. 

  514. 

  515.     case 0x80: case 0x81: case 0x82: case 0x83: case 0x84: case 0x85: case 0x86: case 0x87:
    516. 

  516.       return(inst_add(code));
    517. 

  517.     case 0x88: case 0x89: case 0x8a: case 0x8b: case 0x8c: case 0x8d: case 0x8e: case 0x8f:
    518. 

  518.       return(inst_adc(code));
    519. 

  519. 

  520.     case 0x90: case 0x91: case 0x92: case 0x93: case 0x94: case 0x95: case 0x96: case 0x97:
    521. 

  521.       return(inst_sub(code));
    522. 

  522.     case 0x98: case 0x99: case 0x9a: case 0x9b: case 0x9c: case 0x9d: case 0x9e: case 0x9f:
    523. 

  523.       return(inst_sbc(code));
    524. 

  524. 

  525.     case 0xa0: case 0xa1: case 0xa2: case 0xa3: case 0xa4: case 0xa5: case 0xa6: case 0xa7:
    526. 

  526.       return(inst_and(code));
    527. 

  527.     case 0xa8: case 0xa9: case 0xaa: case 0xab: case 0xac: case 0xad: case 0xae: case 0xaf:
    528. 

  528.       return(inst_xor(code));
    529. 

  529. 

  530.     case 0xb0: case 0xb1: case 0xb2: case 0xb3: case 0xb4: case 0xb5: case 0xb6: case 0xb7:
    531. 

  531.       return(inst_or(code));
    532. 

  532.     case 0xb8: case 0xb9: case 0xba: case 0xbb: case 0xbc: case 0xbd: case 0xbe: case 0xbf:
    533. 

  533.       return(inst_cp(code));
    534. 

  534. 

  535.     case 0xc0: return(inst_ret(code));
    536. 

  536.     case 0xc1: return(inst_pop(code));
    537. 

  537.     case 0xc2: case 0xc3: return(inst_jp(code));
    538. 

  538.     case 0xc4: return(inst_call(code));
    539. 

  539.     case 0xc5: return(inst_push(code));
    540. 

  540.     case 0xc6: return(inst_add(code));
    541. 

  541.     case 0xc7: return(inst_rst(code));
    542. 

  542. 

  543.     case 0xc8: case 0xc9: return(inst_ret(code));
    544. 

  544.     case 0xca: return(inst_jp(code));
    545. 

  545. 

  546.       /* CB escapes out to 2 byte opcodes(CB include), opcodes
    547. 

  547.          to do register bit manipulations */
    548. 

  548.     case 0xcb: return(inst_cb());
    549. 

  549.     case 0xcc: case 0xcd: return(inst_call(code));
    550. 

  550.     case 0xce: return(inst_adc(code));
    551. 

  551.     case 0xcf: return(inst_rst(code));
    552. 

  552. 

  553. 

  554.     case 0xd0: return(inst_ret(code));
    555. 

  555.     case 0xd1: return(inst_pop(code));
    556. 

  556.     case 0xd2: return(inst_jp(code));
    557. 

  557.     case 0xd3: return(inst_out(code));
    558. 

  558.     case 0xd4: return(inst_call(code));
    559. 

  559.     case 0xd5: return(inst_push(code));
    560. 

  560.     case 0xd6: return(inst_sub(code));
    561. 

  561.     case 0xd7: return(inst_rst(code));
    562. 

  562. 

  563.     case 0xd8: return(inst_ret(code));
    564. 

  564.     case 0xd9: return(inst_exx(code));
    565. 

  565.     case 0xda: return(inst_jp(code));
    566. 

  566.     case 0xdb: return(inst_in(code));
    567. 

  567.     case 0xdc: return(inst_call(code));
    568. 

  568.       /* DD escapes out to 2 to 4 byte opcodes(DD included)
    569. 

  569.         with a variety of uses.  It can precede the CB escape
    570. 

  570.         sequence to extend CB codes with IX+immed_byte */
    571. 

  571.     case 0xdd: return(inst_dd());
    572. 

  572.     case 0xde: return(inst_sbc(code));
    573. 

  573.     case 0xdf: return(inst_rst(code));
    574. 

  574. 

  575. 

  576.     case 0xe0: return(inst_ret(code));
    577. 

  577.     case 0xe1: return(inst_pop(code));
    578. 

  578.     case 0xe2: return(inst_jp(code));
    579. 

  579.     case 0xe3: return(inst_ex(code));
    580. 

  580.     case 0xe4: return(inst_call(code));
    581. 

  581.     case 0xe5: return(inst_push(code));
    582. 

  582.     case 0xe6: return(inst_and(code));
    583. 

  583.     case 0xe7: return(inst_rst(code));
    584. 

  584. 

  585.     case 0xe8: return(inst_ret(code));
    586. 

  586.     case 0xe9: return(inst_jp(code));
    587. 

  587.     case 0xea: return(inst_jp(code));
    588. 

  588.     case 0xeb: return(inst_ex(code));
    589. 

  589.     case 0xec: return(inst_call(code));
    590. 

  590.       /* ED escapes out to misc IN, OUT and other oddball opcodes */
    591. 

  591.     case 0xed: return(inst_ed());
    592. 

  592.     case 0xee: return(inst_xor(code));
    593. 

  593.     case 0xef: return(inst_rst(code));
    594. 

  594. 

  595. 

  596.     case 0xf0: return(inst_ret(code));
    597. 

  597.     case 0xf1: return(inst_pop(code));
    598. 

  598.     case 0xf2: return(inst_jp(code));
    599. 

  599.     case 0xf3: return(inst_di(code));
    600. 

  600.     case 0xf4: return(inst_call(code));
    601. 

  601.     case 0xf5: return(inst_push(code));
    602. 

  602.     case 0xf6: return(inst_or(code));
    603. 

  603.     case 0xf7: return(inst_rst(code));
    604. 

  604. 

  605.     case 0xf8: return(inst_ret(code));
    606. 

  606.     case 0xf9: return(inst_ld(code));
    607. 

  607.     case 0xfa: return(inst_jp(code));
    608. 

  608.     case 0xfb: return(inst_ei(code));
    609. 

  609.     case 0xfc: return(inst_call(code));
    610. 

  610.       /* DD escapes out to 2 to 4 byte opcodes(DD included)
    611. 

  611.         with a variety of uses.  It can precede the CB escape
    612. 

  612.         sequence to extend CB codes with IX+immed_byte */
    613. 

  613.     case 0xfd: return(inst_fd());
    614. 

  614.     case 0xfe: return(inst_cp(code));
    615. 

  615.     case 0xff: return(inst_rst(code));
    616. 

  616.     }
    617. 

  617. 

  618.   /*if (PC)
    619. 

  619.     PC--;
    620. 

  620.   else
    621. 

  621.   PC= get_mem_size(MEM_ROM_ID)-1;*/
    622. 

  622.   PC= rom->inc_address(PC, -1);
    623. 

  623. 

  624.   sim->stop(resINV_INST);
    625. 

  625.   return(resINV_INST);
    626. 

  626. }
    627. 

  627. 

  628. 

  629. /* End of z80.src/z80.cc */
    630. 

  630.