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/tags/sdcc-310/sim/ucsim/z80.src/z80.cc

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C++ | 661 lines | 473 code | 103 blank | 85 comment | 59 complexity | c20c1e4dcc3fdff355e395cdb6727e88 MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, LGPL-2.1, GPL-3.0
  1. /*
  2. * Simulator of microcontrollers (z80.cc)
  3. *
  4. * some z80 code base from Karl Bongers karl@turbobit.com
  5. *
  6. * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
  7. *
  8. * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
  9. *
  10. */
  11. /* This file is part of microcontroller simulator: ucsim.
  12. UCSIM is free software; you can redistribute it and/or modify
  13. it under the terms of the GNU General Public License as published by
  14. the Free Software Foundation; either version 2 of the License, or
  15. (at your option) any later version.
  16. UCSIM is distributed in the hope that it will be useful,
  17. but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. GNU General Public License for more details.
  20. You should have received a copy of the GNU General Public License
  21. along with UCSIM; see the file COPYING. If not, write to the Free
  22. Software Foundation, 59 Temple Place - Suite 330, Boston, MA
  23. 02111-1307, USA. */
  24. /*@1@*/
  25. #include "ddconfig.h"
  26. #include <stdarg.h> /* for va_list */
  27. #include <stdio.h>
  28. #include <stdlib.h>
  29. #include <ctype.h>
  30. #include "i_string.h"
  31. // prj
  32. #include "pobjcl.h"
  33. // sim
  34. #include "simcl.h"
  35. // local
  36. #include "z80cl.h"
  37. #include "glob.h"
  38. #include "regsz80.h"
  39. #define uint32 t_addr
  40. #define uint8 unsigned char
  41. /*******************************************************************/
  42. /*
  43. * Base type of Z80 controllers
  44. */
  45. cl_z80::cl_z80(int Itype, int Itech, class cl_sim *asim):
  46. cl_uc(asim)
  47. {
  48. type= Itype;
  49. }
  50. int
  51. cl_z80::init(void)
  52. {
  53. cl_uc::init(); /* Memories now exist */
  54. rom= address_space(MEM_ROM_ID);
  55. // ram= mem(MEM_XRAM);
  56. ram= rom;
  57. // zero out ram(this is assumed in regression tests)
  58. for (int i=0x8000; i<0x10000; i++) {
  59. ram->set((t_addr) i, 0);
  60. }
  61. return(0);
  62. }
  63. const char *
  64. cl_z80::id_string(void)
  65. {
  66. return("unspecified Z80");
  67. }
  68. /*
  69. * Making elements of the controller
  70. */
  71. /*
  72. t_addr
  73. cl_z80::get_mem_size(enum mem_class type)
  74. {
  75. switch(type)
  76. {
  77. case MEM_ROM: return(0x10000);
  78. case MEM_XRAM: return(0x10000);
  79. default: return(0);
  80. }
  81. return(cl_uc::get_mem_size(type));
  82. }
  83. */
  84. void
  85. cl_z80::mk_hw_elements(void)
  86. {
  87. //class cl_base *o;
  88. /* t_uc::mk_hw() does nothing */
  89. }
  90. void
  91. cl_z80::make_memories(void)
  92. {
  93. class cl_address_space *as;
  94. as= new cl_address_space("rom", 0, 0x10000, 8);
  95. as->init();
  96. address_spaces->add(as);
  97. class cl_address_decoder *ad;
  98. class cl_memory_chip *chip;
  99. chip= new cl_memory_chip("rom_chip", 0x10000, 8);
  100. chip->init();
  101. memchips->add(chip);
  102. ad= new cl_address_decoder(as= address_space("rom"), chip, 0, 0xffff, 0);
  103. ad->init();
  104. as->decoders->add(ad);
  105. ad->activate(0);
  106. }
  107. /*
  108. * Help command interpreter
  109. */
  110. struct dis_entry *
  111. cl_z80::dis_tbl(void)
  112. {
  113. return(disass_z80);
  114. }
  115. /*struct name_entry *
  116. cl_z80::sfr_tbl(void)
  117. {
  118. return(0);
  119. }*/
  120. /*struct name_entry *
  121. cl_z80::bit_tbl(void)
  122. {
  123. //FIXME
  124. return(0);
  125. }*/
  126. int
  127. cl_z80::inst_length(t_addr addr)
  128. {
  129. int len = 0;
  130. get_disasm_info(addr, &len, NULL, NULL);
  131. return len;
  132. }
  133. int
  134. cl_z80::inst_branch(t_addr addr)
  135. {
  136. int b;
  137. get_disasm_info(addr, NULL, &b, NULL);
  138. return b;
  139. }
  140. int
  141. cl_z80::longest_inst(void)
  142. {
  143. return 4;
  144. }
  145. const char *
  146. cl_z80::get_disasm_info(t_addr addr,
  147. int *ret_len,
  148. int *ret_branch,
  149. int *immed_offset)
  150. {
  151. const char *b = NULL;
  152. uint code;
  153. int len = 0;
  154. int immed_n = 0;
  155. int i;
  156. int start_addr = addr;
  157. struct dis_entry *dis_e;
  158. code= get_mem(MEM_ROM_ID, addr++);
  159. dis_e = NULL;
  160. switch(code) {
  161. case 0xcb: /* ESC code to lots of op-codes, all 2-byte */
  162. code= get_mem(MEM_ROM_ID, addr++);
  163. i= 0;
  164. while ((code & disass_z80_cb[i].mask) != disass_z80_cb[i].code &&
  165. disass_z80_cb[i].mnemonic)
  166. i++;
  167. dis_e = &disass_z80_cb[i];
  168. b= disass_z80_cb[i].mnemonic;
  169. if (b != NULL)
  170. len += (disass_z80_cb[i].length + 1);
  171. break;
  172. case 0xed: /* ESC code to about 80 opcodes of various lengths */
  173. code= get_mem(MEM_ROM_ID, addr++);
  174. i= 0;
  175. while ((code & disass_z80_ed[i].mask) != disass_z80_ed[i].code &&
  176. disass_z80_ed[i].mnemonic)
  177. i++;
  178. dis_e = &disass_z80_ed[i];
  179. b= disass_z80_ed[i].mnemonic;
  180. if (b != NULL)
  181. len += (disass_z80_ed[i].length + 1);
  182. break;
  183. case 0xdd: /* ESC codes,about 284, vary lengths, IX centric */
  184. code= get_mem(MEM_ROM_ID, addr++);
  185. if (code == 0xcb) {
  186. immed_n = 2;
  187. addr++; // pass up immed data
  188. code= get_mem(MEM_ROM_ID, addr++);
  189. i= 0;
  190. while ((code & disass_z80_ddcb[i].mask) != disass_z80_ddcb[i].code &&
  191. disass_z80_ddcb[i].mnemonic)
  192. i++;
  193. dis_e = &disass_z80_ddcb[i];
  194. b= disass_z80_ddcb[i].mnemonic;
  195. if (b != NULL)
  196. len += (disass_z80_ddcb[i].length + 2);
  197. } else {
  198. i= 0;
  199. while ((code & disass_z80_dd[i].mask) != disass_z80_dd[i].code &&
  200. disass_z80_dd[i].mnemonic)
  201. i++;
  202. dis_e = &disass_z80_dd[i];
  203. b= disass_z80_dd[i].mnemonic;
  204. if (b != NULL)
  205. len += (disass_z80_dd[i].length + 1);
  206. }
  207. break;
  208. case 0xfd: /* ESC codes,sme as dd but IY centric */
  209. code= get_mem(MEM_ROM_ID, addr++);
  210. if (code == 0xcb) {
  211. immed_n = 2;
  212. addr++; // pass up immed data
  213. code= get_mem(MEM_ROM_ID, addr++);
  214. i= 0;
  215. while ((code & disass_z80_fdcb[i].mask) != disass_z80_fdcb[i].code &&
  216. disass_z80_fdcb[i].mnemonic)
  217. i++;
  218. dis_e = &disass_z80_fdcb[i];
  219. b= disass_z80_fdcb[i].mnemonic;
  220. if (b != NULL)
  221. len += (disass_z80_fdcb[i].length + 2);
  222. } else {
  223. i= 0;
  224. while ((code & disass_z80_fd[i].mask) != disass_z80_fd[i].code &&
  225. disass_z80_fd[i].mnemonic)
  226. i++;
  227. dis_e = &disass_z80_fd[i];
  228. b= disass_z80_fd[i].mnemonic;
  229. if (b != NULL)
  230. len += (disass_z80_fd[i].length + 1);
  231. }
  232. break;
  233. default:
  234. i= 0;
  235. while ((code & disass_z80[i].mask) != disass_z80[i].code &&
  236. disass_z80[i].mnemonic)
  237. i++;
  238. dis_e = &disass_z80[i];
  239. b= disass_z80[i].mnemonic;
  240. if (b != NULL)
  241. len += (disass_z80[i].length);
  242. break;
  243. }
  244. if (ret_branch) {
  245. *ret_branch = dis_e->branch;
  246. }
  247. if (immed_offset) {
  248. if (immed_n > 0)
  249. *immed_offset = immed_n;
  250. else *immed_offset = (addr - start_addr);
  251. }
  252. if (len == 0)
  253. len = 1;
  254. if (ret_len)
  255. *ret_len = len;
  256. return b;
  257. }
  258. const char *
  259. cl_z80::disass(t_addr addr, const char *sep)
  260. {
  261. char work[256], temp[20];
  262. const char *b;
  263. char *buf, *p, *t;
  264. int len = 0;
  265. int immed_offset = 0;
  266. p= work;
  267. b = get_disasm_info(addr, &len, NULL, &immed_offset);
  268. if (b == NULL) {
  269. buf= (char*)malloc(30);
  270. strcpy(buf, "UNKNOWN/INVALID");
  271. return(buf);
  272. }
  273. while (*b)
  274. {
  275. if (*b == '%')
  276. {
  277. b++;
  278. switch (*(b++))
  279. {
  280. case 'd': // d jump relative target, signed? byte immediate operand
  281. sprintf(temp, "#%d", (char)get_mem(MEM_ROM_ID, addr+immed_offset));
  282. ++immed_offset;
  283. break;
  284. case 'w': // w word immediate operand
  285. sprintf(temp, "#0x%04x",
  286. (uint)((get_mem(MEM_ROM_ID, addr+immed_offset)) |
  287. (get_mem(MEM_ROM_ID, addr+immed_offset+1)<<8)) );
  288. ++immed_offset;
  289. ++immed_offset;
  290. break;
  291. case 'b': // b byte immediate operand
  292. sprintf(temp, "#0x%02x", (uint)get_mem(MEM_ROM_ID, addr+immed_offset));
  293. ++immed_offset;
  294. break;
  295. default:
  296. strcpy(temp, "?");
  297. break;
  298. }
  299. t= temp;
  300. while (*t)
  301. *(p++)= *(t++);
  302. }
  303. else
  304. *(p++)= *(b++);
  305. }
  306. *p= '\0';
  307. p= strchr(work, ' ');
  308. if (!p)
  309. {
  310. buf= strdup(work);
  311. return(buf);
  312. }
  313. if (sep == NULL)
  314. buf= (char *)malloc(6+strlen(p)+1);
  315. else
  316. buf= (char *)malloc((p-work)+strlen(sep)+strlen(p)+1);
  317. for (p= work, t= buf; *p != ' '; p++, t++)
  318. *t= *p;
  319. p++;
  320. *t= '\0';
  321. if (sep == NULL)
  322. {
  323. while (strlen(buf) < 6)
  324. strcat(buf, " ");
  325. }
  326. else
  327. strcat(buf, sep);
  328. strcat(buf, p);
  329. return(buf);
  330. }
  331. void
  332. cl_z80::print_regs(class cl_console_base *con)
  333. {
  334. con->dd_printf("SZ-A-PNC Flags= 0x%02x %3d %c ",
  335. regs.F, regs.F, isprint(regs.F)?regs.F:'.');
  336. con->dd_printf("A= 0x%02x %3d %c\n",
  337. regs.A, regs.A, isprint(regs.A)?regs.A:'.');
  338. con->dd_printf("%c%c-%c-%c%c%c\n",
  339. (regs.F&BIT_S)?'1':'0',
  340. (regs.F&BIT_Z)?'1':'0',
  341. (regs.F&BIT_A)?'1':'0',
  342. (regs.F&BIT_P)?'1':'0',
  343. (regs.F&BIT_N)?'1':'0',
  344. (regs.F&BIT_C)?'1':'0');
  345. con->dd_printf("BC= 0x%04x [BC]= %02x %3d %c ",
  346. regs.BC, ram->get(regs.BC), ram->get(regs.BC),
  347. isprint(ram->get(regs.BC))?ram->get(regs.BC):'.');
  348. con->dd_printf("DE= 0x%04x [DE]= %02x %3d %c ",
  349. regs.DE, ram->get(regs.DE), ram->get(regs.DE),
  350. isprint(ram->get(regs.DE))?ram->get(regs.DE):'.');
  351. con->dd_printf("HL= 0x%04x [HL]= %02x %3d %c\n",
  352. regs.HL, ram->get(regs.HL), ram->get(regs.HL),
  353. isprint(ram->get(regs.HL))?ram->get(regs.HL):'.');
  354. con->dd_printf("IX= 0x%04x [IX]= %02x %3d %c ",
  355. regs.IX, ram->get(regs.IX), ram->get(regs.IX),
  356. isprint(ram->get(regs.IX))?ram->get(regs.IX):'.');
  357. con->dd_printf("IY= 0x%04x [IY]= %02x %3d %c ",
  358. regs.IY, ram->get(regs.IY), ram->get(regs.IY),
  359. isprint(ram->get(regs.IY))?ram->get(regs.IY):'.');
  360. con->dd_printf("SP= 0x%04x [SP]= %02x %3d %c\n",
  361. regs.SP, ram->get(regs.SP), ram->get(regs.SP),
  362. isprint(ram->get(regs.SP))?ram->get(regs.SP):'.');
  363. print_disass(PC, con);
  364. }
  365. /*
  366. * Execution
  367. */
  368. int
  369. cl_z80::exec_inst(void)
  370. {
  371. t_mem code;
  372. if (fetch(&code))
  373. return(resBREAKPOINT);
  374. tick(1);
  375. switch (code)
  376. {
  377. case 0x00: return(inst_nop(code));
  378. case 0x01: case 0x02: case 0x06: return(inst_ld(code));
  379. case 0x03: case 0x04: return(inst_inc(code));
  380. case 0x05: return(inst_dec(code));
  381. case 0x07: return(inst_rlca(code));
  382. case 0x08: return(inst_ex(code));
  383. case 0x09: return(inst_add(code));
  384. case 0x0a: case 0x0e: return(inst_ld(code));
  385. case 0x0b: case 0x0d: return(inst_dec(code));
  386. case 0x0c: return(inst_inc(code));
  387. case 0x0f: return(inst_rrca(code));
  388. case 0x10: return(inst_djnz(code));
  389. case 0x11: case 0x12: case 0x16: return(inst_ld(code));
  390. case 0x13: case 0x14: return(inst_inc(code));
  391. case 0x15: return(inst_dec(code));
  392. case 0x17: return(inst_rla(code));
  393. case 0x18: return(inst_jr(code));
  394. case 0x19: return(inst_add(code));
  395. case 0x1a: case 0x1e: return(inst_ld(code));
  396. case 0x1b: case 0x1d: return(inst_dec(code));
  397. case 0x1c: return(inst_inc(code));
  398. case 0x1f: return(inst_rra(code));
  399. case 0x20: return(inst_jr(code));
  400. case 0x21: case 0x22: case 0x26: return(inst_ld(code));
  401. case 0x23: case 0x24: return(inst_inc(code));
  402. case 0x25: return(inst_dec(code));
  403. case 0x27: return(inst_daa(code));
  404. case 0x28: return(inst_jr(code));
  405. case 0x29: return(inst_add(code));
  406. case 0x2a: case 0x2e: return(inst_ld(code));
  407. case 0x2b: case 0x2d: return(inst_dec(code));
  408. case 0x2c: return(inst_inc(code));
  409. case 0x2f: return(inst_cpl(code));
  410. case 0x30: return(inst_jr(code));
  411. case 0x31: case 0x32: case 0x36: return(inst_ld(code));
  412. case 0x33: case 0x34: return(inst_inc(code));
  413. case 0x35: return(inst_dec(code));
  414. case 0x37: return(inst_scf(code));
  415. case 0x38: return(inst_jr(code));
  416. case 0x39: return(inst_add(code));
  417. case 0x3a: case 0x3e: return(inst_ld(code));
  418. case 0x3b: case 0x3d: return(inst_dec(code));
  419. case 0x3c: return(inst_inc(code));
  420. case 0x3f: return(inst_ccf(code));
  421. case 0x40: case 0x41: case 0x42: case 0x43: case 0x44: case 0x45: case 0x46: case 0x47:
  422. case 0x48: case 0x49: case 0x4a: case 0x4b: case 0x4c: case 0x4d: case 0x4e: case 0x4f:
  423. return(inst_ld(code));
  424. case 0x50: case 0x51: case 0x52: case 0x53: case 0x54: case 0x55: case 0x56: case 0x57:
  425. case 0x58: case 0x59: case 0x5a: case 0x5b: case 0x5c: case 0x5d: case 0x5e: case 0x5f:
  426. return(inst_ld(code));
  427. case 0x60: case 0x61: case 0x62: case 0x63: case 0x64: case 0x65: case 0x66: case 0x67:
  428. case 0x68: case 0x69: case 0x6a: case 0x6b: case 0x6c: case 0x6d: case 0x6e: case 0x6f:
  429. return(inst_ld(code));
  430. case 0x70: case 0x71: case 0x72: case 0x73: case 0x74: case 0x75: case 0x77:
  431. case 0x78: case 0x79: case 0x7a: case 0x7b: case 0x7c: case 0x7d: case 0x7e: case 0x7f:
  432. return(inst_ld(code));
  433. case 0x76:
  434. return(inst_halt(code));
  435. case 0x80: case 0x81: case 0x82: case 0x83: case 0x84: case 0x85: case 0x86: case 0x87:
  436. return(inst_add(code));
  437. case 0x88: case 0x89: case 0x8a: case 0x8b: case 0x8c: case 0x8d: case 0x8e: case 0x8f:
  438. return(inst_adc(code));
  439. case 0x90: case 0x91: case 0x92: case 0x93: case 0x94: case 0x95: case 0x96: case 0x97:
  440. return(inst_sub(code));
  441. case 0x98: case 0x99: case 0x9a: case 0x9b: case 0x9c: case 0x9d: case 0x9e: case 0x9f:
  442. return(inst_sbc(code));
  443. case 0xa0: case 0xa1: case 0xa2: case 0xa3: case 0xa4: case 0xa5: case 0xa6: case 0xa7:
  444. return(inst_and(code));
  445. case 0xa8: case 0xa9: case 0xaa: case 0xab: case 0xac: case 0xad: case 0xae: case 0xaf:
  446. return(inst_xor(code));
  447. case 0xb0: case 0xb1: case 0xb2: case 0xb3: case 0xb4: case 0xb5: case 0xb6: case 0xb7:
  448. return(inst_or(code));
  449. case 0xb8: case 0xb9: case 0xba: case 0xbb: case 0xbc: case 0xbd: case 0xbe: case 0xbf:
  450. return(inst_cp(code));
  451. case 0xc0: return(inst_ret(code));
  452. case 0xc1: return(inst_pop(code));
  453. case 0xc2: case 0xc3: return(inst_jp(code));
  454. case 0xc4: return(inst_call(code));
  455. case 0xc5: return(inst_push(code));
  456. case 0xc6: return(inst_add(code));
  457. case 0xc7: return(inst_rst(code));
  458. case 0xc8: case 0xc9: return(inst_ret(code));
  459. case 0xca: return(inst_jp(code));
  460. /* CB escapes out to 2 byte opcodes(CB include), opcodes
  461. to do register bit manipulations */
  462. case 0xcb: return(inst_cb());
  463. case 0xcc: case 0xcd: return(inst_call(code));
  464. case 0xce: return(inst_adc(code));
  465. case 0xcf: return(inst_rst(code));
  466. case 0xd0: return(inst_ret(code));
  467. case 0xd1: return(inst_pop(code));
  468. case 0xd2: return(inst_jp(code));
  469. case 0xd3: return(inst_out(code));
  470. case 0xd4: return(inst_call(code));
  471. case 0xd5: return(inst_push(code));
  472. case 0xd6: return(inst_sub(code));
  473. case 0xd7: return(inst_rst(code));
  474. case 0xd8: return(inst_ret(code));
  475. case 0xd9: return(inst_exx(code));
  476. case 0xda: return(inst_jp(code));
  477. case 0xdb: return(inst_in(code));
  478. case 0xdc: return(inst_call(code));
  479. /* DD escapes out to 2 to 4 byte opcodes(DD included)
  480. with a variety of uses. It can precede the CB escape
  481. sequence to extend CB codes with IX+immed_byte */
  482. case 0xdd: return(inst_dd());
  483. case 0xde: return(inst_sbc(code));
  484. case 0xdf: return(inst_rst(code));
  485. case 0xe0: return(inst_ret(code));
  486. case 0xe1: return(inst_pop(code));
  487. case 0xe2: return(inst_jp(code));
  488. case 0xe3: return(inst_ex(code));
  489. case 0xe4: return(inst_call(code));
  490. case 0xe5: return(inst_push(code));
  491. case 0xe6: return(inst_and(code));
  492. case 0xe7: return(inst_rst(code));
  493. case 0xe8: return(inst_ret(code));
  494. case 0xe9: return(inst_jp(code));
  495. case 0xea: return(inst_jp(code));
  496. case 0xeb: return(inst_ex(code));
  497. case 0xec: return(inst_call(code));
  498. /* ED escapes out to misc IN, OUT and other oddball opcodes */
  499. case 0xed: return(inst_ed());
  500. case 0xee: return(inst_xor(code));
  501. case 0xef: return(inst_rst(code));
  502. case 0xf0: return(inst_ret(code));
  503. case 0xf1: return(inst_pop(code));
  504. case 0xf2: return(inst_jp(code));
  505. case 0xf3: return(inst_di(code));
  506. case 0xf4: return(inst_call(code));
  507. case 0xf5: return(inst_push(code));
  508. case 0xf6: return(inst_or(code));
  509. case 0xf7: return(inst_rst(code));
  510. case 0xf8: return(inst_ret(code));
  511. case 0xf9: return(inst_ld(code));
  512. case 0xfa: return(inst_jp(code));
  513. case 0xfb: return(inst_ei(code));
  514. case 0xfc: return(inst_call(code));
  515. /* DD escapes out to 2 to 4 byte opcodes(DD included)
  516. with a variety of uses. It can precede the CB escape
  517. sequence to extend CB codes with IX+immed_byte */
  518. case 0xfd: return(inst_fd());
  519. case 0xfe: return(inst_cp(code));
  520. case 0xff: return(inst_rst(code));
  521. }
  522. /*if (PC)
  523. PC--;
  524. else
  525. PC= get_mem_size(MEM_ROM_ID)-1;*/
  526. PC= rom->inc_address(PC, -1);
  527. sim->stop(resINV_INST);
  528. return(resINV_INST);
  529. }
  530. void cl_z80::store1( TYPE_UWORD addr, t_mem val ) {
  531. ram->set(addr, val);
  532. }
  533. void cl_z80::store2( TYPE_UWORD addr, TYPE_UWORD val ) {
  534. ram->set(addr, val & 0xff);
  535. ram->set(addr+1, (val >> 8) & 0xff);
  536. }
  537. TYPE_UBYTE cl_z80::get1( TYPE_UWORD addr ) {
  538. return ram->get(addr);
  539. }
  540. TYPE_UWORD cl_z80::get2( TYPE_UWORD addr ) {
  541. TYPE_UWORD l, h;
  542. l = ram->get(addr );
  543. h = ram->get(addr+1);
  544. return (h << 8) | l;
  545. }
  546. t_mem cl_z80::fetch1( void ) {
  547. return fetch( );
  548. }
  549. TYPE_UWORD cl_z80::fetch2( void ) {
  550. TYPE_UWORD c1, c2;
  551. c1 = fetch( );
  552. c2 = fetch( );
  553. return (c2 << 8) | c1;
  554. }
  555. /* End of z80.src/z80.cc */