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/scsi.cpp

https://github.com/tonioni/WinUAE
C++ | 5735 lines | 4966 code | 661 blank | 108 comment | 1757 complexity | 926e04a3dba70969a5bd22aed068e453 MD5 | raw file

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  1. /*
  2. * UAE - The Un*x Amiga Emulator
  3. *
  4. * SCSI and SASI emulation (not uaescsi.device)
  5. *
  6. * Copyright 2007-2015 Toni Wilen
  7. *
  8. */
  9. #include "sysconfig.h"
  10. #include "sysdeps.h"
  11. #include "options.h"
  12. #include "filesys.h"
  13. #include "blkdev.h"
  14. #include "zfile.h"
  15. #include "debug.h"
  16. #include "memory.h"
  17. #include "scsi.h"
  18. #include "autoconf.h"
  19. #include "rommgr.h"
  20. #include "newcpu.h"
  21. #include "custom.h"
  22. #include "gayle.h"
  23. #include "cia.h"
  24. #include "devices.h"
  25. #include "flashrom.h"
  26. #include "gui.h"
  27. #define SCSI_EMU_DEBUG 0
  28. #define RAW_SCSI_DEBUG 0
  29. #define NCR5380_DEBUG 0
  30. #define NCR5380_DEBUG_IRQ 0
  31. #define NCR53400_DEBUG 0
  32. #define NCR5380_SUPRA 1
  33. #define NONCR_GOLEM 2
  34. #define NCR5380_STARDRIVE 3
  35. #define NONCR_KOMMOS 4
  36. #define NONCR_VECTOR 5
  37. #define NONCR_APOLLO 6
  38. #define NCR5380_PROTAR 7
  39. #define NCR5380_ADD500 8
  40. #define NCR5380_KRONOS 9
  41. #define NCR5380_ADSCSI 10
  42. #define NCR5380_ROCHARD 11
  43. #define NCR5380_CLTD 12
  44. #define NCR5380_PTNEXUS 13
  45. #define NCR5380_DATAFLYER 14
  46. #define NONCR_TECMAR 15
  47. #define NCR5380_XEBEC 16
  48. #define NONCR_MICROFORGE 17
  49. #define NONCR_PARADOX 18
  50. #define OMTI_HDA506 19
  51. #define OMTI_ALF1 20
  52. #define OMTI_PROMIGOS 21
  53. #define OMTI_SYSTEM2000 22
  54. #define OMTI_ADAPTER 23
  55. #define NCR5380_X86_RT1000 24
  56. #define NCR5380_PHOENIXBOARD 25
  57. #define NCR5380_TRUMPCARDPRO 26
  58. #define NCR5380_IVSVECTOR 27 // nearly identical to trumpcard pro
  59. #define NCR5380_SCRAM 28
  60. #define NCR5380_OSSI 29
  61. #define NCR5380_DATAFLYERPLUS 30
  62. #define NONCR_HARDFRAME 31
  63. #define NCR5380_MALIBU 32
  64. #define NCR5380_ADDHARD 33
  65. #define NONCR_INMATE 34
  66. #define NCR5380_EMPLANT 35
  67. #define OMTI_HD3000 36
  68. #define OMTI_WEDGE 37
  69. #define NCR5380_EVESHAMREF 38
  70. #define OMTI_PROFEX 39
  71. #define NCR5380_FASTTRAK 40
  72. #define NCR5380_12GAUGE 41
  73. #define NCR5380_OVERDRIVE 42
  74. #define NCR5380_TRUMPCARD 43
  75. #define OMTI_ALF2 44
  76. #define NCR5380_SYNTHESIS 45 // clone of ICD AdSCSI
  77. #define NCR5380_FIREBALL 46
  78. #define OMTI_HD20 47
  79. #define NCR_LAST 48
  80. extern int log_scsiemu;
  81. static const uae_s16 outcmd[] = { 0x04, 0x0a, 0x0c, 0x11, 0x2a, 0xaa, 0x15, 0x55, 0x0f, -1 };
  82. static const uae_s16 incmd[] = { 0x01, 0x03, 0x08, 0x0e, 0x12, 0x1a, 0x5a, 0x25, 0x28, 0x34, 0x37, 0x42, 0x43, 0xa8, 0x51, 0x52, 0xb9, 0xbd, 0xd8, 0xd9, 0xbe, -1 };
  83. static const uae_s16 nonecmd[] = { 0x00, 0x05, 0x06, 0x07, 0x09, 0x0b, 0x10, 0x16, 0x17, 0x19, 0x1b, 0x1d, 0x1e, 0x2b, 0x35, 0x45, 0x47, 0x48, 0x49, 0x4b, 0x4e, 0xa5, 0xa9, 0xba, 0xbc, 0xe0, 0xe3, 0xe4, -1 };
  84. static const uae_s16 safescsi[] = { 0x00, 0x01, 0x03, 0x08, 0x0e, 0x0f, 0x12, 0x1a, 0x1b, 0x25, 0x28, 0x35, 0x5a, -1 };
  85. static const uae_s16 scsicmdsizes[] = { 6, 10, 10, 12, 16, 12, 10, 6 };
  86. static void scsi_illegal_command(struct scsi_data *sd)
  87. {
  88. uae_u8 *s = sd->sense;
  89. memset (s, 0, sizeof (sd->sense));
  90. sd->status = SCSI_STATUS_CHECK_CONDITION;
  91. s[0] = 0x70;
  92. s[2] = 5; /* ILLEGAL REQUEST */
  93. s[12] = 0x24; /* ILLEGAL FIELD IN CDB */
  94. sd->sense_len = 0x12;
  95. }
  96. static void scsi_grow_buffer(struct scsi_data *sd, int newsize)
  97. {
  98. if (sd->buffer_size >= newsize)
  99. return;
  100. uae_u8 *oldbuf = sd->buffer;
  101. int oldsize = sd->buffer_size;
  102. sd->buffer_size = newsize + SCSI_DEFAULT_DATA_BUFFER_SIZE;
  103. write_log(_T("SCSI buffer %d -> %d\n"), oldsize, sd->buffer_size);
  104. sd->buffer = xmalloc(uae_u8, sd->buffer_size);
  105. memcpy(sd->buffer, oldbuf, oldsize);
  106. xfree(oldbuf);
  107. }
  108. static int scsi_data_dir(struct scsi_data *sd)
  109. {
  110. int i;
  111. uae_u8 cmd;
  112. cmd = sd->cmd[0];
  113. for (i = 0; outcmd[i] >= 0; i++) {
  114. if (cmd == outcmd[i]) {
  115. return 1;
  116. }
  117. }
  118. for (i = 0; incmd[i] >= 0; i++) {
  119. if (cmd == incmd[i]) {
  120. return -1;
  121. }
  122. }
  123. for (i = 0; nonecmd[i] >= 0; i++) {
  124. if (cmd == nonecmd[i]) {
  125. return 0;
  126. }
  127. }
  128. write_log (_T("SCSI command %02X, no direction specified!\n"), sd->cmd[0]);
  129. return 0;
  130. }
  131. bool scsi_emulate_analyze (struct scsi_data *sd)
  132. {
  133. int cmd_len, data_len, data_len2, tmp_len;
  134. data_len = sd->data_len;
  135. data_len2 = 0;
  136. cmd_len = scsicmdsizes[sd->cmd[0] >> 5];
  137. if (sd->hdhfd && sd->hdhfd->ansi_version < 2 && cmd_len > 10)
  138. goto nocmd;
  139. sd->cmd_len = cmd_len;
  140. switch (sd->cmd[0])
  141. {
  142. case 0x04: // FORMAT UNIT
  143. if (sd->device_type == UAEDEV_CD)
  144. goto nocmd;
  145. // FmtData set?
  146. if (sd->cmd[1] & 0x10) {
  147. int cl = (sd->cmd[1] & 8) != 0;
  148. int dlf = sd->cmd[1] & 7;
  149. data_len2 = 4;
  150. } else {
  151. sd->direction = 0;
  152. sd->data_len = 0;
  153. return true;
  154. }
  155. break;
  156. case 0x06: // FORMAT TRACK
  157. case 0x07: // FORMAT BAD TRACK
  158. if (sd->device_type == UAEDEV_CD)
  159. goto nocmd;
  160. sd->direction = 0;
  161. sd->data_len = 0;
  162. return true;
  163. case 0x0c: // INITIALIZE DRIVE CHARACTERICS (SASI)
  164. if (sd->hfd && sd->hfd->ci.unit_feature_level < HD_LEVEL_SASI)
  165. goto nocmd;
  166. data_len = 8;
  167. break;
  168. case 0x08: // READ(6)
  169. data_len2 = (sd->cmd[4] == 0 ? 256 : sd->cmd[4]) * sd->blocksize;
  170. scsi_grow_buffer(sd, data_len2);
  171. break;
  172. case 0x11: // ASSIGN ALTERNATE TRACK (SASI)
  173. if (sd->hfd && sd->hfd->ci.unit_feature_level < HD_LEVEL_SASI)
  174. goto nocmd;
  175. data_len = 4;
  176. break;
  177. case 0x28: // READ(10)
  178. data_len2 = ((sd->cmd[7] << 8) | (sd->cmd[8] << 0)) * (uae_s64)sd->blocksize;
  179. scsi_grow_buffer(sd, data_len2);
  180. break;
  181. case 0xa8: // READ(12)
  182. data_len2 = ((sd->cmd[6] << 24) | (sd->cmd[7] << 16) | (sd->cmd[8] << 8) | (sd->cmd[9] << 0)) * (uae_s64)sd->blocksize;
  183. scsi_grow_buffer(sd, data_len2);
  184. break;
  185. case 0x0f: // WRITE SECTOR BUFFER
  186. data_len = sd->blocksize;
  187. scsi_grow_buffer(sd, data_len);
  188. break;
  189. case 0x0a: // WRITE(6)
  190. if (sd->device_type == UAEDEV_CD)
  191. goto nocmd;
  192. data_len = (sd->cmd[4] == 0 ? 256 : sd->cmd[4]) * sd->blocksize;
  193. scsi_grow_buffer(sd, data_len);
  194. break;
  195. case 0x2a: // WRITE(10)
  196. if (sd->device_type == UAEDEV_CD)
  197. goto nocmd;
  198. data_len = ((sd->cmd[7] << 8) | (sd->cmd[8] << 0)) * (uae_s64)sd->blocksize;
  199. scsi_grow_buffer(sd, data_len);
  200. break;
  201. case 0xaa: // WRITE(12)
  202. if (sd->device_type == UAEDEV_CD)
  203. goto nocmd;
  204. data_len = ((sd->cmd[6] << 24) | (sd->cmd[7] << 16) | (sd->cmd[8] << 8) | (sd->cmd[9] << 0)) * (uae_s64)sd->blocksize;
  205. scsi_grow_buffer(sd, data_len);
  206. break;
  207. case 0xbe: // READ CD
  208. case 0xb9: // READ CD MSF
  209. case 0xd8: // READ CD-DA
  210. case 0xd9: // READ CD-DA MSF
  211. if (sd->device_type != UAEDEV_CD)
  212. goto nocmd;
  213. tmp_len = (sd->cmd[6] << 16) | (sd->cmd[7] << 8) | sd->cmd[8];
  214. // max block transfer size, it is usually smaller.
  215. tmp_len *= 2352 + 96;
  216. scsi_grow_buffer(sd, tmp_len);
  217. break;
  218. case 0x2f: // VERIFY
  219. if (sd->cmd[1] & 2) {
  220. sd->data_len = ((sd->cmd[7] << 8) | (sd->cmd[8] << 0)) * (uae_s64)sd->blocksize;
  221. scsi_grow_buffer(sd, sd->data_len);
  222. sd->direction = 1;
  223. } else {
  224. sd->data_len = 0;
  225. sd->direction = 0;
  226. }
  227. return true;
  228. }
  229. if (data_len < 0) {
  230. if (cmd_len == 6) {
  231. sd->data_len = sd->cmd[4];
  232. } else {
  233. sd->data_len = (sd->cmd[7] << 8) | sd->cmd[8];
  234. }
  235. } else {
  236. sd->data_len = data_len;
  237. }
  238. sd->direction = scsi_data_dir(sd);
  239. if (sd->direction > 0 && sd->data_len == 0) {
  240. sd->direction = 0;
  241. }
  242. return true;
  243. nocmd:
  244. sd->status = SCSI_STATUS_CHECK_CONDITION;
  245. sd->direction = 0;
  246. scsi_illegal_command(sd);
  247. return false;
  248. }
  249. void scsi_illegal_lun(struct scsi_data *sd)
  250. {
  251. uae_u8 *s = sd->sense;
  252. memset (s, 0, sizeof (sd->sense));
  253. sd->status = SCSI_STATUS_CHECK_CONDITION;
  254. s[0] = 0x70;
  255. s[2] = SCSI_SK_ILLEGAL_REQ;
  256. s[12] = SCSI_INVALID_LUN;
  257. sd->sense_len = 0x12;
  258. }
  259. void scsi_clear_sense(struct scsi_data *sd)
  260. {
  261. memset (sd->sense, 0, sizeof (sd->sense));
  262. memset (sd->reply, 0, sizeof (sd->reply));
  263. sd->sense[0] = 0x70;
  264. }
  265. static void showsense(struct scsi_data *sd)
  266. {
  267. if (log_scsiemu) {
  268. for (int i = 0; i < sd->sense_len; i++) {
  269. if (i > 0)
  270. write_log (_T("."));
  271. write_log (_T("%02X"), sd->buffer[i]);
  272. }
  273. write_log (_T("\n"));
  274. }
  275. }
  276. static void copysense(struct scsi_data *sd)
  277. {
  278. bool sasi = sd->hfd && (sd->hfd->ci.unit_feature_level >= HD_LEVEL_SASI && sd->hfd->ci.unit_feature_level <= HD_LEVEL_SASI_ENHANCED);
  279. int len = sd->cmd[4];
  280. if (len == 0 || sasi)
  281. len = 4;
  282. memset(sd->buffer, 0, len);
  283. int tlen = sd->sense_len > len ? len : sd->sense_len;
  284. memcpy(sd->buffer, sd->sense, tlen);
  285. if (!sasi && sd->sense_len == 0) {
  286. // at least 0x12 bytes if SCSI and no sense
  287. tlen = len > 0x12 ? 0x12 : len;
  288. sd->buffer[0] = 0x70;
  289. sd->sense_len = tlen;
  290. }
  291. if (log_scsiemu)
  292. write_log(_T("REQUEST SENSE %d (%d -> %d)\n"), sd->cmd[4], sd->sense_len, tlen);
  293. showsense (sd);
  294. sd->data_len = tlen;
  295. scsi_clear_sense(sd);
  296. }
  297. static void copyreply(struct scsi_data *sd)
  298. {
  299. if (sd->status == 0 && sd->reply_len > 0) {
  300. memset(sd->buffer, 0, 256);
  301. memcpy(sd->buffer, sd->reply, sd->reply_len);
  302. sd->data_len = sd->reply_len;
  303. }
  304. }
  305. static void scsi_set_unit_attention(struct scsi_data *sd, uae_u8 v1, uae_u8 v2)
  306. {
  307. sd->unit_attention = (v1 << 8) | v2;
  308. }
  309. static void scsi_emulate_reset_device(struct scsi_data *sd)
  310. {
  311. if (!sd)
  312. return;
  313. if (sd->device_type == UAEDEV_HDF && sd->nativescsiunit < 0) {
  314. scsi_clear_sense(sd);
  315. // SCSI bus reset occurred
  316. scsi_set_unit_attention(sd, 0x29, 0x02);
  317. }
  318. }
  319. static bool handle_ca(struct scsi_data *sd)
  320. {
  321. bool cc = sd->sense_len > 2 && sd->sense[2] >= 2;
  322. bool ua = sd->unit_attention != 0;
  323. uae_u8 cmd = sd->cmd[0];
  324. // INQUIRY
  325. if (cmd == 0x12) {
  326. if (ua && cc && sd->sense[2] == 6) {
  327. // INQUIRY clears UA only if previous
  328. // command was aborted due to UA
  329. sd->unit_attention = 0;
  330. }
  331. memset(sd->reply, 0, sizeof(sd->reply));
  332. return true;
  333. }
  334. // REQUEST SENSE
  335. if (cmd == 0x03) {
  336. if (ua) {
  337. uae_u8 *s = sd->sense;
  338. scsi_clear_sense(sd);
  339. s[0] = 0x70;
  340. s[2] = 6; /* UNIT ATTENTION */
  341. s[12] = (sd->unit_attention >> 8) & 0xff;
  342. s[13] = (sd->unit_attention >> 0) & 0xff;
  343. sd->sense_len = 0x12;
  344. }
  345. sd->unit_attention = 0;
  346. return true;
  347. }
  348. scsi_clear_sense(sd);
  349. if (ua) {
  350. uae_u8 *s = sd->sense;
  351. s[0] = 0x70;
  352. s[2] = 6; /* UNIT ATTENTION */
  353. s[12] = (sd->unit_attention >> 8) & 0xff;
  354. s[13] = (sd->unit_attention >> 0) & 0xff;
  355. sd->sense_len = 0x12;
  356. sd->unit_attention = 0;
  357. sd->status = 2;
  358. return false;
  359. }
  360. return true;
  361. }
  362. bool scsi_cmd_is_safe(uae_u8 cmd)
  363. {
  364. for (int i = 0; safescsi[i] >= 0; i++) {
  365. if (safescsi[i] == cmd) {
  366. return true;
  367. }
  368. }
  369. return false;
  370. }
  371. void scsi_emulate_cmd(struct scsi_data *sd)
  372. {
  373. sd->status = 0;
  374. if ((sd->message[0] & 0xc0) == 0x80 && (sd->message[0] & 0x1f)) {
  375. uae_u8 lun = sd->message[0] & 0x1f;
  376. if (lun > 7)
  377. lun = 7;
  378. sd->cmd[1] &= ~(7 << 5);
  379. sd->cmd[1] |= lun << 5;
  380. }
  381. #if SCSI_EMU_DEBUG
  382. write_log (_T("CMD=%02x.%02x.%02x.%02x.%02x.%02x.%02x.%02x.%02x.%02x (%d,%d)\n"),
  383. sd->cmd[0], sd->cmd[1], sd->cmd[2], sd->cmd[3], sd->cmd[4], sd->cmd[5], sd->cmd[6], sd->cmd[7], sd->cmd[8], sd->cmd[9],
  384. sd->device_type, sd->nativescsiunit);
  385. #endif
  386. if (sd->device_type == UAEDEV_CD && sd->cd_emu_unit >= 0) {
  387. uae_u32 ua = 0;
  388. ua = scsi_cd_emulate(sd->cd_emu_unit, NULL, 0, 0, 0, 0, 0, 0, 0, sd->atapi);
  389. if (ua)
  390. sd->unit_attention = ua;
  391. if (handle_ca(sd)) {
  392. if (sd->cmd[0] == 0x03) { /* REQUEST SENSE */
  393. scsi_cd_emulate(sd->cd_emu_unit, sd->cmd, 0, 0, 0, 0, 0, 0, 0, sd->atapi); /* ack request sense */
  394. copysense(sd);
  395. } else {
  396. sd->status = scsi_cd_emulate(sd->cd_emu_unit, sd->cmd, sd->cmd_len, sd->buffer, &sd->data_len, sd->reply, &sd->reply_len, sd->sense, &sd->sense_len, sd->atapi);
  397. copyreply(sd);
  398. }
  399. }
  400. gui_flicker_led(LED_CD, sd->uae_unitnum, 1);
  401. } else if (sd->device_type == UAEDEV_HDF && sd->nativescsiunit < 0) {
  402. uae_u32 ua = 0;
  403. ua = scsi_hd_emulate(sd->hfd, sd->hdhfd, NULL, 0, 0, 0, 0, 0, 0, 0);
  404. if (ua)
  405. sd->unit_attention = ua;
  406. if (handle_ca(sd)) {
  407. if (sd->cmd[0] == 0x03) { /* REQUEST SENSE */
  408. scsi_hd_emulate(sd->hfd, sd->hdhfd, sd->cmd, 0, 0, 0, 0, 0, sd->sense, &sd->sense_len);
  409. copysense(sd);
  410. } else {
  411. sd->status = scsi_hd_emulate(sd->hfd, sd->hdhfd,
  412. sd->cmd, sd->cmd_len, sd->buffer, &sd->data_len, sd->reply, &sd->reply_len, sd->sense, &sd->sense_len);
  413. copyreply(sd);
  414. }
  415. }
  416. } else if (sd->device_type == UAEDEV_TAPE && sd->nativescsiunit < 0) {
  417. uae_u32 ua = 0;
  418. ua = scsi_tape_emulate(sd->tape, NULL, 0, 0, 0, 0, 0, 0, 0);
  419. if (ua)
  420. sd->unit_attention = ua;
  421. if (handle_ca(sd)) {
  422. if (sd->cmd[0] == 0x03) { /* REQUEST SENSE */
  423. scsi_tape_emulate(sd->tape, sd->cmd, 0, 0, 0, sd->reply, &sd->reply_len, sd->sense, &sd->sense_len); /* get request sense extra bits */
  424. copysense(sd);
  425. } else {
  426. sd->status = scsi_tape_emulate(sd->tape,
  427. sd->cmd, sd->cmd_len, sd->buffer, &sd->data_len, sd->reply, &sd->reply_len, sd->sense, &sd->sense_len);
  428. copyreply(sd);
  429. }
  430. }
  431. } else if (sd->device_type == UAEDEV_DIR) {
  432. uae_u32 ua = 0;
  433. ua = scsi_hd_emulate(sd->hfd, sd->hdhfd, NULL, 0, 0, 0, 0, 0, 0, 0);
  434. if (ua)
  435. sd->unit_attention = ua;
  436. if (handle_ca(sd)) {
  437. if (scsi_cmd_is_safe(sd->cmd[0])) {
  438. if (sd->cmd[0] == 0x03) { /* REQUEST SENSE */
  439. scsi_hd_emulate(sd->hfd, sd->hdhfd, sd->cmd, 0, 0, 0, 0, 0, sd->sense, &sd->sense_len);
  440. copysense(sd);
  441. } else {
  442. sd->status = scsi_hd_emulate(sd->hfd, sd->hdhfd,
  443. sd->cmd, sd->cmd_len, sd->buffer, &sd->data_len, sd->reply, &sd->reply_len, sd->sense, &sd->sense_len);
  444. copyreply(sd);
  445. }
  446. } else {
  447. sd->sense[0] = 0x70;
  448. sd->sense[2] = 5; /* Illegal Request */
  449. sd->sense[12] = 0x20; /* Invalid/unsupported command code */
  450. sd->sense_len = 18;
  451. sd->status = 2;
  452. copyreply(sd);
  453. }
  454. }
  455. } else if (sd->nativescsiunit >= 0) {
  456. struct amigascsi as;
  457. memset(sd->sense, 0, 256);
  458. memset(&as, 0, sizeof as);
  459. memcpy (&as.cmd, sd->cmd, sd->cmd_len);
  460. as.flags = 2 | 1;
  461. if (sd->direction > 0)
  462. as.flags &= ~1;
  463. as.sense_len = 32;
  464. as.cmd_len = sd->cmd_len;
  465. as.data = sd->buffer;
  466. as.len = sd->direction < 0 ? DEVICE_SCSI_BUFSIZE : sd->data_len;
  467. sys_command_scsi_direct_native(sd->nativescsiunit, -1, &as);
  468. sd->status = as.status;
  469. sd->data_len = as.len;
  470. if (sd->status) {
  471. sd->direction = 0;
  472. sd->data_len = 0;
  473. memcpy(sd->sense, as.sensedata, as.sense_len);
  474. }
  475. }
  476. sd->offset = 0;
  477. }
  478. static void allocscsibuf(struct scsi_data *sd)
  479. {
  480. sd->buffer_size = SCSI_DEFAULT_DATA_BUFFER_SIZE;
  481. sd->buffer = xcalloc(uae_u8, sd->buffer_size);
  482. }
  483. struct scsi_data *scsi_alloc_generic(struct hardfiledata *hfd, int type, int uae_unitnum)
  484. {
  485. struct scsi_data *sd = xcalloc(struct scsi_data, 1);
  486. sd->hfd = hfd;
  487. sd->id = -1;
  488. sd->nativescsiunit = -1;
  489. sd->cd_emu_unit = -1;
  490. sd->blocksize = hfd->ci.blocksize;
  491. sd->device_type = type;
  492. sd->uae_unitnum = uae_unitnum;
  493. allocscsibuf(sd);
  494. return sd;
  495. }
  496. struct scsi_data *scsi_alloc_hd(int id, struct hd_hardfiledata *hfd, int uae_unitnum)
  497. {
  498. struct scsi_data *sd = xcalloc (struct scsi_data, 1);
  499. sd->hdhfd = hfd;
  500. sd->hfd = &hfd->hfd;
  501. sd->id = id;
  502. sd->nativescsiunit = -1;
  503. sd->cd_emu_unit = -1;
  504. sd->blocksize = hfd->hfd.virtual_rdb ? 512 : hfd->hfd.ci.blocksize;
  505. sd->device_type = UAEDEV_HDF;
  506. sd->uae_unitnum = uae_unitnum;
  507. allocscsibuf(sd);
  508. return sd;
  509. }
  510. struct scsi_data *scsi_alloc_cd(int id, int unitnum, bool atapi, int uae_unitnum)
  511. {
  512. struct scsi_data *sd;
  513. if (!sys_command_open (unitnum)) {
  514. write_log (_T("SCSI: CD EMU scsi unit %d failed to open\n"), unitnum);
  515. return NULL;
  516. }
  517. sd = xcalloc (struct scsi_data, 1);
  518. sd->id = id;
  519. sd->cd_emu_unit = unitnum;
  520. sd->nativescsiunit = -1;
  521. sd->atapi = atapi;
  522. sd->blocksize = 2048;
  523. sd->device_type = UAEDEV_CD;
  524. sd->uae_unitnum = uae_unitnum;
  525. allocscsibuf(sd);
  526. return sd;
  527. }
  528. struct scsi_data *scsi_alloc_tape(int id, const TCHAR *tape_directory, bool readonly, int uae_unitnum)
  529. {
  530. struct scsi_data_tape *tape;
  531. tape = tape_alloc (id, tape_directory, readonly);
  532. if (!tape)
  533. return NULL;
  534. struct scsi_data *sd = xcalloc (struct scsi_data, 1);
  535. sd->id = id;
  536. sd->nativescsiunit = -1;
  537. sd->cd_emu_unit = -1;
  538. sd->blocksize = tape->blocksize;
  539. sd->tape = tape;
  540. sd->device_type = UAEDEV_TAPE;
  541. sd->uae_unitnum = uae_unitnum;
  542. allocscsibuf(sd);
  543. return sd;
  544. }
  545. struct scsi_data *scsi_alloc_native(int id, int nativeunit)
  546. {
  547. struct scsi_data *sd;
  548. if (!sys_command_open (nativeunit)) {
  549. write_log (_T("SCSI: native scsi unit %d failed to open\n"), nativeunit);
  550. return NULL;
  551. }
  552. sd = xcalloc (struct scsi_data, 1);
  553. sd->id = id;
  554. sd->nativescsiunit = nativeunit;
  555. sd->cd_emu_unit = -1;
  556. sd->blocksize = 2048;
  557. sd->device_type = 0;
  558. allocscsibuf(sd);
  559. return sd;
  560. }
  561. void scsi_reset(void)
  562. {
  563. //device_func_init (DEVICE_TYPE_SCSI);
  564. }
  565. void scsi_free(struct scsi_data *sd)
  566. {
  567. if (!sd)
  568. return;
  569. if (sd->nativescsiunit >= 0) {
  570. sys_command_close (sd->nativescsiunit);
  571. sd->nativescsiunit = -1;
  572. }
  573. if (sd->cd_emu_unit >= 0) {
  574. sys_command_close (sd->cd_emu_unit);
  575. sd->cd_emu_unit = -1;
  576. }
  577. tape_free (sd->tape);
  578. xfree(sd->buffer);
  579. xfree(sd);
  580. }
  581. void scsi_start_transfer(struct scsi_data *sd)
  582. {
  583. sd->offset = 0;
  584. }
  585. int scsi_send_data(struct scsi_data *sd, uae_u8 b)
  586. {
  587. if (sd->offset < 0) {
  588. write_log(_T("SCSI data offset is negative!\n"));
  589. return 0;
  590. }
  591. if (sd->direction == 1) {
  592. if (sd->offset >= sd->buffer_size) {
  593. write_log (_T("SCSI data buffer overflow!\n"));
  594. return 0;
  595. }
  596. sd->buffer[sd->offset++] = b;
  597. } else if (sd->direction == 2) {
  598. if (sd->offset >= 16) {
  599. write_log (_T("SCSI command buffer overflow!\n"));
  600. return 0;
  601. }
  602. sd->cmd[sd->offset++] = b;
  603. if (sd->offset == sd->cmd_len)
  604. return 1;
  605. } else {
  606. write_log (_T("scsi_send_data() without direction! (%02X)\n"), sd->cmd[0]);
  607. return 0;
  608. }
  609. if (sd->offset == sd->data_len)
  610. return 1;
  611. return 0;
  612. }
  613. int scsi_receive_data(struct scsi_data *sd, uae_u8 *b, bool next)
  614. {
  615. if (!sd->data_len)
  616. return -1;
  617. *b = sd->buffer[sd->offset];
  618. if (next) {
  619. sd->offset++;
  620. if (sd->offset == sd->data_len)
  621. return 1; // requested length got
  622. }
  623. return 0;
  624. }
  625. void free_scsi (struct scsi_data *sd)
  626. {
  627. if (!sd)
  628. return;
  629. hdf_hd_close(sd->hdhfd);
  630. scsi_free (sd);
  631. }
  632. int add_scsi_hd (struct scsi_data **sd, int ch, struct hd_hardfiledata *hfd, struct uaedev_config_info *ci)
  633. {
  634. free_scsi (*sd);
  635. *sd = NULL;
  636. if (!hfd) {
  637. hfd = xcalloc (struct hd_hardfiledata, 1);
  638. memcpy (&hfd->hfd.ci, ci, sizeof (struct uaedev_config_info));
  639. }
  640. if (!hdf_hd_open (hfd))
  641. return 0;
  642. hfd->ansi_version = ci->unit_feature_level + 1;
  643. *sd = scsi_alloc_hd (ch, hfd, ci->uae_unitnum);
  644. return *sd ? 1 : 0;
  645. }
  646. int add_scsi_cd (struct scsi_data **sd, int ch, int unitnum)
  647. {
  648. device_func_init (0);
  649. free_scsi (*sd);
  650. *sd = scsi_alloc_cd (ch, unitnum, false, unitnum);
  651. return *sd ? 1 : 0;
  652. }
  653. int add_scsi_tape (struct scsi_data **sd, int ch, const TCHAR *tape_directory, bool readonly)
  654. {
  655. free_scsi (*sd);
  656. *sd = scsi_alloc_tape (ch, tape_directory, readonly, ch);
  657. return *sd ? 1 : 0;
  658. }
  659. int add_scsi_device(struct scsi_data **sd, int ch, struct uaedev_config_info *ci, struct romconfig *rc)
  660. {
  661. if (ci->type == UAEDEV_CD)
  662. return add_scsi_cd(sd, ch, ci->device_emu_unit);
  663. else if (ci->type == UAEDEV_TAPE)
  664. return add_scsi_tape(sd, ch, ci->rootdir, ci->readonly);
  665. else if (ci->type == UAEDEV_HDF)
  666. return add_scsi_hd(sd, ch, NULL, ci);
  667. return 0;
  668. }
  669. void scsi_freenative(struct scsi_data **sd, int max)
  670. {
  671. for (int i = 0; i < max; i++) {
  672. free_scsi (sd[i]);
  673. sd[i] = NULL;
  674. }
  675. }
  676. void scsi_addnative(struct scsi_data **sd)
  677. {
  678. int i, j;
  679. int devices[MAX_TOTAL_SCSI_DEVICES];
  680. int types[MAX_TOTAL_SCSI_DEVICES];
  681. struct device_info dis[MAX_TOTAL_SCSI_DEVICES];
  682. scsi_freenative (sd, MAX_TOTAL_SCSI_DEVICES);
  683. i = 0;
  684. while (i < MAX_TOTAL_SCSI_DEVICES) {
  685. types[i] = -1;
  686. devices[i] = -1;
  687. if (sys_command_open (i)) {
  688. if (sys_command_info (i, &dis[i], 0)) {
  689. devices[i] = i;
  690. types[i] = 100 - i;
  691. if (dis[i].type == INQ_ROMD)
  692. types[i] = 1000 - i;
  693. }
  694. sys_command_close (i);
  695. }
  696. i++;
  697. }
  698. i = 0;
  699. while (devices[i] >= 0) {
  700. j = i + 1;
  701. while (devices[j] >= 0) {
  702. if (types[i] > types[j]) {
  703. int tmp = types[i];
  704. types[i] = types[j];
  705. types[j] = tmp;
  706. }
  707. j++;
  708. }
  709. i++;
  710. }
  711. i = 0; j = 0;
  712. while (devices[i] >= 0 && j < 7) {
  713. if (sd[j] == NULL) {
  714. sd[j] = scsi_alloc_native(j, devices[i]);
  715. write_log (_T("SCSI: %d:'%s'\n"), j, dis[i].label);
  716. i++;
  717. }
  718. j++;
  719. }
  720. }
  721. // raw scsi
  722. #define SCSI_IO_BUSY 0x80
  723. #define SCSI_IO_ATN 0x40
  724. #define SCSI_IO_SEL 0x20
  725. #define SCSI_IO_REQ 0x10
  726. #define SCSI_IO_DIRECTION 0x01
  727. #define SCSI_IO_COMMAND 0x02
  728. #define SCSI_IO_MESSAGE 0x04
  729. #define SCSI_SIGNAL_PHASE_FREE -1
  730. #define SCSI_SIGNAL_PHASE_ARBIT -2
  731. #define SCSI_SIGNAL_PHASE_SELECT_1 -3
  732. #define SCSI_SIGNAL_PHASE_SELECT_2 -4
  733. #define SCSI_SIGNAL_PHASE_DATA_OUT 0
  734. #define SCSI_SIGNAL_PHASE_DATA_IN 1
  735. #define SCSI_SIGNAL_PHASE_COMMAND 2
  736. #define SCSI_SIGNAL_PHASE_STATUS 3
  737. #define SCSI_SIGNAL_PHASE_MESSAGE_OUT 6
  738. #define SCSI_SIGNAL_PHASE_MESSAGE_IN 7
  739. struct raw_scsi
  740. {
  741. int io;
  742. int bus_phase;
  743. bool atn;
  744. bool ack;
  745. bool wait_ack;
  746. uae_u8 data_write;
  747. uae_u8 status;
  748. bool databusoutput;
  749. int initiator_id, target_id;
  750. struct scsi_data *device[MAX_TOTAL_SCSI_DEVICES];
  751. struct scsi_data *target;
  752. int msglun;
  753. };
  754. struct soft_scsi
  755. {
  756. uae_u8 regs[32];
  757. uae_u16 regs_400[2];
  758. uae_u8 scratch_400[64];
  759. int c400_count;
  760. bool c400;
  761. bool dp8490v;
  762. uae_u8 aic_reg;
  763. struct raw_scsi rscsi;
  764. bool irq;
  765. bool intena;
  766. bool level6;
  767. bool enabled;
  768. bool delayed_irq;
  769. bool configured;
  770. uae_u8 acmemory[128];
  771. uaecptr baseaddress;
  772. uaecptr baseaddress2;
  773. uae_u8 *rom;
  774. int rom_size;
  775. int board_mask;
  776. int board_mask2;
  777. int board_size;
  778. addrbank *bank;
  779. int type;
  780. int subtype;
  781. int dma_direction;
  782. bool dma_active;
  783. bool dma_started;
  784. bool dma_controller;
  785. bool dma_drq;
  786. bool dma_autodack;
  787. uae_u32 dma_mask;
  788. struct romconfig *rc;
  789. struct soft_scsi **self_ptr;
  790. int dmac_direction;
  791. uaecptr dmac_address;
  792. int dmac_length;
  793. int dmac_active;
  794. int chip_state;
  795. // add500
  796. uae_u16 databuffer[2];
  797. bool databuffer_empty;
  798. // kronos/xebec
  799. uae_u8 *databufferptr;
  800. int databuffer_size;
  801. int db_read_index;
  802. int db_write_index;
  803. void *eeprom;
  804. // sasi
  805. bool active_select;
  806. bool wait_select;
  807. // 12 Gauge needs this (Driver has buggy BSY test)
  808. bool busy_delayed_hack;
  809. int busy_delayed_hack_cnt;
  810. };
  811. #define MAX_SOFT_SCSI_UNITS 10
  812. static struct soft_scsi *soft_scsi_devices[MAX_SOFT_SCSI_UNITS];
  813. static struct soft_scsi *soft_scsi_units[NCR_LAST * MAX_DUPLICATE_EXPANSION_BOARDS];
  814. bool parallel_port_scsi;
  815. static struct soft_scsi *parallel_port_scsi_data;
  816. static struct soft_scsi *x86_hd_data;
  817. static void soft_scsi_free_unit(struct soft_scsi *s)
  818. {
  819. if (!s)
  820. return;
  821. struct raw_scsi *rs = &s->rscsi;
  822. for (int j = 0; j < 8; j++) {
  823. free_scsi (rs->device[j]);
  824. rs->device[j] = NULL;
  825. }
  826. eeprom93xx_free(s->eeprom);
  827. xfree(s->databufferptr);
  828. xfree(s->rom);
  829. if (s->self_ptr)
  830. *s->self_ptr = NULL;
  831. xfree(s);
  832. }
  833. static void freescsi(struct soft_scsi **ncr)
  834. {
  835. if (!ncr)
  836. return;
  837. for (int i = 0; i < MAX_SOFT_SCSI_UNITS; i++) {
  838. if (soft_scsi_devices[i] == *ncr) {
  839. soft_scsi_devices[i] = NULL;
  840. }
  841. }
  842. if (*ncr) {
  843. soft_scsi_free_unit(*ncr);
  844. }
  845. *ncr = NULL;
  846. }
  847. static struct soft_scsi *allocscsi(struct soft_scsi **ncr, struct romconfig *rc, int ch)
  848. {
  849. struct soft_scsi *scsi;
  850. if (ch < 0) {
  851. freescsi(ncr);
  852. *ncr = NULL;
  853. }
  854. if ((*ncr) == NULL) {
  855. scsi = xcalloc(struct soft_scsi, 1);
  856. for (int i = 0; i < MAX_SOFT_SCSI_UNITS; i++) {
  857. if (soft_scsi_devices[i] == NULL) {
  858. soft_scsi_devices[i] = scsi;
  859. rc->unitdata = scsi;
  860. scsi->rc = rc;
  861. scsi->self_ptr = ncr;
  862. if (ncr)
  863. *ncr = scsi;
  864. return scsi;
  865. }
  866. }
  867. }
  868. return *ncr;
  869. }
  870. static struct soft_scsi *getscsiboard(uaecptr addr)
  871. {
  872. for (int i = 0; soft_scsi_devices[i]; i++) {
  873. struct soft_scsi *s = soft_scsi_devices[i];
  874. if (s->baseaddress2 && (addr & ~s->board_mask2) == s->baseaddress2)
  875. return s;
  876. if (!s->baseaddress && !s->configured)
  877. return s;
  878. if ((addr & ~s->board_mask) == s->baseaddress)
  879. return s;
  880. if (s->baseaddress == AUTOCONFIG_Z2 && addr < 65536)
  881. return s;
  882. }
  883. return NULL;
  884. }
  885. static void raw_scsi_reset(struct raw_scsi *rs)
  886. {
  887. rs->target = NULL;
  888. rs->io = 0;
  889. rs->bus_phase = SCSI_SIGNAL_PHASE_FREE;
  890. }
  891. extern addrbank soft_bank_generic;
  892. static void ew(struct soft_scsi *scsi, int addr, uae_u32 value)
  893. {
  894. addr &= 0xffff;
  895. if (addr == 00 || addr == 02 || addr == 0x40 || addr == 0x42) {
  896. scsi->acmemory[addr] = (value & 0xf0);
  897. scsi->acmemory[addr + 2] = (value & 0x0f) << 4;
  898. } else {
  899. scsi->acmemory[addr] = ~(value & 0xf0);
  900. scsi->acmemory[addr + 2] = ~((value & 0x0f) << 4);
  901. }
  902. }
  903. static struct soft_scsi *generic_soft_scsi_add(int ch, struct uaedev_config_info *ci, struct romconfig *rc, int type, int boardsize, int romsize, int romtype)
  904. {
  905. struct soft_scsi *ss = allocscsi(&soft_scsi_units[type * MAX_DUPLICATE_EXPANSION_BOARDS + ci->controller_type_unit], rc, ch);
  906. ss->type = type;
  907. ss->configured = 0;
  908. ss->bank = &soft_bank_generic;
  909. ss->subtype = rc->subtype;
  910. ss->intena = false;
  911. ss->dma_mask = 0xffffffff;
  912. if (boardsize > 0) {
  913. ss->board_size = boardsize;
  914. ss->board_mask = ss->board_size - 1;
  915. }
  916. if (!ss->board_mask && !ss->board_size) {
  917. ss->board_size = 0x10000;
  918. ss->board_mask = 0xffff;
  919. }
  920. ss->board_mask2 = ss->board_mask;
  921. if (romsize >= 0) {
  922. ss->rom_size = romsize;
  923. xfree(ss->rom);
  924. ss->rom = NULL;
  925. if (romsize > 0) {
  926. ss->rom = xcalloc(uae_u8, ss->rom_size);
  927. memset(ss->rom, 0xff, ss->rom_size);
  928. }
  929. }
  930. memset(ss->acmemory, 0xff, sizeof ss->acmemory);
  931. const struct expansionromtype *ert = get_device_expansion_rom(romtype);
  932. if (ert) {
  933. const uae_u8 *ac = NULL;
  934. if (ert->subtypes)
  935. ac = ert->subtypes[rc->subtype].autoconfig;
  936. else
  937. ac = ert->autoconfig;
  938. if (ac[0]) {
  939. for (int i = 0; i < 16; i++) {
  940. uae_u8 b = ac[i];
  941. ew(ss, i * 4, b);
  942. }
  943. }
  944. }
  945. raw_scsi_reset(&ss->rscsi);
  946. if (ch < 0)
  947. return ss;
  948. add_scsi_device(&ss->rscsi.device[ch], ch, ci, rc);
  949. return ss;
  950. }
  951. static void raw_scsi_busfree(struct raw_scsi *rs)
  952. {
  953. rs->target = NULL;
  954. rs->io = 0;
  955. rs->bus_phase = SCSI_SIGNAL_PHASE_FREE;
  956. }
  957. static void bus_free(struct raw_scsi *rs)
  958. {
  959. rs->bus_phase = SCSI_SIGNAL_PHASE_FREE;
  960. rs->io = 0;
  961. }
  962. static int getbit(uae_u8 v)
  963. {
  964. for (int i = 7; i >= 0; i--) {
  965. if ((1 << i) & v)
  966. return i;
  967. }
  968. return -1;
  969. }
  970. static int countbits(uae_u8 v)
  971. {
  972. int cnt = 0;
  973. for (int i = 7; i >= 0; i--) {
  974. if ((1 << i) & v)
  975. cnt++;
  976. }
  977. return cnt;
  978. }
  979. static void raw_scsi_reset_bus(struct soft_scsi *scsi)
  980. {
  981. struct raw_scsi *r = &scsi->rscsi;
  982. #if RAW_SCSI_DEBUG
  983. write_log(_T("SCSI BUS reset\n"));
  984. #endif
  985. raw_scsi_reset(r);
  986. for (int i = 0; i < 8; i++) {
  987. scsi_emulate_reset_device(r->device[i]);
  988. }
  989. }
  990. static void raw_scsi_set_databus(struct raw_scsi *rs, bool databusoutput)
  991. {
  992. rs->databusoutput = databusoutput;
  993. }
  994. static void raw_scsi_set_signal_phase(struct raw_scsi *rs, bool busy, bool select, bool atn)
  995. {
  996. switch (rs->bus_phase)
  997. {
  998. case SCSI_SIGNAL_PHASE_FREE:
  999. if (busy && !select && !rs->databusoutput) {
  1000. if (countbits(rs->data_write) != 1) {
  1001. #if RAW_SCSI_DEBUG
  1002. write_log(_T("raw_scsi: invalid arbitration scsi id mask! (%02x) %08x\n"), rs->data_write, M68K_GETPC);
  1003. #endif
  1004. return;
  1005. }
  1006. rs->bus_phase = SCSI_SIGNAL_PHASE_ARBIT;
  1007. rs->initiator_id = getbit(rs->data_write);
  1008. #if RAW_SCSI_DEBUG
  1009. write_log(_T("raw_scsi: arbitration initiator id %d (%02x) %08x\n"), rs->initiator_id, rs->data_write, M68K_GETPC);
  1010. #endif
  1011. } else if (!busy && select) {
  1012. if (countbits(rs->data_write) > 2 || rs->data_write == 0) {
  1013. #if RAW_SCSI_DEBUG
  1014. write_log(_T("raw_scsi: invalid scsi id selected mask (%02x) %08x\n"), rs->data_write, M68K_GETPC);
  1015. #endif
  1016. return;
  1017. }
  1018. rs->initiator_id = -1;
  1019. rs->bus_phase = SCSI_SIGNAL_PHASE_SELECT_1;
  1020. #if RAW_SCSI_DEBUG
  1021. write_log(_T("raw_scsi: selected scsi id mask (%02x) %08x\n"), rs->data_write, M68K_GETPC);
  1022. #endif
  1023. raw_scsi_set_signal_phase(rs, busy, select, atn);
  1024. }
  1025. break;
  1026. case SCSI_SIGNAL_PHASE_ARBIT:
  1027. rs->target_id = -1;
  1028. rs->target = NULL;
  1029. if (busy && select) {
  1030. rs->bus_phase = SCSI_SIGNAL_PHASE_SELECT_1;
  1031. }
  1032. break;
  1033. case SCSI_SIGNAL_PHASE_SELECT_1:
  1034. rs->atn = atn;
  1035. rs->msglun = -1;
  1036. rs->target_id = -1;
  1037. if (!busy) {
  1038. for (int i = 0; i < 8; i++) {
  1039. if (i == rs->initiator_id)
  1040. continue;
  1041. if ((rs->data_write & (1 << i)) && rs->device[i]) {
  1042. rs->target_id = i;
  1043. rs->target = rs->device[rs->target_id];
  1044. #if RAW_SCSI_DEBUG
  1045. write_log(_T("raw_scsi: selected id %d %08x\n"), rs->target_id, M68K_GETPC);
  1046. #endif
  1047. rs->io |= SCSI_IO_BUSY;
  1048. }
  1049. }
  1050. #if RAW_SCSI_DEBUG
  1051. if (rs->target_id < 0) {
  1052. for (int i = 0; i < 8; i++) {
  1053. if (i == rs->initiator_id)
  1054. continue;
  1055. if ((rs->data_write & (1 << i)) && !rs->device[i]) {
  1056. write_log(_T("raw_scsi: selected non-existing id %d %08x\n"), i, M68K_GETPC);
  1057. }
  1058. }
  1059. }
  1060. #endif
  1061. if (rs->target_id >= 0) {
  1062. rs->bus_phase = SCSI_SIGNAL_PHASE_SELECT_2;
  1063. } else {
  1064. if (!select) {
  1065. rs->bus_phase = SCSI_SIGNAL_PHASE_FREE;
  1066. }
  1067. }
  1068. }
  1069. break;
  1070. case SCSI_SIGNAL_PHASE_SELECT_2:
  1071. if (!select) {
  1072. scsi_start_transfer(rs->target);
  1073. rs->bus_phase = rs->atn ? SCSI_SIGNAL_PHASE_MESSAGE_OUT : SCSI_SIGNAL_PHASE_COMMAND;
  1074. rs->io = SCSI_IO_BUSY | SCSI_IO_REQ;
  1075. }
  1076. break;
  1077. }
  1078. }
  1079. static uae_u8 raw_scsi_get_signal_phase(struct raw_scsi *rs)
  1080. {
  1081. uae_u8 v = rs->io;
  1082. if (rs->bus_phase >= 0)
  1083. v |= rs->bus_phase;
  1084. if (rs->ack)
  1085. v &= ~SCSI_IO_REQ;
  1086. return v;
  1087. }
  1088. static uae_u8 raw_scsi_get_data_2(struct raw_scsi *rs, bool next, bool nodebug)
  1089. {
  1090. struct scsi_data *sd = rs->target;
  1091. uae_u8 v = 0;
  1092. switch (rs->bus_phase)
  1093. {
  1094. case SCSI_SIGNAL_PHASE_FREE:
  1095. v = 0;
  1096. break;
  1097. case SCSI_SIGNAL_PHASE_ARBIT:
  1098. #if RAW_SCSI_DEBUG
  1099. write_log(_T("raw_scsi: arbitration %08x\n"), M68K_GETPC);
  1100. #endif
  1101. v = rs->data_write;
  1102. break;
  1103. case SCSI_SIGNAL_PHASE_DATA_IN:
  1104. #if RAW_SCSI_DEBUG > 2
  1105. scsi_receive_data(sd, &v, false);
  1106. write_log(_T("raw_scsi: read data byte %02x (%d/%d) %08x\n"), v, sd->offset, sd->data_len, M68K_GETPC);
  1107. #endif
  1108. if (scsi_receive_data(sd, &v, next)) {
  1109. #if RAW_SCSI_DEBUG
  1110. write_log(_T("raw_scsi: data in finished, %d bytes: status phase\n"), sd->offset);
  1111. #endif
  1112. rs->bus_phase = SCSI_SIGNAL_PHASE_STATUS;
  1113. }
  1114. break;
  1115. case SCSI_SIGNAL_PHASE_STATUS:
  1116. #if RAW_SCSI_DEBUG
  1117. if (!nodebug || next)
  1118. write_log(_T("raw_scsi: status byte read %02x. Next=%d PC=%08x\n"), sd->status, next, M68K_GETPC);
  1119. #endif
  1120. v = sd->status;
  1121. if (next) {
  1122. sd->status = 0;
  1123. rs->bus_phase = SCSI_SIGNAL_PHASE_MESSAGE_IN;
  1124. }
  1125. break;
  1126. case SCSI_SIGNAL_PHASE_MESSAGE_IN:
  1127. #if RAW_SCSI_DEBUG
  1128. if (!nodebug || next)
  1129. write_log(_T("raw_scsi: message byte read %02x. Next=%d PC=%08x\n"), sd->status, next, M68K_GETPC);
  1130. #endif
  1131. v = sd->status;
  1132. rs->status = v;
  1133. if (next) {
  1134. bus_free(rs);
  1135. }
  1136. break;
  1137. default:
  1138. #if RAW_SCSI_DEBUG
  1139. write_log(_T("raw_scsi_get_data but bus phase is %d %08x!\n"), rs->bus_phase, M68K_GETPC);
  1140. #endif
  1141. break;
  1142. }
  1143. return v;
  1144. }
  1145. static uae_u8 raw_scsi_get_data(struct raw_scsi *rs, bool next)
  1146. {
  1147. return raw_scsi_get_data_2(rs, next, true);
  1148. }
  1149. static int getmsglen(uae_u8 *msgp, int len)
  1150. {
  1151. uae_u8 msg = msgp[0];
  1152. if (msg == 0 || (msg >= 0x02 && msg <= 0x1f) ||msg >= 0x80)
  1153. return 1;
  1154. if (msg >= 0x20 && msg <= 0x2f)
  1155. return 2;
  1156. // extended message, at least 3 bytes
  1157. if (len < 2)
  1158. return 3;
  1159. return msgp[1];
  1160. }
  1161. static void raw_scsi_write_data(struct raw_scsi *rs, uae_u8 data)
  1162. {
  1163. struct scsi_data *sd = rs->target;
  1164. int len;
  1165. switch (rs->bus_phase)
  1166. {
  1167. case SCSI_SIGNAL_PHASE_SELECT_1:
  1168. case SCSI_SIGNAL_PHASE_FREE:
  1169. break;
  1170. case SCSI_SIGNAL_PHASE_COMMAND:
  1171. sd->cmd[sd->offset++] = data;
  1172. len = scsicmdsizes[sd->cmd[0] >> 5];
  1173. #if RAW_SCSI_DEBUG > 1
  1174. write_log(_T("raw_scsi: got command byte %02x (%d/%d) %08x\n"), data, sd->offset, len, M68K_GETPC);
  1175. #endif
  1176. if (sd->offset >= len) {
  1177. if (rs->msglun >= 0) {
  1178. sd->cmd[1] &= ~(0x80 | 0x40 | 0x20);
  1179. sd->cmd[1] |= rs->msglun << 5;
  1180. }
  1181. scsi_emulate_analyze(rs->target);
  1182. if (sd->direction > 0) {
  1183. #if RAW_SCSI_DEBUG
  1184. write_log(_T("raw_scsi: data out %d bytes required\n"), sd->data_len);
  1185. #endif
  1186. scsi_start_transfer(sd);
  1187. rs->bus_phase = SCSI_SIGNAL_PHASE_DATA_OUT;
  1188. } else if (sd->direction <= 0) {
  1189. scsi_emulate_cmd(sd);
  1190. scsi_start_transfer(sd);
  1191. #if RAW_SCSI_DEBUG
  1192. if (sd->status) {
  1193. write_log(_T("raw_scsi: status = %d len = %d\n"), sd->status, sd->data_len);
  1194. }
  1195. #endif
  1196. if (!sd->status && sd->data_len > 0) {
  1197. #if RAW_SCSI_DEBUG
  1198. write_log(_T("raw_scsi: data in %d bytes waiting\n"), sd->data_len);
  1199. #endif
  1200. rs->bus_phase = SCSI_SIGNAL_PHASE_DATA_IN;
  1201. } else {
  1202. #if RAW_SCSI_DEBUG
  1203. write_log(_T("raw_scsi: no data, status = %d\n"), sd->status);
  1204. #endif
  1205. rs->bus_phase = SCSI_SIGNAL_PHASE_STATUS;
  1206. }
  1207. }
  1208. }
  1209. break;
  1210. case SCSI_SIGNAL_PHASE_DATA_OUT:
  1211. #if RAW_SCSI_DEBUG > 2
  1212. write_log(_T("raw_scsi: write data byte %02x (%d/%d) %08x\n"), data, sd->offset, sd->data_len, M68K_GETPC);
  1213. #endif
  1214. if (scsi_send_data(sd, data)) {
  1215. #if RAW_SCSI_DEBUG
  1216. write_log(_T("raw_scsi: data out finished, %d bytes\n"), sd->data_len);
  1217. #endif
  1218. scsi_emulate_cmd(sd);
  1219. rs->bus_phase = SCSI_SIGNAL_PHASE_STATUS;
  1220. }
  1221. break;
  1222. case SCSI_SIGNAL_PHASE_MESSAGE_OUT:
  1223. sd->msgout[sd->offset++] = data;
  1224. len = getmsglen(sd->msgout, sd->offset);
  1225. #if RAW_SCSI_DEBUG
  1226. write_log(_T("raw_scsi_put_data got message %02x (%d/%d) %08x\n"), data, sd->offset, len, M68K_GETPC);
  1227. #endif
  1228. if (sd->offset >= len) {
  1229. #if RAW_SCSI_DEBUG
  1230. write_log(_T("raw_scsi_put_data got message %02x (%d bytes)\n"), sd->msgout[0], len);
  1231. #endif
  1232. if ((sd->msgout[0] & (0x80 | 0x20)) == 0x80)
  1233. rs->msglun = sd->msgout[0] & 7;
  1234. scsi_start_transfer(sd);
  1235. rs->bus_phase = SCSI_SIGNAL_PHASE_COMMAND;
  1236. }
  1237. break;
  1238. default:
  1239. #if RAW_SCSI_DEBUG
  1240. write_log(_T("raw_scsi_put_data but bus phase is %d!\n"), rs->bus_phase);
  1241. #endif
  1242. break;
  1243. }
  1244. }
  1245. static void raw_scsi_put_data(struct raw_scsi *rs, uae_u8 data, bool databusoutput)
  1246. {
  1247. rs->data_write = data;
  1248. if (!databusoutput)
  1249. return;
  1250. raw_scsi_write_data(rs, data);
  1251. }
  1252. static void raw_scsi_set_ack(struct raw_scsi *rs, bool ack)
  1253. {
  1254. if (rs->ack != ack) {
  1255. rs->ack = ack;
  1256. if (!ack)
  1257. return;
  1258. if (rs->bus_phase < 0)
  1259. return;
  1260. if (!(rs->bus_phase & SCSI_IO_DIRECTION)) {
  1261. if (rs->databusoutput) {
  1262. raw_scsi_write_data(rs, rs->data_write);
  1263. }
  1264. } else {
  1265. raw_scsi_get_data_2(rs, true, false);
  1266. }
  1267. }
  1268. }
  1269. // APOLLO SOFTSCSI
  1270. void apollo_scsi_bput(uaecptr addr, uae_u8 v, uae_u32 config)
  1271. {
  1272. struct soft_scsi *as = getscsiboard(addr);
  1273. if (!as)
  1274. return;
  1275. int bank = addr & (0x800 | 0x400);
  1276. struct raw_scsi *rs = &as->rscsi;
  1277. addr &= 0x3fff;
  1278. if (bank == 0) {
  1279. raw_scsi_put_data(rs, v, true);
  1280. } else if (bank == 0xc00 && !(addr & 1)) {
  1281. as->irq = (v & 64) != 0;
  1282. raw_scsi_set_signal_phase(rs,
  1283. (v & 128) != 0,
  1284. (v & 32) != 0,
  1285. false);
  1286. } else if (bank == 0x400 && (addr & 1)) {
  1287. raw_scsi_put_data(rs, v, true);
  1288. raw_scsi_set_signal_phase(rs, true, false, false);
  1289. }
  1290. //write_log(_T("apollo scsi put %04x = %02x\n"), addr, v);
  1291. }
  1292. uae_u8 apollo_scsi_bget(uaecptr addr, uae_u32 config)
  1293. {
  1294. struct soft_scsi *as = getscsiboard(addr);
  1295. if (!as)
  1296. return 0;
  1297. int bank = addr & (0x800 | 0x400);
  1298. struct raw_scsi *rs = &as->rscsi;
  1299. uae_u8 v = 0xff;
  1300. addr &= 0x3fff;
  1301. if (bank == 0) {
  1302. v = raw_scsi_get_data(rs, true);
  1303. } else if (bank == 0x800 && (addr & 1)) {
  1304. uae_u8 t = raw_scsi_get_signal_phase(rs);
  1305. v = 0;
  1306. if (config & 1) // scsi module installed
  1307. v |= 1;
  1308. if (t & SCSI_IO_BUSY)
  1309. v |= 128;
  1310. if (t & SCSI_IO_SEL)
  1311. v |= 32;
  1312. if (t & SCSI_IO_REQ)
  1313. v |= 2;
  1314. if (t & SCSI_IO_DIRECTION)
  1315. v |= 8;
  1316. if (t & SCSI_IO_COMMAND)
  1317. v |= 16;
  1318. if (t & SCSI_IO_MESSAGE)
  1319. v |= 4;
  1320. v ^= (1 | 2 | 4 | 8 | 16 | 32 | 128);
  1321. //v |= apolloscsi.irq ? 64 : 0;
  1322. }
  1323. //write_log(_T("apollo scsi get %04x = %02x\n"), addr, v);
  1324. return v;
  1325. }
  1326. void apollo_add_ide_unit(int ch, struct uaedev_config_info *ci, struct romconfig *rc);
  1327. void apollo_add_scsi_unit(int ch, struct uaedev_config_info *ci, struct romconfig *rc)
  1328. {
  1329. if (ch < 0) {
  1330. generic_soft_scsi_add(-1, ci, rc, NONCR_APOLLO, -1, -1, ROMTYPE_APOLLO);
  1331. // make sure IDE side is also initialized
  1332. struct uaedev_config_info ci2 = { 0 };
  1333. apollo_add_ide_unit(-1, &ci2, rc);
  1334. } else {
  1335. if (ci->controller_type < HD_CONTROLLER_TYPE_SCSI_FIRST) {
  1336. apollo_add_ide_unit(ch, ci, rc);
  1337. } else {
  1338. generic_soft_scsi_add(ch, ci, rc, NONCR_APOLLO, -1, -1, ROMTYPE_APOLLO);
  1339. }
  1340. }
  1341. }
  1342. uae_u8 ncr5380_bget(struct soft_scsi *scsi, int reg);
  1343. void ncr5380_bput(struct soft_scsi *scsi, int reg, uae_u8 v);
  1344. static void supra_do_dma(struct soft_scsi *ncr)
  1345. {
  1346. int len = ncr->dmac_length;
  1347. for (int i = 0; i < len; i++) {
  1348. if (ncr->dmac_direction < 0) {
  1349. dma_put_byte(ncr->dmac_address & ncr->dma_mask, ncr5380_bget(ncr, 0));
  1350. } else if (ncr->dmac_direction > 0) {
  1351. ncr5380_bput(ncr, 0, dma_get_byte(ncr->dmac_address & ncr->dma_mask));
  1352. }
  1353. ncr->dmac_length--;
  1354. ncr->dmac_address++;
  1355. }
  1356. }
  1357. uae_u8 aic_bget_dma(struct soft_scsi *scsi, bool *phaseerr);
  1358. void aic_bput_dma(struct soft_scsi *scsi, uae_u8 v, bool *phaseerr);
  1359. static void hardframe_do_dma(struct soft_scsi *ncr)
  1360. {
  1361. int len = ncr->dmac_length;
  1362. for (int i = 0; i < len; i++) {
  1363. bool phaseerr;
  1364. if (ncr->dmac_direction < 0) {
  1365. uae_u8 v = aic_bget_dma(ncr, &phaseerr);
  1366. if (phaseerr)
  1367. break;
  1368. dma_put_byte(ncr->dmac_address & ncr->dma_mask, v);
  1369. } else if (ncr->dmac_direction > 0) {
  1370. uae_u8 v = dma_get_byte(ncr->dmac_address & ncr->dma_mask);
  1371. aic_bput_dma(ncr, v, &phaseerr);
  1372. if (phaseerr)
  1373. break;
  1374. }
  1375. ncr->dmac_length--;
  1376. ncr->dmac_address++;
  1377. }
  1378. }
  1379. static void xebec_do_dma(struct soft_scsi *ncr)
  1380. {
  1381. struct raw_scsi *rs = &ncr->rscsi;
  1382. while (rs->bus_phase == SCSI_SIGNAL_PHASE_DATA_OUT || rs->bus_phase == SCSI_SIGNAL_PHASE_DATA_IN) {
  1383. if (rs->bus_phase == SCSI_SIGNAL_PHASE_DATA_IN) {
  1384. dma_put_byte(ncr->dmac_address & ncr->dma_mask, ncr5380_bget(ncr, 8));
  1385. } else if (rs->bus_phase == SCSI_SIGNAL_PHASE_DATA_OUT) {
  1386. ncr5380_bput(ncr, 8, dma_get_byte(ncr->dmac_address & ncr->dma_mask));
  1387. }
  1388. }
  1389. }
  1390. static void overdrive_do_dma(struct soft_scsi *ncr)
  1391. {
  1392. struct raw_scsi *rs = &ncr->rscsi;
  1393. while ((rs->bus_phase == SCSI_SIGNAL_PHASE_DATA_OUT || rs->bus_phase == SCSI_SIGNAL_PHASE_DATA_IN) && ncr->dmac_length > 0) {
  1394. if (rs->bus_phase == SCSI_SIGNAL_PHASE_DATA_IN) {
  1395. dma_put_byte(ncr->dmac_address & ncr->dma_mask, ncr5380_bget(ncr, 8));
  1396. ncr->dmac_address++;
  1397. ncr->dmac_length--;
  1398. } else if (rs->bus_phase == SCSI_SIGNAL_PHASE_DATA_OUT) {
  1399. ncr5380_bput(ncr, 8, dma_get_byte(ncr->dmac_address & ncr->dma_mask));
  1400. ncr->dmac_address++;
  1401. ncr->dmac_length--;
  1402. }
  1403. }
  1404. }
  1405. static void fireball_do_dma(struct soft_scsi* ncr)
  1406. {
  1407. struct raw_scsi* rs = &ncr->rscsi;
  1408. while (rs->bus_phase == SCSI_SIGNAL_PHASE_DATA_OUT || rs->bus_phase == SCSI_SIGNAL_PHASE_DATA_IN) {
  1409. if (rs->bus_phase == SCSI_SIGNAL_PHASE_DATA_IN) {
  1410. dma_put_byte(ncr->dmac_address & ncr->dma_mask, ncr5380_bget(ncr, 8));
  1411. ncr->dmac_address++;
  1412. } else if (rs->bus_phase == SCSI_SIGNAL_PHASE_DATA_OUT) {
  1413. ncr5380_bput(ncr, 8, dma_get_byte(ncr->dmac_address & ncr->dma_mask));
  1414. ncr->dmac_address++;
  1415. }
  1416. }
  1417. }
  1418. static void dma_check(struct soft_scsi *ncr)
  1419. {
  1420. if (ncr->dmac_active && ncr->dma_direction) {
  1421. m68k_cancel_idle();
  1422. if (ncr->type == NCR5380_SUPRA && ncr->subtype == 4) {
  1423. if (ncr->dmac_direction != ncr->dma_direction) {
  1424. write_log(_T("SUPRADMA: mismatched direction\n"));
  1425. ncr->dmac_active = 0;
  1426. return;
  1427. }
  1428. supra_do_dma(ncr);
  1429. }
  1430. if (ncr->type == NCR5380_XEBEC) {
  1431. xebec_do_dma(ncr);
  1432. }
  1433. if (ncr->type == NONCR_HARDFRAME) {
  1434. hardframe_do_dma(ncr);
  1435. }
  1436. if (ncr->type == NCR5380_OVERDRIVE) {
  1437. overdrive_do_dma(ncr);
  1438. }
  1439. if (ncr->type == NCR5380_FIREBALL) {
  1440. fireball_do_dma(ncr);
  1441. }
  1442. ncr->dmac_active = 0;
  1443. }
  1444. }
  1445. void x86_doirq(uint8_t irqnum);
  1446. static void ncr80_rethink(void)
  1447. {
  1448. for (int i = 0; soft_scsi_devices[i]; i++) {
  1449. struct soft_scsi *s = soft_scsi_devices[i];
  1450. if (s->irq && s->intena && (
  1451. (s->c400 && (s->regs_400[0] & 0x10) && !s->c400_count) ||
  1452. (s->dp8490v && (s->regs[18] & 0x20)) ||
  1453. (!s->c400 && !s->dp8490v)))
  1454. {
  1455. if (soft_scsi_devices[i] == x86_hd_data) {
  1456. ;// x86_doirq(5);
  1457. } else {
  1458. safe_interrupt_set(IRQ_SOURCE_SCSI, i, soft_scsi_devices[i]->level6);
  1459. }
  1460. }
  1461. }
  1462. }
  1463. // AIC-6250
  1464. static void aic_int(struct soft_scsi *scsi, uae_u8 mask)
  1465. {
  1466. scsi->regs[16 + 8] |= mask;
  1467. if ((scsi->regs[16 + 8] & scsi->regs[3]) & 0x1f) {
  1468. scsi->irq = true;
  1469. devices_rethink_all(ncr80_rethink);
  1470. } else {
  1471. scsi->irq = false;
  1472. }
  1473. }
  1474. static bool aic_phase_match(struct soft_scsi *scsi)
  1475. {
  1476. struct raw_scsi *r = &scsi->rscsi;
  1477. uae_u8 phase = r->bus_phase;
  1478. bool cd = (phase & SCSI_IO_COMMAND) != 0;
  1479. bool io = (phase & SCSI_IO_DIRECTION) != 0;
  1480. bool msg = (phase & SCSI_IO_MESSAGE) != 0;
  1481. if (phase >= 0 &&
  1482. ((scsi->regs[9] >> 5) & 1) == msg &&
  1483. ((scsi->regs[9] >> 6) & 1) == io &&
  1484. ((scsi->regs[9] >> 7) & 1) == cd) {
  1485. return true;
  1486. }
  1487. return false;
  1488. }
  1489. static void aic_reg_inc(struct soft_scsi *scsi)
  1490. {
  1491. if (scsi->aic_reg >= 8)
  1492. return;
  1493. scsi->aic_reg++;
  1494. }
  1495. static uae_u8 aic_bget_reg(struct soft_scsi *scsi)
  1496. {
  1497. return scsi->aic_reg & 15;
  1498. }
  1499. static uae_u8 aic_bget_dma(struct soft_scsi *scsi, bool *phaseerr)
  1500. {
  1501. struct raw_scsi *r = &scsi->rscsi;
  1502. if (!scsi->dma_direction)
  1503. return 0;
  1504. if (!aic_phase_match(scsi)) {
  1505. if (phaseerr)
  1506. *phaseerr = true;
  1507. if (!scsi->dmac_active) {
  1508. aic_int(scsi, 0x08); // COMMAND DONE
  1509. }
  1510. scsi->dma_direction = 0;
  1511. return 0;
  1512. }
  1513. if (phaseerr)
  1514. *phaseerr = false;
  1515. return raw_scsi_get_data(r, true);
  1516. }
  1517. static uae_u8 aic_bget_data(struct soft_scsi *scsi)
  1518. {
  1519. struct raw_scsi *r = &scsi->rscsi;
  1520. int reg = scsi->aic_reg;
  1521. uae_u8 v = scsi->regs[reg];
  1522. aic_reg_inc(scsi);
  1523. switch (reg)
  1524. {
  1525. case 0:
  1526. v = (scsi->dmac_length >> 0) & 0xff;
  1527. break;
  1528. case 1:
  1529. v = (scsi->dmac_length >> 8) & 0xff;
  1530. break;
  1531. case 2:
  1532. v = (scsi->dmac_length >> 16) & 0xff;
  1533. break;
  1534. case 6: // REVISION CONTROL
  1535. v = 2;
  1536. break;
  1537. case 7: // STATUS 0
  1538. {
  1539. v = scsi->regs[reg + 16] & 2;
  1540. if (r->bus_phase == SCSI_SIGNAL_PHASE_FREE)
  1541. v |= 0x10; // BUS FREE
  1542. if (raw_scsi_get_signal_phase(r) & SCSI_IO_REQ)
  1543. v |= 0x04; // SCSI REQ ON
  1544. if (scsi->dmac_length == 0)
  1545. v |= 0x01; // DMA BYTE COUNT ZERO
  1546. if ((raw_scsi_get_signal_phase(r) & SCSI_IO_REQ) && !aic_phase_match(scsi))
  1547. v |= 0x20; // PHASE MISMATCH
  1548. }
  1549. break;
  1550. case 8: // STATUS 1
  1551. {
  1552. v = scsi->regs[reg + 16] | 0x40;
  1553. if (scsi->regs[8] & 2) { // SCSI RESET OUT
  1554. v |= 0x20; // SCSI RESET IN
  1555. } else {
  1556. v &= ~0x20;
  1557. }
  1558. scsi->regs[reg + 16] = v;
  1559. }
  1560. break;
  1561. case 9: // SCSI SIGNAL
  1562. {
  1563. uae_u8 t = raw_scsi_get_signal_phase(r);
  1564. v = 0;
  1565. if (t & SCSI_IO_BUSY)
  1566. v |= 0x04;
  1567. if (t & SCSI_IO_ATN)
  1568. v |= 0x10;
  1569. if (t & SCSI_IO_SEL)
  1570. v |= 0x08;
  1571. if (t & SCSI_IO_REQ)
  1572. v |= 0x02;
  1573. if (t & SCSI_IO_DIRECTION)
  1574. v |= 0x40;
  1575. if (t & SCSI_IO_COMMAND)
  1576. v |= 0x80;
  1577. if (t & SCSI_IO_MESSAGE)
  1578. v |= 0x20;
  1579. if (r->ack)
  1580. v |= 0x01;
  1581. }
  1582. break;
  1583. case 10: // SCSI ID DATA
  1584. v = scsi->regs[16 + 10];
  1585. break;
  1586. case 13:
  1587. {
  1588. // SCSI ID (4 to 7 only)
  1589. int vv = scsi->rc->device_id - 4;
  1590. if (vv < 0)
  1591. vv = 0;
  1592. vv ^= 3;
  1593. vv = (vv >> 1) | (vv << 1);
  1594. v = (vv & 3) << 5;
  1595. }
  1596. break;
  1597. }
  1598. return v;
  1599. }
  1600. static void aic_bput_reg(struct soft_scsi *scsi, uae_u8 v)
  1601. {
  1602. scsi->aic_reg = v & 15;
  1603. }
  1604. static void aic_bput_dma(struct soft_scsi *scsi, uae_u8 v, bool *phaseerr)
  1605. {
  1606. struct raw_scsi *r = &scsi->rscsi;
  1607. if (!scsi->dma_direction)
  1608. return;
  1609. if (!aic_phase_match(scsi)) {
  1610. if (phaseerr)
  1611. *phaseerr = true;
  1612. if (!scsi->dmac_active) {
  1613. aic_int(scsi, 0x08); // COMMAND DONE
  1614. }
  1615. scsi->dma_direction = 0;
  1616. return;
  1617. }
  1618. if (phaseerr)
  1619. *phaseerr = false;
  1620. raw_scsi_put_data(r, v, true);
  1621. }
  1622. static void aic_bput_data(struct soft_scsi *scsi, uae_u8 v)
  1623. {
  1624. struct raw_scsi *r = &scsi->rscsi;
  1625. int reg = scsi->aic_reg;
  1626. aic_reg_inc(scsi);
  1627. switch (reg)
  1628. {
  1629. case 0:
  1630. scsi->dmac_length &= 0xffff00;
  1631. scsi->dmac_length |= v << 0;
  1632. break;
  1633. case 1:
  1634. scsi->dmac_length &= 0xff00ff;
  1635. scsi->dmac_length |= v << 8;
  1636. break;
  1637. case 2:
  1638. scsi->dmac_length &= 0x00ffff;
  1639. scsi->dmac_length |= v << 16;
  1640. break;
  1641. case 3: // INT MSK
  1642. // cleared interrupt mask clears request
  1643. scsi->regs[16 + 8] &= v | ~0x1f;
  1644. if (v & 0x40) { // ARB/SEL START
  1645. raw_scsi_put_data(r, scsi->regs[10], false);
  1646. raw_scsi_set_signal_phase(r, false, true, (v & 0x20) != 0);
  1647. raw_scsi_set_signal_phase(r, true, false, false);
  1648. aic_int(scsi, 0x08); // COMMAND DONE
  1649. scsi->regs[11] = scsi->regs[10]; // SOURCE AND DESTINATION ID = DATA
  1650. v &= ~0x40;
  1651. }
  1652. aic_int(scsi, 0);
  1653. break;
  1654. case 5:
  1655. if (v & 1) { // DMA XFER EN
  1656. scsi->dma_direction = (v & 2) ? 1 : -1;
  1657. if (scsi->dmac_active) {
  1658. dma_check(scsi);
  1659. aic_int(scsi, 0x08); // COMMAND DONE
  1660. scsi->dma_direction = 0;
  1661. }
  1662. } else {
  1663. scsi->dma_direction = 0;
  1664. }
  1665. break;
  1666. case 8: // CONTROL
  1667. if (v & 2) { // SCSI RESET OUT
  1668. raw_scsi_reset(r);
  1669. }
  1670. if (v & 0x80) { // AUTO SCSI PIO REQ
  1671. if (aic_phase_match(scsi)) {
  1672. int phase = r->bus_phase;
  1673. bool io = (phase & SCSI_IO_DIRECTION) != 0;
  1674. scsi->regs[16 + 7] &= ~0x02;
  1675. if (!io) {
  1676. raw_scsi_put_data(r, scsi->regs[10], true);
  1677. } else {
  1678. scsi->regs[16 + 10] = raw_scsi_get_data(r, true);
  1679. }
  1680. aic_int(scsi, 0x08); // COMMAND DONE
  1681. if (phase != r->bus_phase)
  1682. scsi->regs[16 + 7] |= 0x02; // SCSI PHASE CHG/ATN
  1683. v &= ~0x80;
  1684. } else {
  1685. aic_int(scsi, 0x10); // ERROR
  1686. }
  1687. }
  1688. break;
  1689. case 9: // SCSI SIGNAL
  1690. break;
  1691. }
  1692. scsi->regs[reg] = v;
  1693. }
  1694. // NCR 53C80/MISC SCSI-LIKE
  1695. static void ncr5380_set_irq(struct soft_scsi *scsi)
  1696. {
  1697. if (scsi->irq)
  1698. return;
  1699. scsi->irq = true;
  1700. devices_rethink_all(ncr80_rethink);
  1701. if (scsi->delayed_irq)
  1702. x_do_cycles(2 * CYCLE_UNIT);
  1703. #if NCR5380_DEBUG_IRQ
  1704. write_log(_T("IRQ\n"));
  1705. #endif
  1706. }
  1707. static void ncr5380_databusoutput(struct soft_scsi *scsi)
  1708. {
  1709. bool databusoutput = (scsi->regs[1] & 1) != 0;
  1710. struct raw_scsi *r = &scsi->rscsi;
  1711. if (r->bus_phase >= 0 && (r->bus_phase & SCSI_IO_DIRECTION))
  1712. databusoutput = false;
  1713. raw_scsi_set_databus(r, databusoutput);
  1714. }
  1715. static void ncr5380_check(struct soft_scsi *scsi)
  1716. {
  1717. ncr5380_databusoutput(scsi);
  1718. }
  1719. static void ncr5380_check_phase(struct soft_scsi *scsi)
  1720. {
  1721. if (!(scsi->regs[2] & 2))
  1722. return;
  1723. if (scsi->regs[2] & 0x40)
  1724. return;
  1725. if (scsi->rscsi.bus_phase != (scsi->regs[3] & 7)) {
  1726. if (scsi->dma_controller) {
  1727. scsi->regs[5] |= 0x80; // end of dma
  1728. scsi->regs[3] |= 0x80; // last byte sent
  1729. }
  1730. ncr5380_set_irq(scsi);
  1731. }
  1732. }
  1733. static void ncr5380_reset(struct soft_scsi *scsi, bool busreset)
  1734. {
  1735. struct raw_scsi *r = &scsi->rscsi;
  1736. if (scsi->dp8490v) {
  1737. // DP8490V manual says all registers are reset but that can't work
  1738. // with Fireball driver. It assumes IMR is not reset.
  1739. memset(scsi->regs, 0, 16);
  1740. } else {
  1741. memset(scsi->regs, 0, sizeof scsi->regs);
  1742. }
  1743. if (busreset) {
  1744. raw_scsi_reset_bus(scsi);
  1745. scsi->regs[1] = 0x80;
  1746. ncr5380_set_irq(scsi);
  1747. }
  1748. }
  1749. uae_u8 ncr5380_bget(struct soft_scsi *scsi, int reg)
  1750. {
  1751. if (reg > 8)
  1752. return 0;
  1753. if (scsi->dp8490v) {
  1754. if ((scsi->regs[1] & 0x40) && reg == 7) {
  1755. reg = 17;
  1756. }
  1757. }
  1758. uae_u8 v = scsi->regs[reg];
  1759. struct raw_scsi *r = &scsi->rscsi;
  1760. switch(reg)
  1761. {
  1762. case 1:
  1763. break;
  1764. case 4:
  1765. {
  1766. uae_u8 oldv = v;
  1767. uae_u8 t = raw_scsi_get_signal_phase(r);
  1768. v = 0;
  1769. if (t & SCSI_IO_BUSY)
  1770. v |= 1 << 6;
  1771. if (t & SCSI_IO_REQ)
  1772. v |= 1 << 5;
  1773. if (t & SCSI_IO_SEL)
  1774. v |= 1 << 1;
  1775. if (r->bus_phase >= 0)
  1776. v |= r->bus_phase << 2;
  1777. if (scsi->regs[1] & 0x80)
  1778. v |= 0x80;
  1779. scsi->regs[reg] = v;
  1780. if (scsi->busy_delayed_hack && !(v & (1 << 6)) && (oldv & (1 << 6))) {
  1781. scsi->busy_delayed_hack_cnt = 2;
  1782. }
  1783. if (scsi->busy_delayed_hack_cnt > 0) {
  1784. scsi->busy_delayed_hack_cnt--;
  1785. v |= 1 << 6;
  1786. }
  1787. }
  1788. break;
  1789. case 5:
  1790. {
  1791. uae_u8 t = raw_scsi_get_signal_phase(r);
  1792. v &= (0x80 | 0x40 | 0x20 | 0x04);
  1793. if (t & SCSI_IO_ATN)
  1794. v |= 1 << 1;
  1795. if (r->bus_phase == (scsi->regs[3] & 7)) {
  1796. v |= 1 << 3;
  1797. }
  1798. if (scsi->irq) {
  1799. v |= 1 << 4;
  1800. }
  1801. if (scsi->dma_drq || (scsi->dma_active && !scsi->dma_controller && r->bus_phase == (scsi->regs[3] & 7))) {
  1802. scsi->dma_drq = true;
  1803. if (scsi->dma_autodack && r->bus_phase != (scsi->regs[3] & 7))
  1804. scsi->dma_drq = false;
  1805. if (scsi->dma_drq)
  1806. v |= 1 << 6;
  1807. }
  1808. if (scsi->regs[2] & 4) {
  1809. // monitor busy
  1810. if (r->bus_phase == SCSI_SIGNAL_PHASE_FREE) {
  1811. // any loss of busy = Busy error
  1812. // not just "unexpected" loss of busy
  1813. v |= 1 << 2;
  1814. scsi->dmac_active = false;
  1815. }
  1816. }
  1817. }
  1818. break;
  1819. case 0:
  1820. v = raw_scsi_get_data(r, false);
  1821. break;
  1822. case 6:
  1823. v = raw_scsi_get_data(r, scsi->dma_active);
  1824. ncr5380_check_phase(scsi);
  1825. break;
  1826. case 7:
  1827. scsi->irq = false;
  1828. break;
  1829. case 17: // DP8490V MODE_E
  1830. {
  1831. int efr = (scsi->regs[17] >> 1) & 3;
  1832. if (efr == 3) {
  1833. v = 0;
  1834. uae_u8 t = raw_scsi_get_signal_phase(r);
  1835. // End of DMA -> DMA Phase Mismatch
  1836. if (scsi->regs[5] & 0x80) {
  1837. v = 0x10;
  1838. }
  1839. // Any Phase Mismatch
  1840. if (r->bus_phase == (scsi->regs[3] & 7)) {
  1841. v |= 0x20;
  1842. }
  1843. scsi->regs[17] &= ~(3 << 1);
  1844. }
  1845. }
  1846. break;
  1847. case 8: // fake dma port
  1848. v = raw_scsi_get_data(r, true);
  1849. ncr5380_check_phase(scsi);
  1850. break;
  1851. }
  1852. ncr5380_check(scsi);
  1853. return v;
  1854. }
  1855. void ncr5380_bput(struct soft_scsi *scsi, int reg, uae_u8 v)
  1856. {
  1857. if (reg > 8)
  1858. return;
  1859. if (scsi->dp8490v) {
  1860. if ((scsi->regs[1] & 0x40) && reg == 7) {
  1861. reg = 17;
  1862. }
  1863. }
  1864. bool dataoutput = (scsi->regs[1] & 1) != 0;
  1865. struct raw_scsi *r = &scsi->rscsi;
  1866. uae_u8 old = scsi->regs[reg];
  1867. scsi->regs[reg] = v;
  1868. switch(reg)
  1869. {
  1870. case 0:
  1871. {
  1872. r->data_write = v;
  1873. // assert data bus can be only active if direction is out
  1874. // and bus phase matches
  1875. if (r->databusoutput) {
  1876. if (((scsi->regs[2] & 2) && scsi->dma_active) || r->bus_phase < 0) {
  1877. raw_scsi_write_data(r, v);
  1878. ncr5380_check_phase(scsi);
  1879. }
  1880. }
  1881. }
  1882. break;
  1883. case 1:
  1884. {
  1885. scsi->regs[reg] &= ~((1 << 5) | (1 << 6));
  1886. scsi->regs[reg] |= old & ((1 << 5) | (1 << 6)); // AIP, LA
  1887. if (!(v & 0x80)) {
  1888. bool init = r->bus_phase < 0;
  1889. ncr5380_databusoutput(scsi);
  1890. if (init && !dataoutput && (v & 1) && (scsi->regs[2] & 1)) {
  1891. r->bus_phase = SCSI_SIGNAL_PHASE_SELECT_1;
  1892. }
  1893. raw_scsi_set_signal_phase(r,
  1894. (v & (1 << 3)) != 0,
  1895. (v & (1 << 2)) != 0,
  1896. (v & (1 << 1)) != 0);
  1897. if (!(scsi->regs[2] & 2))
  1898. raw_scsi_set_ack(r, (v & (1 << 4)) != 0);
  1899. }
  1900. if (v & 0x80) { // RST
  1901. ncr5380_reset(scsi, true);
  1902. }
  1903. if (scsi->dp8490v) {
  1904. scsi->regs[reg] &= ~0x40

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