/MSP-EXP430FR5969/MSP-EXP430FR5969_RC5_to_I2C_Slave.4th
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Possible License(s): GPL-3.0
- ; -------------------------------------
- ; MSP-EXP430FR5969_RC5_to_I2C_Slave.4th
- ; -------------------------------------
- STOP ; to stop any interrupt in progress
- WIPE ;
- NOECHO ; comment to debug
- ; FORTH source file
- ; Copyright (C) <2016> <J.M. THOORENS>
- ;
- ; This program is free software: you can redistribute it and/or modify
- ; it under the terms of the GNU General Public License as published by
- ; the Free Software Foundation, either version 3 of the License, or
- ; (at your option) any later version.
- ;
- ; This program is distributed in the hope that it will be useful,
- ; but WITHOUT ANY WARRANTY; without even the implied warranty of
- ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- ; GNU General Public License for more details.
- ;
- ; You should have received a copy of the GNU General Public License
- ; along with this program. If not, see <http://www.gnu.org/licenses/>.
- ; ========================================
- ; DEMO with two MSP-EXP430FR5969 LAUNCHPAD
- ; test : I2C_MASTER READ & I2C_SLAVE WRITE
- ; ========================================
- ; load this MSP-EXP430FR969_RC5_to_I2C_Slave.4th file on the first LAUNCHPAD
- ; load MSP-EXP430FR5969_I2C_Soft_Master_to_PJ_LCD_2x20.4th on the other LAUNCHPAD
- ; target : MSP-EXP430fr5969 LAUNCHPAD
- ; with code : "FORTH_MSP430FR596916MHzT16.HEX"
- ; ===================================================================================
- ; in case of 3.3V powered by UARTtoUSB bridge, open J13 straps {RST,TST,V+,5V} BEFORE
- ; ===================================================================================
- ; -----------------------------------------------
- ; MSP - LAUNCHPAD <--> OUTPUT WORLD
- ; -----------------------------------------------
- ; P4.6 - J6 - LED1 red
- ; P1.0 - LED2 green
- ; P4.5 - Switch S1 \\\ <--- LCD contrast + (finger :-)
- ; P1.1 - Switch S2 \\\ <--- LCD contrast - (finger ;-)
- ; GND - J1.2 \\\ <-------+---0V0----------> 1 LCD_Vss
- ; VCC - J1.3 \\\ >------ | --3V6-----+----> 2 LCD_Vdd
- ; \\\ | |
- ; \\\ |___ 470n ---
- ; \\\ ^ | ---
- ; \\\ / \ BAT54 |
- ; \\\ --- |
- ; \\\ 100n | 2k2 |
- ; P2.2 - J4.7 UCB0 CLK TB0.2 \\\ >---||--+--^/\/\/v--+----> 3 LCD_Vo (=0V6 without modulation)
- ; P3.4 - J4.8 \\\ -------------------------> 4 LCD_RS
- ; P3.5 - J4.9 \\\ -------------------------> 5 LCD_R/W
- ; P3.6 - J4.10 \\\ -------------------------> 6 LCD_EN0
- ; PJ.0 - J3.1 \\\ <------------------------> 11 LCD_DB4
- ; PJ.1 - J3.3 \\\ <------------------------> 12 LCD_DB5
- ; PJ.2 - J3.5 \\\ <------------------------> 13 LCD_DB5
- ; PJ.3 - J3.7 \\\ <------------------------> 14 LCD_DB7
-
- ; P2.0 - J13.8 UCA0 TXD ---> RX UARTtoUSB bridge
- ; P2.1 - J13.10 UCA0 RXD <--- TX UARTtoUSB bridge
- ; P4.1 - J13.14 RTS ---> CTS UARTtoUSB bridge (optional hardware control flow)
- ; VCC - J13.16 <--- VCC (optional supply from UARTtoUSB bridge - WARNING ! 3.3V !)
- ; GND - J13.20 <--> GND (optional supply from UARTtoUSB bridge)
-
- ; VCC - J11.1 ---> VCC SD_CardAdapter
- ; GND - J12.3 <--> GND SD_CardAdapter
- ; P2.4 - J4.6 UCA1 CLK ---> CLK SD_CardAdapter (SCK)
- ; P4.3 - J4.5 ---> CS SD_CardAdapter (Card Select)
- ; P2.5 - J4.4 UCA1 TXD/SIMO ---> SDI SD_CardAdapter (MOSI)
- ; P2.6 - J4.3 UCA1 RXD/SOMI <--- SDO SD_CardAdapter (MISO)
- ; P4.2 - J4.2 <--- CD SD_CardAdapter (Card Detect)
-
- ; P4.0 - J3.10 <--- OUT IR_Receiver (1 TSOP32236)
- ; VCC - J3.2 ---> VCC IR_Receiver (2 TSOP32236)
- ; GND - J3.9 <--> GND IR_Receiver (3 TSOP32236)
-
- ; PJ.4 - LFXI 32768Hz quartz
- ; PJ.5 - LFXO 32768Hz quartz
- ; PJ.6 - HFXI
- ; PJ.7 - HFXO
-
- ; P1.2 - J5.19 Soft I2C_Master <--> SDA
- ; P1.3 - J5.11 Soft I2C_Master ---> SCL
- ; P1.4 - J5.12 TB0.1 <--> free
- ; P1.5 - J5.13 UCA0 CLK TB0.2 <--> free
- ; P1.6 - J5.15 UCB0 SDA/SIMO <--> SDA <------------------------------------------------------> P1.2 other LAUNCHPAD
- ; P1.7 - J5.14 UCB0 SCL/SOMI <--- SCL <------------------------------------------------------- P1.3 other LAUNCHPAD
- ; P3.0 - J5.7 <--- free
- ; P2.3 - NC
- ; P2.7 - NC
- ; P3.1 - NC
- ; P3.2 - NC
- ; P3.3 - NC
- ; P3.7 - NC
- ; P4.4 - NC
- ; P4.7 - NC
- ; HERE ; general minidump, part 1
- VARIABLE MY_I2CADR ; slave I2C address without RW flag (low byte) + DATA0 input (HIGH byte)
- 2 ALLOT ; next the low byte of MY_I2CADR word, it is the input buffer
- VARIABLE I2CS_OUT ; buffer output, lentgh (low byte),DATA0 output (HIGH byte)
- ; 2 ALLOT ; this byte lentgh is shared by input and output buffers
- ; P4.0 - J3.10 <--- OUT IR_Receiver (1 TSOP32236)
- ; VCC - J3.2 ---> VCC IR_Receiver (2 TSOP32236)
- ; GND - J3.9 <--> GND IR_Receiver (3 TSOP32236)
-
- ; ------------------------------;
- ; IR_RC5 driver ;
- ; ******************************;
- CODE IR_RC5 ; wake up on P4.0 change interrupt
- ; ******************************;
- BIC #0xF8,0(RSP) ; CPU on, GIE off in oldSR
- ; ------------------------------;
- ; in : SR(9)=old Toggle bit memory
- ; SMclock = 8 MHz or 16 MHz
- ; use : U,V,W,X,Y, TA0 timer, TA0R register
- ; out : U = 0 x T A4 A3 A2 A1 A0| 0 C6 C5 C4 C3 C2 C1 C0
- ; SR(9)=new Toggle bit memory
- ; ------------------------------;
- ; RC5_FirstStartBitHalfCycle: ;
- ; ------------------------------;
- MOV #0,&0x0360 ; predivide by 1 in TA0EX0 register ( 8 MHZ), reset value
- ; MOV #1,&0x0360 ; predivide by 2 in TA0EX0 register (16 MHZ)
- ; MOV #2,&0x0360 ; predivide by 3 in TA0EX0 register (24 MHZ)
- MOV #1778,X ; RC5_Period in us
- MOV #14,W ; count of loop
- BEGIN ;
- ; ------------------------------;
- ; RC5_TopSynchro: ; <--- loop back ---+ with readjusted RC5_Period
- ; ------------------------------; | here, we are just after 1/2 RC5_cycle
- MOV #0b1011100100,&0x0340 ; (re)start timer_A | SMCLK_pre/2 /8 : 2us time interval,free running,clear TA0_IFG and TA0R
- ; RC5_Compute_3_4Period: ; |
- RRUM #1,X ; X=1/2 cycle |
- MOV X,Y ; Y=1/2 ^
- RRUM #1,Y ; Y=1/4
- ADD X,Y ; Y=3/4
- ; RC5_Wait_1_4: ; wait 3/4 cycle after 1/2 cycle to sample RC5_Input at 1/4 cycle
- BEGIN CMP Y,&0x0350 ; CMP &TA0R with 3/4 cycle value
- = UNTIL ;
- ; ------------------------------;
- ; RC5_Sample: ; at 1/4 cycle, we can sample RC5_input, ST2/C6 bit first
- ; ------------------------------;
- BIT.B #0x01,&0x0221 ; C_flag = P4.0 = IR bit
- ADDC V,V ; C_flag <-- V(15):V(0) <-- C_flag
- MOV.B &0x0221,&0x0239 ; preset IES_4.0 state for next IFG
- BIC.B #0x01,&0x023D ; clear P4.0_IFG after full cycle pin change
- SUB #1,W ; decrement count loop
- ; count = 13 ==> V = x x x x x x x x |x x x x x x x /C6
- ; count = 0 ==> V = x x /C6 Tg A4 A3 A2 A1|A0 C5 C4 C3 C2 C1 C0 1
- 0<> WHILE ; ----> out of loop ----+
- ; RC5_compute_2_4_OverFlow: ; |
- ADD X,Y ; | out of bound = 5/4 period
- ; RC5_WaitHalfCycleP1.2_IFG: ; |
- BEGIN ; |
- CMP Y,&0x0350 ; | TA0R = 5/4 cycle test
- >= IF ; | if cycle time out of bound
- MOV #4,&0x0340 ; | stop timer_A and clear TA0R
- RETI ; | then quit to do nothing
- THEN ; |
- ; ------------------------------; |
- BIT.B #0x01,&0x023D ; ^ | test P4.0_IFG
- <> UNTIL ; | |
- MOV &0x0350,X ; | | get new RC5_period value
- REPEAT ; ----> loop back --+ |
- ; ------------------------------; |
- ; RC5_SampleEndOf: ; <---------------------+
- ; ------------------------------;
- MOV #4,&0x0340 ; stop timer_A
- RLAM #1,V ; V = x /C6 Tg A4 A3 A2 A1 A0|C5 C4 C3 C2 C1 C0 1 0
- ; ------------------------------;
- ; ------------------------------;
- ; Only New_RC5_Command ADD_ON ; use SR(9) bit as toggle bit
- ; ------------------------------;
- MOV @RSP,X ; retiSR(9) = old RC5 toggle bit
- RLAM #4,X ; retiSR(9) --> X(13)
- XOR V,X ; (new XOR old)(13) Toggle bit
- BIT #0x2000,X ; X(13) = New_RC5_command
- 0= IF ;
- RETI ; case of repeated RC5_command : RETI without SR(9) change
- THEN ;
- XOR #0x0200,0(RSP) ; change Toggle bit memory SR(9)
- ; ------------------------------;
- ; ------------------------------;
- ; RC5_ComputeNewRC5word ;
- ; ------------------------------;
- MOV.B V,U ; U= 0 0 0 0 0 0 0 0 C5 C4 C3 C2 C1 C0 0 0
- RRUM #2,U ; U= 0 0 0 0 0 0 0 0 0 0 C5 C4 C3 C2 C1 C0
- ; AND #0x7F00,V ; V= 0 /C6 Tg A4 A3 A2 A1 A0 0 0 0 0 0 0 0 0
- ; ADD V,U ; U= 0 /C6 Tg A4 A3 A2 A1 A0 0 0 C5 C4 C3 C2 C1 C0
- ; ------------------------------;
- ; RC5_ComputeC6bit ;
- ; ------------------------------;
- BIT #0x4000,V ; test /C6
- 0= IF BIS.B #0x40,U ; set C6 bit
- THEN ;
- ; ------------------------------;
- ; RC5_CommandByteIsDone: ; U= 0 0 0 0 0 0 0 0 0 C6 C5 C4 C3 C2 C1 C0
- ; ------------------------------;
- SWPB U ; 1
- MOV U,&I2CS_OUT ; 3 count=low byte, Command=high byte
- ; ------------------------------;
- ; SUB #2,PSP
- ; MOV TOS,0(PSP)
- ; MOV.B U,TOS
- ; ASM>FORTH
- ; SPACE ." 0x" HEX 2 U.R
- ; FORTH>ASM
- ; ------------------------------;
- RETI ;
- ENDCODE ;
- ; ------------------------------;
- ; P1.7 - J5.14 UCB0 SCL/SOMI ---> SCL I2C MASTER/SLAVE
- ; P1.6 - J5.15 UCB0 SDA/SIMO <--> SDA I2C MASTER/SLAVE
- ; **************************************;
- CODE I2C_S ; <== eUSCIB0 interrupt vector
- ; **************************************;
- BIC #0xF8,0(RSP) ; CPU on, GIE off in oldSR
- ; --------------------------------------;
- MOV #I2CS_OUT,W ; W = buffer output address -1
- MOV #MY_I2CADR,X ; X = buffer input address -1
- CMP.B @X,&0x65C ; UCBR0ADDRX = own address ?
- MOV #0,&0x66C ; write UCB0IFG to clear all int flags
- = IF ;
- BIS.B #0x20,&0x640 ; UCB0CTLW0(UCTXACK) : software Ack address
- BIT.B #0x10,&0X640 ; test UCB0CTLW0(UCTR) R/W bit
- 0= IF ; I2C_Master Write ?
- ; ------------------------------;
- ; slave receive datas ; yes
- ; ------------------------------;
- MOV X,Y ; Y = input buffer ptr
- BEGIN ;
- ; --------------------------;
- ; slave receive one byte ;
- ; --------------------------;
- BEGIN ;
- BIT.B #0x8C,&0x66C ; UCB0IFG(CLTO,STP,STT,) = 1 ? ( SCL low timeout,STOP, START)
- 0<> IF ;
- ; ------------------;
- ; master stoP/rStart;
- ; ------------------;
- SUB X,Y ; (ptr-org) = count
- MOV.B Y,0(W) ; store length in first byte of buffer output
- ; ------------------;
- RETI ;
- ; ------------------;
- THEN ; if not (stop, restart, CLTO)
- BIT.B #0x01,&0x66C ; UCB0IFG(RX0) = 1 ?
- <> UNTIL ;
- ADD #1,Y ; reserve one byte for length first, then preincrement
- MOV.B &0x64C,0(Y) ; [UCB0RXBUF] = data --> +[Y]
- AGAIN ; loop for new received data if any
- THEN ; I2C_Master read
- ; ------------------------------;
- ; slave transmit datas ; no
- ; ------------------------------;
- MOV W,Y ; Y = output buffer ptr
- ADD #1,Y ; first reserve one byte for length
- BEGIN ;
- ; --------------------------;
- ; slave send byte ;
- ; --------------------------;
- MOV.B @Y+,&0x64E ; [Y]+ --> UCB0TXBUF
- BEGIN ;
- BIT.B #0x8C,&0x66C ; UCB0IFG(CLTO,STP,STT,) = 1 ? ( SCL low timeout,STOP, START)
- 0<> IF ;
- ; ------------------;
- ; master stop/rStart;
- ; ------------------;
- SUB W,Y ; BUF (ptr-org)= count+1
- SUB.B #1,Y ; Y = count
- MOV.B Y,0(W) ; store length in buf_out(0)
- ; ------------------;
- RETI ;
- ; ------------------;
- THEN ;
- BIT.B #0x02,&0x66C ; UCB0IFG(TX0) = 1 ?
- <> UNTIL ;
- AGAIN ;
- THEN ; if bad I2C address
- BIC.B #0x20,&0x640 ; UCB0CTLW0(UCTXACK) : send Nack address
- RETI ;
- ENDCODE
- ; --------------------------------------;
- CODE START ;
- ; --------------------------------------;
- ; init I2C_slave ;
- ; UCB0CTLW0 = 0b0000 0111 1100 0001 0x640
- ; - UCMST = 0 : I2C_Slave
- ; -- UCMODE = 0b11 = I2C
- ; _ USYNC=1 (always 1)
- ; -- UCSSEL=SMCLK (don't care in slave mode)
- ; - UCTXACK=0 not auto ACK slave address
- ; - UCTR=0 : RX (for RX address)
- ; - UCSWRST=1
- ; UCB0CTLW1 = 0b0000 0000 1101 0000 0x642
- ; - UCETXINT=0 : UCTXIFG0 set address match UCxI2COAx and TX mode
- ; -- UCCLTO=0b11 : SCL low time out = 34 ms
- ; - UCSWACK=1 : UCTXACK must be written to continue
- ; UCB0RXBUF 0x64C
- ; UCB0TXBUF 0x64E
- ; UCB0I2COA0 0x654 must be written ? enabled ?
- ; UCB0ADDRX 0x65C
- ; UCB0ADDMSK 0x65E
- ; UCB0IE = 0b0000 0000 0000 0100 0x66A
- ; - UCSTTIE : StartCond Interrupt only
- ; UCB0IFG 0x66C
- ; UCB0IV 0x66E : write it to clear all IFG
- ; ------------------------------;
- ; init I2C_slave ;
- ; ------------------------------;
- MOV #1,&0x640 ; set eUSCI_B in reset state
- BIS #0x07A0,&0x640
- BIS #0x0010,&0x642 ; UCB0CTLW1 : set software ack address
- MOV #0x040A,&0x654 ; UCB0I2COA0 : UCOAEN=1 enable with address slave
- MOV #0,&0x65E ; UCB0ADDMSK : enable address mask for all addresses i.e. software address
- BIC #1,&0x640 ; activate eUSCI_B
- MOV #0x0004,&0x66A ; UCB0IE : enable StartCond interrupt
- MOV #0b1010,&MY_I2CADR ; my slave address, without RW flag !
- ; ------------------------------;
- ; init interrupt vectors
- ; ------------------------------;
- MOV #IR_RC5,&0xFFD0 ; init P4 vector interrupt
- MOV #I2C_S,&0xFFEE ; eUSCIB0 interrupt vector
- ; ------------------------------;
- ; init PORTA (P2:P1) (complement) default I/O are input with pullup resistors
- ; ------------------------------;
- BIC.B #0xC0,&0x206 ; P1REN.76 SDA + SCL pullup/down disable
- BIS.B #0xC0,&0x20C ; P1SEL1.76 on : enable I2C I/O
- ; ------------------------------;
- ; init PORTB (P4:P3) (complement) default I/O are input with pullup resistors
- ; ------------------------------;
- BIC.B #0x01,&0x23D ; P4IFG.0 clear int flag for TSOP32236 (after IES select)
- BIS.B #0x01,&0x23B ; P4IE.0 enable interrupt for TSOP32236
- ; ------------------------------;
- ASM>FORTH
- ." Type STOP to quit RC5_to_I2C_Slave"
- LIT RECURSE IS WARM \ ; insert this starting routine between COLD and WARM...
- (WARM) ; ; ...and continue with WARM
- CODE STOP
- MOV #1,&0x640 ; set eUSCI_B in reset state
- BIC.B #0x01,&0x023B ; Clear P4IE.0 IR_RC5 interrupt from TSOP32236
- ASM>FORTH
- ['] (WARM) IS WARM \ ; reconnect RUNNING to WARM
- -1 ABORT"
- ; ; above, ABORT" followed by CRLF allows ABORT" without message...
- ; DUP HERE SWAP - DUMP ; general minidump, part 2
- FORGET I2C_S FORGET IR_RC5 ; not FORTH executable
- ECHO
- RST_HERE
- START