/sys/dev/drm2/i915/i915_reg.h
C++ Header | 3876 lines | 2935 code | 326 blank | 615 comment | 3 complexity | 3aaf1695cb25cc73496c100866da077b MD5 | raw file
Possible License(s): MPL-2.0-no-copyleft-exception, BSD-3-Clause, LGPL-2.0, LGPL-2.1, BSD-2-Clause, 0BSD, JSON, AGPL-1.0, GPL-2.0
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- /* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sub license, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial portions
- * of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
- * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
- * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
- #include <sys/cdefs.h>
- __FBSDID("$FreeBSD$");
- #ifndef _I915_REG_H_
- #define _I915_REG_H_
- #define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
- /*
- * The Bridge device's PCI config space has information about the
- * fb aperture size and the amount of pre-reserved memory.
- * This is all handled in the intel-gtt.ko module. i915.ko only
- * cares about the vga bit for the vga rbiter.
- */
- #define INTEL_GMCH_CTRL 0x52
- #define INTEL_GMCH_VGA_DISABLE (1 << 1)
- /* PCI config space */
- #define HPLLCC 0xc0 /* 855 only */
- #define GC_CLOCK_CONTROL_MASK (0xf << 0)
- #define GC_CLOCK_133_200 (0 << 0)
- #define GC_CLOCK_100_200 (1 << 0)
- #define GC_CLOCK_100_133 (2 << 0)
- #define GC_CLOCK_166_250 (3 << 0)
- #define GCFGC2 0xda
- #define GCFGC 0xf0 /* 915+ only */
- #define GC_LOW_FREQUENCY_ENABLE (1 << 7)
- #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
- #define GC_DISPLAY_CLOCK_333_MHZ (4 << 4)
- #define GC_DISPLAY_CLOCK_MASK (7 << 4)
- #define GM45_GC_RENDER_CLOCK_MASK (0xf << 0)
- #define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0)
- #define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0)
- #define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0)
- #define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0)
- #define I965_GC_RENDER_CLOCK_MASK (0xf << 0)
- #define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0)
- #define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0)
- #define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0)
- #define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0)
- #define I945_GC_RENDER_CLOCK_MASK (7 << 0)
- #define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0)
- #define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0)
- #define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0)
- #define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0)
- #define I915_GC_RENDER_CLOCK_MASK (7 << 0)
- #define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0)
- #define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0)
- #define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0)
- #define LBB 0xf4
- /* Graphics reset regs */
- #define I965_GDRST 0xc0 /* PCI config register */
- #define ILK_GDSR 0x2ca4 /* MCHBAR offset */
- #define GRDOM_FULL (0<<2)
- #define GRDOM_RENDER (1<<2)
- #define GRDOM_MEDIA (3<<2)
- #define GEN6_MBCUNIT_SNPCR 0x900c /* for LLC config */
- #define GEN6_MBC_SNPCR_SHIFT 21
- #define GEN6_MBC_SNPCR_MASK (3<<21)
- #define GEN6_MBC_SNPCR_MAX (0<<21)
- #define GEN6_MBC_SNPCR_MED (1<<21)
- #define GEN6_MBC_SNPCR_LOW (2<<21)
- #define GEN6_MBC_SNPCR_MIN (3<<21) /* only 1/16th of the cache is shared */
- #define GEN6_MBCTL 0x0907c
- #define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4)
- #define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3)
- #define GEN6_MBCTL_BME_UPDATE_ENABLE (1 << 2)
- #define GEN6_MBCTL_MAE_UPDATE_ENABLE (1 << 1)
- #define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0)
- #define GEN6_GDRST 0x941c
- #define GEN6_GRDOM_FULL (1 << 0)
- #define GEN6_GRDOM_RENDER (1 << 1)
- #define GEN6_GRDOM_MEDIA (1 << 2)
- #define GEN6_GRDOM_BLT (1 << 3)
- /* PPGTT stuff */
- #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0))
- #define GEN6_PDE_VALID (1 << 0)
- #define GEN6_PDE_LARGE_PAGE (2 << 0) /* use 32kb pages */
- /* gen6+ has bit 11-4 for physical addr bit 39-32 */
- #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
- #define GEN6_PTE_VALID (1 << 0)
- #define GEN6_PTE_UNCACHED (1 << 1)
- #define GEN6_PTE_CACHE_LLC (2 << 1)
- #define GEN6_PTE_CACHE_LLC_MLC (3 << 1)
- #define GEN6_PTE_CACHE_BITS (3 << 1)
- #define GEN6_PTE_GFDT (1 << 3)
- #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
- #define RING_PP_DIR_BASE(ring) ((ring)->mmio_base+0x228)
- #define RING_PP_DIR_BASE_READ(ring) ((ring)->mmio_base+0x518)
- #define RING_PP_DIR_DCLV(ring) ((ring)->mmio_base+0x220)
- #define PP_DIR_DCLV_2G 0xffffffff
- #define GAM_ECOCHK 0x4090
- #define ECOCHK_SNB_BIT (1<<10)
- #define ECOCHK_PPGTT_CACHE64B (0x3<<3)
- #define ECOCHK_PPGTT_CACHE4B (0x0<<3)
- /* VGA stuff */
- #define VGA_ST01_MDA 0x3ba
- #define VGA_ST01_CGA 0x3da
- #define VGA_MSR_WRITE 0x3c2
- #define VGA_MSR_READ 0x3cc
- #define VGA_MSR_MEM_EN (1<<1)
- #define VGA_MSR_CGA_MODE (1<<0)
- #define VGA_SR_INDEX 0x3c4
- #define VGA_SR_DATA 0x3c5
- #define VGA_AR_INDEX 0x3c0
- #define VGA_AR_VID_EN (1<<5)
- #define VGA_AR_DATA_WRITE 0x3c0
- #define VGA_AR_DATA_READ 0x3c1
- #define VGA_GR_INDEX 0x3ce
- #define VGA_GR_DATA 0x3cf
- /* GR05 */
- #define VGA_GR_MEM_READ_MODE_SHIFT 3
- #define VGA_GR_MEM_READ_MODE_PLANE 1
- /* GR06 */
- #define VGA_GR_MEM_MODE_MASK 0xc
- #define VGA_GR_MEM_MODE_SHIFT 2
- #define VGA_GR_MEM_A0000_AFFFF 0
- #define VGA_GR_MEM_A0000_BFFFF 1
- #define VGA_GR_MEM_B0000_B7FFF 2
- #define VGA_GR_MEM_B0000_BFFFF 3
- #define VGA_DACMASK 0x3c6
- #define VGA_DACRX 0x3c7
- #define VGA_DACWX 0x3c8
- #define VGA_DACDATA 0x3c9
- #define VGA_CR_INDEX_MDA 0x3b4
- #define VGA_CR_DATA_MDA 0x3b5
- #define VGA_CR_INDEX_CGA 0x3d4
- #define VGA_CR_DATA_CGA 0x3d5
- /*
- * Memory interface instructions used by the kernel
- */
- #define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
- #define MI_NOOP MI_INSTR(0, 0)
- #define MI_USER_INTERRUPT MI_INSTR(0x02, 0)
- #define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0)
- #define MI_WAIT_FOR_OVERLAY_FLIP (1<<16)
- #define MI_WAIT_FOR_PLANE_B_FLIP (1<<6)
- #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
- #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
- #define MI_FLUSH MI_INSTR(0x04, 0)
- #define MI_READ_FLUSH (1 << 0)
- #define MI_EXE_FLUSH (1 << 1)
- #define MI_NO_WRITE_FLUSH (1 << 2)
- #define MI_SCENE_COUNT (1 << 3) /* just increment scene count */
- #define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */
- #define MI_INVALIDATE_ISP (1 << 5) /* invalidate indirect state pointers */
- #define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0)
- #define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0)
- #define MI_SUSPEND_FLUSH_EN (1<<0)
- #define MI_REPORT_HEAD MI_INSTR(0x07, 0)
- #define MI_OVERLAY_FLIP MI_INSTR(0x11, 0)
- #define MI_OVERLAY_CONTINUE (0x0<<21)
- #define MI_OVERLAY_ON (0x1<<21)
- #define MI_OVERLAY_OFF (0x2<<21)
- #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
- #define MI_DISPLAY_FLIP MI_INSTR(0x14, 2)
- #define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1)
- #define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20)
- #define MI_SET_CONTEXT MI_INSTR(0x18, 0)
- #define MI_MM_SPACE_GTT (1<<8)
- #define MI_MM_SPACE_PHYSICAL (0<<8)
- #define MI_SAVE_EXT_STATE_EN (1<<3)
- #define MI_RESTORE_EXT_STATE_EN (1<<2)
- #define MI_FORCE_RESTORE (1<<1)
- #define MI_RESTORE_INHIBIT (1<<0)
- #define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1)
- #define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */
- #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1)
- #define MI_STORE_DWORD_INDEX_SHIFT 2
- /* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM:
- * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw
- * simply ignores the register load under certain conditions.
- * - One can actually load arbitrary many arbitrary registers: Simply issue x
- * address/value pairs. Don't overdue it, though, x <= 2^4 must hold!
- */
- #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*x-1)
- #define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */
- #define MI_INVALIDATE_TLB (1<<18)
- #define MI_INVALIDATE_BSD (1<<7)
- #define MI_BATCH_BUFFER MI_INSTR(0x30, 1)
- #define MI_BATCH_NON_SECURE (1)
- #define MI_BATCH_NON_SECURE_I965 (1<<8)
- #define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0)
- #define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6+ */
- #define MI_SEMAPHORE_GLOBAL_GTT (1<<22)
- #define MI_SEMAPHORE_UPDATE (1<<21)
- #define MI_SEMAPHORE_COMPARE (1<<20)
- #define MI_SEMAPHORE_REGISTER (1<<18)
- #define MI_SEMAPHORE_SYNC_RV (2<<16)
- #define MI_SEMAPHORE_SYNC_RB (0<<16)
- #define MI_SEMAPHORE_SYNC_VR (0<<16)
- #define MI_SEMAPHORE_SYNC_VB (2<<16)
- #define MI_SEMAPHORE_SYNC_BR (2<<16)
- #define MI_SEMAPHORE_SYNC_BV (0<<16)
- #define MI_SEMAPHORE_SYNC_INVALID (1<<0)
- /*
- * 3D instructions used by the kernel
- */
- #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
- #define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24))
- #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
- #define SC_UPDATE_SCISSOR (0x1<<1)
- #define SC_ENABLE_MASK (0x1<<0)
- #define SC_ENABLE (0x1<<0)
- #define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16))
- #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
- #define SCI_YMIN_MASK (0xffff<<16)
- #define SCI_XMIN_MASK (0xffff<<0)
- #define SCI_YMAX_MASK (0xffff<<16)
- #define SCI_XMAX_MASK (0xffff<<0)
- #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))
- #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
- #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
- #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
- #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4)
- #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
- #define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
- #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
- #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)
- #define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4)
- #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)
- #define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5)
- #define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21)
- #define XY_SRC_COPY_BLT_WRITE_RGB (1<<20)
- #define BLT_DEPTH_8 (0<<24)
- #define BLT_DEPTH_16_565 (1<<24)
- #define BLT_DEPTH_16_1555 (2<<24)
- #define BLT_DEPTH_32 (3<<24)
- #define BLT_ROP_GXCOPY (0xcc<<16)
- #define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */
- #define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */
- #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
- #define ASYNC_FLIP (1<<22)
- #define DISPLAY_PLANE_A (0<<20)
- #define DISPLAY_PLANE_B (1<<20)
- #define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2))
- #define PIPE_CONTROL_CS_STALL (1<<20)
- #define PIPE_CONTROL_QW_WRITE (1<<14)
- #define PIPE_CONTROL_DEPTH_STALL (1<<13)
- #define PIPE_CONTROL_WRITE_FLUSH (1<<12)
- #define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12) /* gen6+ */
- #define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11) /* MBZ on Ironlake */
- #define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) /* GM45+ only */
- #define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9)
- #define PIPE_CONTROL_NOTIFY (1<<8)
- #define PIPE_CONTROL_VF_CACHE_INVALIDATE (1<<4)
- #define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1<<3)
- #define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1<<2)
- #define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1)
- #define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0)
- #define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
- /*
- * Reset registers
- */
- #define DEBUG_RESET_I830 0x6070
- #define DEBUG_RESET_FULL (1<<7)
- #define DEBUG_RESET_RENDER (1<<8)
- #define DEBUG_RESET_DISPLAY (1<<9)
- /*
- * Fence registers
- */
- #define FENCE_REG_830_0 0x2000
- #define FENCE_REG_945_8 0x3000
- #define I830_FENCE_START_MASK 0x07f80000
- #define I830_FENCE_TILING_Y_SHIFT 12
- #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8)
- #define I830_FENCE_PITCH_SHIFT 4
- #define I830_FENCE_REG_VALID (1<<0)
- #define I915_FENCE_MAX_PITCH_VAL 4
- #define I830_FENCE_MAX_PITCH_VAL 6
- #define I830_FENCE_MAX_SIZE_VAL (1<<8)
- #define I915_FENCE_START_MASK 0x0ff00000
- #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8)
- #define FENCE_REG_965_0 0x03000
- #define I965_FENCE_PITCH_SHIFT 2
- #define I965_FENCE_TILING_Y_SHIFT 1
- #define I965_FENCE_REG_VALID (1<<0)
- #define I965_FENCE_MAX_PITCH_VAL 0x0400
- #define FENCE_REG_SANDYBRIDGE_0 0x100000
- #define SANDYBRIDGE_FENCE_PITCH_SHIFT 32
- /* control register for cpu gtt access */
- #define TILECTL 0x101000
- #define TILECTL_SWZCTL (1 << 0)
- #define TILECTL_TLB_PREFETCH_DIS (1 << 2)
- #define TILECTL_BACKSNOOP_DIS (1 << 3)
- /*
- * Instruction and interrupt control regs
- */
- #define PGTBL_ER 0x02024
- #define RENDER_RING_BASE 0x02000
- #define BSD_RING_BASE 0x04000
- #define GEN6_BSD_RING_BASE 0x12000
- #define BLT_RING_BASE 0x22000
- #define RING_TAIL(base) ((base)+0x30)
- #define RING_HEAD(base) ((base)+0x34)
- #define RING_START(base) ((base)+0x38)
- #define RING_CTL(base) ((base)+0x3c)
- #define RING_SYNC_0(base) ((base)+0x40)
- #define RING_SYNC_1(base) ((base)+0x44)
- #define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE))
- #define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE))
- #define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE))
- #define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE))
- #define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE))
- #define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE))
- #define RING_MAX_IDLE(base) ((base)+0x54)
- #define RING_HWS_PGA(base) ((base)+0x80)
- #define RING_HWS_PGA_GEN6(base) ((base)+0x2080)
- #define ARB_MODE 0x04030
- #define ARB_MODE_SWIZZLE_SNB (1<<4)
- #define ARB_MODE_SWIZZLE_IVB (1<<5)
- #define ARB_MODE_ENABLE(x) GFX_MODE_ENABLE(x)
- #define ARB_MODE_DISABLE(x) GFX_MODE_DISABLE(x)
- #define RENDER_HWS_PGA_GEN7 (0x04080)
- #define RING_FAULT_REG(ring) (0x4094 + 0x100*(ring)->id)
- #define DONE_REG 0x40b0
- #define BSD_HWS_PGA_GEN7 (0x04180)
- #define BLT_HWS_PGA_GEN7 (0x04280)
- #define RING_ACTHD(base) ((base)+0x74)
- #define RING_NOPID(base) ((base)+0x94)
- #define RING_IMR(base) ((base)+0xa8)
- #define TAIL_ADDR 0x001FFFF8
- #define HEAD_WRAP_COUNT 0xFFE00000
- #define HEAD_WRAP_ONE 0x00200000
- #define HEAD_ADDR 0x001FFFFC
- #define RING_NR_PAGES 0x001FF000
- #define RING_REPORT_MASK 0x00000006
- #define RING_REPORT_64K 0x00000002
- #define RING_REPORT_128K 0x00000004
- #define RING_NO_REPORT 0x00000000
- #define RING_VALID_MASK 0x00000001
- #define RING_VALID 0x00000001
- #define RING_INVALID 0x00000000
- #define RING_WAIT_I8XX (1<<0) /* gen2, PRBx_HEAD */
- #define RING_WAIT (1<<11) /* gen3+, PRBx_CTL */
- #define RING_WAIT_SEMAPHORE (1<<10) /* gen6+ */
- #if 0
- #define PRB0_TAIL 0x02030
- #define PRB0_HEAD 0x02034
- #define PRB0_START 0x02038
- #define PRB0_CTL 0x0203c
- #define PRB1_TAIL 0x02040 /* 915+ only */
- #define PRB1_HEAD 0x02044 /* 915+ only */
- #define PRB1_START 0x02048 /* 915+ only */
- #define PRB1_CTL 0x0204c /* 915+ only */
- #endif
- #define IPEIR_I965 0x02064
- #define IPEHR_I965 0x02068
- #define INSTDONE_I965 0x0206c
- #define RING_IPEIR(base) ((base)+0x64)
- #define RING_IPEHR(base) ((base)+0x68)
- #define RING_INSTDONE(base) ((base)+0x6c)
- #define RING_INSTPS(base) ((base)+0x70)
- #define RING_DMA_FADD(base) ((base)+0x78)
- #define RING_INSTPM(base) ((base)+0xc0)
- #define INSTPS 0x02070 /* 965+ only */
- #define INSTDONE1 0x0207c /* 965+ only */
- #define ACTHD_I965 0x02074
- #define HWS_PGA 0x02080
- #define HWS_ADDRESS_MASK 0xfffff000
- #define HWS_START_ADDRESS_SHIFT 4
- #define PWRCTXA 0x2088 /* 965GM+ only */
- #define PWRCTX_EN (1<<0)
- #define IPEIR 0x02088
- #define IPEHR 0x0208c
- #define INSTDONE 0x02090
- #define NOPID 0x02094
- #define HWSTAM 0x02098
- #define ERROR_GEN6 0x040a0
- /* GM45+ chicken bits -- debug workaround bits that may be required
- * for various sorts of correct behavior. The top 16 bits of each are
- * the enables for writing to the corresponding low bit.
- */
- #define _3D_CHICKEN 0x02084
- #define _3D_CHICKEN2 0x0208c
- /* Disables pipelining of read flushes past the SF-WIZ interface.
- * Required on all Ironlake steppings according to the B-Spec, but the
- * particular danger of not doing so is not specified.
- */
- # define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14)
- #define _3D_CHICKEN3 0x02090
- #define MI_MODE 0x0209c
- # define VS_TIMER_DISPATCH (1 << 6)
- # define MI_FLUSH_ENABLE (1 << 12)
- #define GFX_MODE 0x02520
- #define GFX_MODE_GEN7 0x0229c
- #define RING_MODE_GEN7(ring) ((ring)->mmio_base+0x29c)
- #define GFX_RUN_LIST_ENABLE (1<<15)
- #define GFX_TLB_INVALIDATE_ALWAYS (1<<13)
- #define GFX_SURFACE_FAULT_ENABLE (1<<12)
- #define GFX_REPLAY_MODE (1<<11)
- #define GFX_PSMI_GRANULARITY (1<<10)
- #define GFX_PPGTT_ENABLE (1<<9)
- #define GFX_MODE_ENABLE(bit) (((bit) << 16) | (bit))
- #define GFX_MODE_DISABLE(bit) (((bit) << 16) | (0))
- #define SCPD0 0x0209c /* 915+ only */
- #define IER 0x020a0
- #define IIR 0x020a4
- #define IMR 0x020a8
- #define ISR 0x020ac
- #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18)
- #define I915_DISPLAY_PORT_INTERRUPT (1<<17)
- #define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15)
- #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */
- #define I915_HWB_OOM_INTERRUPT (1<<13)
- #define I915_SYNC_STATUS_INTERRUPT (1<<12)
- #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11)
- #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10)
- #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9)
- #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8)
- #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7)
- #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6)
- #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5)
- #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4)
- #define I915_DEBUG_INTERRUPT (1<<2)
- #define I915_USER_INTERRUPT (1<<1)
- #define I915_ASLE_INTERRUPT (1<<0)
- #define I915_BSD_USER_INTERRUPT (1<<25)
- #define EIR 0x020b0
- #define EMR 0x020b4
- #define ESR 0x020b8
- #define GM45_ERROR_PAGE_TABLE (1<<5)
- #define GM45_ERROR_MEM_PRIV (1<<4)
- #define I915_ERROR_PAGE_TABLE (1<<4)
- #define GM45_ERROR_CP_PRIV (1<<3)
- #define I915_ERROR_MEMORY_REFRESH (1<<1)
- #define I915_ERROR_INSTRUCTION (1<<0)
- #define INSTPM 0x020c0
- #define INSTPM_SELF_EN (1<<12) /* 915GM only */
- #define INSTPM_AGPBUSY_DIS (1<<11) /* gen3: when disabled, pending interrupts
- will not assert AGPBUSY# and will only
- be delivered when out of C3. */
- #define INSTPM_FORCE_ORDERING (1<<7) /* GEN6+ */
- #define ACTHD 0x020c8
- #define FW_BLC 0x020d8
- #define FW_BLC2 0x020dc
- #define FW_BLC_SELF 0x020e0 /* 915+ only */
- #define FW_BLC_SELF_EN_MASK (1<<31)
- #define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */
- #define FW_BLC_SELF_EN (1<<15) /* 945 only */
- #define MM_BURST_LENGTH 0x00700000
- #define MM_FIFO_WATERMARK 0x0001F000
- #define LM_BURST_LENGTH 0x00000700
- #define LM_FIFO_WATERMARK 0x0000001F
- #define MI_ARB_STATE 0x020e4 /* 915+ only */
- #define MI_ARB_MASK_SHIFT 16 /* shift for enable bits */
- /* Make render/texture TLB fetches lower priorty than associated data
- * fetches. This is not turned on by default
- */
- #define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15)
- /* Isoch request wait on GTT enable (Display A/B/C streams).
- * Make isoch requests stall on the TLB update. May cause
- * display underruns (test mode only)
- */
- #define MI_ARB_ISOCH_WAIT_GTT (1 << 14)
- /* Block grant count for isoch requests when block count is
- * set to a finite value.
- */
- #define MI_ARB_BLOCK_GRANT_MASK (3 << 12)
- #define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */
- #define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */
- #define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */
- #define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */
- /* Enable render writes to complete in C2/C3/C4 power states.
- * If this isn't enabled, render writes are prevented in low
- * power states. That seems bad to me.
- */
- #define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11)
- /* This acknowledges an async flip immediately instead
- * of waiting for 2TLB fetches.
- */
- #define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10)
- /* Enables non-sequential data reads through arbiter
- */
- #define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9)
- /* Disable FSB snooping of cacheable write cycles from binner/render
- * command stream
- */
- #define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8)
- /* Arbiter time slice for non-isoch streams */
- #define MI_ARB_TIME_SLICE_MASK (7 << 5)
- #define MI_ARB_TIME_SLICE_1 (0 << 5)
- #define MI_ARB_TIME_SLICE_2 (1 << 5)
- #define MI_ARB_TIME_SLICE_4 (2 << 5)
- #define MI_ARB_TIME_SLICE_6 (3 << 5)
- #define MI_ARB_TIME_SLICE_8 (4 << 5)
- #define MI_ARB_TIME_SLICE_10 (5 << 5)
- #define MI_ARB_TIME_SLICE_14 (6 << 5)
- #define MI_ARB_TIME_SLICE_16 (7 << 5)
- /* Low priority grace period page size */
- #define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */
- #define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4)
- /* Disable display A/B trickle feed */
- #define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2)
- /* Set display plane priority */
- #define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */
- #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */
- #define CACHE_MODE_0 0x02120 /* 915+ only */
- #define CM0_MASK_SHIFT 16
- #define CM0_IZ_OPT_DISABLE (1<<6)
- #define CM0_ZR_OPT_DISABLE (1<<5)
- #define CM0_STC_EVICT_DISABLE_LRA_SNB (1<<5)
- #define CM0_DEPTH_EVICT_DISABLE (1<<4)
- #define CM0_COLOR_EVICT_DISABLE (1<<3)
- #define CM0_DEPTH_WRITE_DISABLE (1<<1)
- #define CM0_RC_OP_FLUSH_DISABLE (1<<0)
- #define BB_ADDR 0x02140 /* 8 bytes */
- #define GFX_FLSH_CNTL 0x02170 /* 915+ only */
- #define ECOSKPD 0x021d0
- #define ECO_GATING_CX_ONLY (1<<3)
- #define ECO_FLIP_DONE (1<<0)
- /* GEN6 interrupt control */
- #define GEN6_RENDER_HWSTAM 0x2098
- #define GEN6_RENDER_IMR 0x20a8
- #define GEN6_RENDER_CONTEXT_SWITCH_INTERRUPT (1 << 8)
- #define GEN6_RENDER_PPGTT_PAGE_FAULT (1 << 7)
- #define GEN6_RENDER_TIMEOUT_COUNTER_EXPIRED (1 << 6)
- #define GEN6_RENDER_L3_PARITY_ERROR (1 << 5)
- #define GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 4)
- #define GEN6_RENDER_COMMAND_PARSER_MASTER_ERROR (1 << 3)
- #define GEN6_RENDER_SYNC_STATUS (1 << 2)
- #define GEN6_RENDER_DEBUG_INTERRUPT (1 << 1)
- #define GEN6_RENDER_USER_INTERRUPT (1 << 0)
- #define GEN6_BLITTER_HWSTAM 0x22098
- #define GEN6_BLITTER_IMR 0x220a8
- #define GEN6_BLITTER_MI_FLUSH_DW_NOTIFY_INTERRUPT (1 << 26)
- #define GEN6_BLITTER_COMMAND_PARSER_MASTER_ERROR (1 << 25)
- #define GEN6_BLITTER_SYNC_STATUS (1 << 24)
- #define GEN6_BLITTER_USER_INTERRUPT (1 << 22)
- #define GEN6_BLITTER_ECOSKPD 0x221d0
- #define GEN6_BLITTER_LOCK_SHIFT 16
- #define GEN6_BLITTER_FBC_NOTIFY (1<<3)
- #define GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050
- #define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK (1 << 16)
- #define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE (1 << 0)
- #define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE 0
- #define GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR (1 << 3)
- #define GEN6_BSD_HWSTAM 0x12098
- #define GEN6_BSD_IMR 0x120a8
- #define GEN6_BSD_USER_INTERRUPT (1 << 12)
- #define GEN6_BSD_RNCID 0x12198
- /*
- * Framebuffer compression (915+ only)
- */
- #define FBC_CFB_BASE 0x03200 /* 4k page aligned */
- #define FBC_LL_BASE 0x03204 /* 4k page aligned */
- #define FBC_CONTROL 0x03208
- #define FBC_CTL_EN (1<<31)
- #define FBC_CTL_PERIODIC (1<<30)
- #define FBC_CTL_INTERVAL_SHIFT (16)
- #define FBC_CTL_UNCOMPRESSIBLE (1<<14)
- #define FBC_CTL_C3_IDLE (1<<13)
- #define FBC_CTL_STRIDE_SHIFT (5)
- #define FBC_CTL_FENCENO (1<<0)
- #define FBC_COMMAND 0x0320c
- #define FBC_CMD_COMPRESS (1<<0)
- #define FBC_STATUS 0x03210
- #define FBC_STAT_COMPRESSING (1<<31)
- #define FBC_STAT_COMPRESSED (1<<30)
- #define FBC_STAT_MODIFIED (1<<29)
- #define FBC_STAT_CURRENT_LINE (1<<0)
- #define FBC_CONTROL2 0x03214
- #define FBC_CTL_FENCE_DBL (0<<4)
- #define FBC_CTL_IDLE_IMM (0<<2)
- #define FBC_CTL_IDLE_FULL (1<<2)
- #define FBC_CTL_IDLE_LINE (2<<2)
- #define FBC_CTL_IDLE_DEBUG (3<<2)
- #define FBC_CTL_CPU_FENCE (1<<1)
- #define FBC_CTL_PLANEA (0<<0)
- #define FBC_CTL_PLANEB (1<<0)
- #define FBC_FENCE_OFF 0x0321b
- #define FBC_TAG 0x03300
- #define FBC_LL_SIZE (1536)
- /* Framebuffer compression for GM45+ */
- #define DPFC_CB_BASE 0x3200
- #define DPFC_CONTROL 0x3208
- #define DPFC_CTL_EN (1<<31)
- #define DPFC_CTL_PLANEA (0<<30)
- #define DPFC_CTL_PLANEB (1<<30)
- #define DPFC_CTL_FENCE_EN (1<<29)
- #define DPFC_CTL_PERSISTENT_MODE (1<<25)
- #define DPFC_SR_EN (1<<10)
- #define DPFC_CTL_LIMIT_1X (0<<6)
- #define DPFC_CTL_LIMIT_2X (1<<6)
- #define DPFC_CTL_LIMIT_4X (2<<6)
- #define DPFC_RECOMP_CTL 0x320c
- #define DPFC_RECOMP_STALL_EN (1<<27)
- #define DPFC_RECOMP_STALL_WM_SHIFT (16)
- #define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000)
- #define DPFC_RECOMP_TIMER_COUNT_SHIFT (0)
- #define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f)
- #define DPFC_STATUS 0x3210
- #define DPFC_INVAL_SEG_SHIFT (16)
- #define DPFC_INVAL_SEG_MASK (0x07ff0000)
- #define DPFC_COMP_SEG_SHIFT (0)
- #define DPFC_COMP_SEG_MASK (0x000003ff)
- #define DPFC_STATUS2 0x3214
- #define DPFC_FENCE_YOFF 0x3218
- #define DPFC_CHICKEN 0x3224
- #define DPFC_HT_MODIFY (1<<31)
- /* Framebuffer compression for Ironlake */
- #define ILK_DPFC_CB_BASE 0x43200
- #define ILK_DPFC_CONTROL 0x43208
- /* The bit 28-8 is reserved */
- #define DPFC_RESERVED (0x1FFFFF00)
- #define ILK_DPFC_RECOMP_CTL 0x4320c
- #define ILK_DPFC_STATUS 0x43210
- #define ILK_DPFC_FENCE_YOFF 0x43218
- #define ILK_DPFC_CHICKEN 0x43224
- #define ILK_FBC_RT_BASE 0x2128
- #define ILK_FBC_RT_VALID (1<<0)
- #define ILK_DISPLAY_CHICKEN1 0x42000
- #define ILK_FBCQ_DIS (1<<22)
- #define ILK_PABSTRETCH_DIS (1<<21)
- /*
- * Framebuffer compression for Sandybridge
- *
- * The following two registers are of type GTTMMADR
- */
- #define SNB_DPFC_CTL_SA 0x100100
- #define SNB_CPU_FENCE_ENABLE (1<<29)
- #define DPFC_CPU_FENCE_OFFSET 0x100104
- /*
- * GPIO regs
- */
- #define GPIOA 0x5010
- #define GPIOB 0x5014
- #define GPIOC 0x5018
- #define GPIOD 0x501c
- #define GPIOE 0x5020
- #define GPIOF 0x5024
- #define GPIOG 0x5028
- #define GPIOH 0x502c
- # define GPIO_CLOCK_DIR_MASK (1 << 0)
- # define GPIO_CLOCK_DIR_IN (0 << 1)
- # define GPIO_CLOCK_DIR_OUT (1 << 1)
- # define GPIO_CLOCK_VAL_MASK (1 << 2)
- # define GPIO_CLOCK_VAL_OUT (1 << 3)
- # define GPIO_CLOCK_VAL_IN (1 << 4)
- # define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
- # define GPIO_DATA_DIR_MASK (1 << 8)
- # define GPIO_DATA_DIR_IN (0 << 9)
- # define GPIO_DATA_DIR_OUT (1 << 9)
- # define GPIO_DATA_VAL_MASK (1 << 10)
- # define GPIO_DATA_VAL_OUT (1 << 11)
- # define GPIO_DATA_VAL_IN (1 << 12)
- # define GPIO_DATA_PULLUP_DISABLE (1 << 13)
- #define GMBUS0 0x5100 /* clock/port select */
- #define GMBUS_RATE_100KHZ (0<<8)
- #define GMBUS_RATE_50KHZ (1<<8)
- #define GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */
- #define GMBUS_RATE_1MHZ (3<<8) /* reserved on Pineview */
- #define GMBUS_HOLD_EXT (1<<7) /* 300ns hold time, rsvd on Pineview */
- #define GMBUS_PORT_DISABLED 0
- #define GMBUS_PORT_SSC 1
- #define GMBUS_PORT_VGADDC 2
- #define GMBUS_PORT_PANEL 3
- #define GMBUS_PORT_DPC 4 /* HDMIC */
- #define GMBUS_PORT_DPB 5 /* SDVO, HDMIB */
- /* 6 reserved */
- #define GMBUS_PORT_DPD 7 /* HDMID */
- #define GMBUS_NUM_PORTS 8
- #define GMBUS1 0x5104 /* command/status */
- #define GMBUS_SW_CLR_INT (1<<31)
- #define GMBUS_SW_RDY (1<<30)
- #define GMBUS_ENT (1<<29) /* enable timeout */
- #define GMBUS_CYCLE_NONE (0<<25)
- #define GMBUS_CYCLE_WAIT (1<<25)
- #define GMBUS_CYCLE_INDEX (2<<25)
- #define GMBUS_CYCLE_STOP (4<<25)
- #define GMBUS_BYTE_COUNT_SHIFT 16
- #define GMBUS_SLAVE_INDEX_SHIFT 8
- #define GMBUS_SLAVE_ADDR_SHIFT 1
- #define GMBUS_SLAVE_READ (1<<0)
- #define GMBUS_SLAVE_WRITE (0<<0)
- #define GMBUS2 0x5108 /* status */
- #define GMBUS_INUSE (1<<15)
- #define GMBUS_HW_WAIT_PHASE (1<<14)
- #define GMBUS_STALL_TIMEOUT (1<<13)
- #define GMBUS_INT (1<<12)
- #define GMBUS_HW_RDY (1<<11)
- #define GMBUS_SATOER (1<<10)
- #define GMBUS_ACTIVE (1<<9)
- #define GMBUS3 0x510c /* data buffer bytes 3-0 */
- #define GMBUS4 0x5110 /* interrupt mask (Pineview+) */
- #define GMBUS_SLAVE_TIMEOUT_EN (1<<4)
- #define GMBUS_NAK_EN (1<<3)
- #define GMBUS_IDLE_EN (1<<2)
- #define GMBUS_HW_WAIT_EN (1<<1)
- #define GMBUS_HW_RDY_EN (1<<0)
- #define GMBUS5 0x5120 /* byte index */
- #define GMBUS_2BYTE_INDEX_EN (1<<31)
- /*
- * Clock control & power management
- */
- #define VGA0 0x6000
- #define VGA1 0x6004
- #define VGA_PD 0x6010
- #define VGA0_PD_P2_DIV_4 (1 << 7)
- #define VGA0_PD_P1_DIV_2 (1 << 5)
- #define VGA0_PD_P1_SHIFT 0
- #define VGA0_PD_P1_MASK (0x1f << 0)
- #define VGA1_PD_P2_DIV_4 (1 << 15)
- #define VGA1_PD_P1_DIV_2 (1 << 13)
- #define VGA1_PD_P1_SHIFT 8
- #define VGA1_PD_P1_MASK (0x1f << 8)
- #define _DPLL_A 0x06014
- #define _DPLL_B 0x06018
- #define DPLL(pipe) _PIPE(pipe, _DPLL_A, _DPLL_B)
- #define DPLL_VCO_ENABLE (1 << 31)
- #define DPLL_DVO_HIGH_SPEED (1 << 30)
- #define DPLL_SYNCLOCK_ENABLE (1 << 29)
- #define DPLL_VGA_MODE_DIS (1 << 28)
- #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
- #define DPLLB_MODE_LVDS (2 << 26) /* i915 */
- #define DPLL_MODE_MASK (3 << 26)
- #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
- #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
- #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
- #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
- #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
- #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
- #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */
- #define SRX_INDEX 0x3c4
- #define SRX_DATA 0x3c5
- #define SR01 1
- #define SR01_SCREEN_OFF (1<<5)
- #define PPCR 0x61204
- #define PPCR_ON (1<<0)
- #define DVOB 0x61140
- #define DVOB_ON (1<<31)
- #define DVOC 0x61160
- #define DVOC_ON (1<<31)
- #define LVDS 0x61180
- #define LVDS_ON (1<<31)
- /* Scratch pad debug 0 reg:
- */
- #define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
- /*
- * The i830 generation, in LVDS mode, defines P1 as the bit number set within
- * this field (only one bit may be set).
- */
- #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
- #define DPLL_FPA01_P1_POST_DIV_SHIFT 16
- #define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15
- /* i830, required in DVO non-gang */
- #define PLL_P2_DIVIDE_BY_4 (1 << 23)
- #define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
- #define PLL_REF_INPUT_DREFCLK (0 << 13)
- #define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
- #define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */
- #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
- #define PLL_REF_INPUT_MASK (3 << 13)
- #define PLL_LOAD_PULSE_PHASE_SHIFT 9
- /* Ironlake */
- # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9
- # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9)
- # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1) << 9)
- # define DPLL_FPA1_P1_POST_DIV_SHIFT 0
- # define DPLL_FPA1_P1_POST_DIV_MASK 0xff
- /*
- * Parallel to Serial Load Pulse phase selection.
- * Selects the phase for the 10X DPLL clock for the PCIe
- * digital display port. The range is 4 to 13; 10 or more
- * is just a flip delay. The default is 6
- */
- #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
- #define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
- /*
- * SDVO multiplier for 945G/GM. Not used on 965.
- */
- #define SDVO_MULTIPLIER_MASK 0x000000ff
- #define SDVO_MULTIPLIER_SHIFT_HIRES 4
- #define SDVO_MULTIPLIER_SHIFT_VGA 0
- #define _DPLL_A_MD 0x0601c /* 965+ only */
- /*
- * UDI pixel divider, controlling how many pixels are stuffed into a packet.
- *
- * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
- */
- #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
- #define DPLL_MD_UDI_DIVIDER_SHIFT 24
- /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
- #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
- #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
- /*
- * SDVO/UDI pixel multiplier.
- *
- * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
- * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
- * modes, the bus rate would be below the limits, so SDVO allows for stuffing
- * dummy bytes in the datastream at an increased clock rate, with both sides of
- * the link knowing how many bytes are fill.
- *
- * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
- * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
- * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
- * through an SDVO command.
- *
- * This register field has values of multiplication factor minus 1, with
- * a maximum multiplier of 5 for SDVO.
- */
- #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
- #define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
- /*
- * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
- * This best be set to the default value (3) or the CRT won't work. No,
- * I don't entirely understand what this does...
- */
- #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
- #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
- #define _DPLL_B_MD 0x06020 /* 965+ only */
- #define DPLL_MD(pipe) _PIPE(pipe, _DPLL_A_MD, _DPLL_B_MD)
- #define _FPA0 0x06040
- #define _FPA1 0x06044
- #define _FPB0 0x06048
- #define _FPB1 0x0604c
- #define FP0(pipe) _PIPE(pipe, _FPA0, _FPB0)
- #define FP1(pipe) _PIPE(pipe, _FPA1, _FPB1)
- #define FP_N_DIV_MASK 0x003f0000
- #define FP_N_PINEVIEW_DIV_MASK 0x00ff0000
- #define FP_N_DIV_SHIFT 16
- #define FP_M1_DIV_MASK 0x00003f00
- #define FP_M1_DIV_SHIFT 8
- #define FP_M2_DIV_MASK 0x0000003f
- #define FP_M2_PINEVIEW_DIV_MASK 0x000000ff
- #define FP_M2_DIV_SHIFT 0
- #define DPLL_TEST 0x606c
- #define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
- #define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
- #define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
- #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)
- #define DPLLB_TEST_N_BYPASS (1 << 19)
- #define DPLLB_TEST_M_BYPASS (1 << 18)
- #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)
- #define DPLLA_TEST_N_BYPASS (1 << 3)
- #define DPLLA_TEST_M_BYPASS (1 << 2)
- #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
- #define D_STATE 0x6104
- #define DSTATE_GFX_RESET_I830 (1<<6)
- #define DSTATE_PLL_D3_OFF (1<<3)
- #define DSTATE_GFX_CLOCK_GATING (1<<1)
- #define DSTATE_DOT_CLOCK_GATING (1<<0)
- #define DSPCLK_GATE_D 0x6200
- # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */
- # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */
- # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */
- # define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */
- # define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */
- # define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */
- # define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */
- # define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */
- # define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */
- # define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */
- # define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */
- # define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */
- # define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */
- # define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */
- # define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */
- # define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */
- # define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */
- # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */
- # define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */
- # define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11)
- # define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10)
- # define DCUNIT_CLOCK_GATE_DISABLE (1 << 9)
- # define DPUNIT_CLOCK_GATE_DISABLE (1 << 8)
- # define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */
- # define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */
- # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */
- # define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5)
- # define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4)
- /**
- * This bit must be set on the 830 to prevent hangs when turning off the
- * overlay scaler.
- */
- # define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3)
- # define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2)
- # define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1)
- # define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */
- # define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */
- #define RENCLK_GATE_D1 0x6204
- # define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */
- # define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */
- # define PC_FE_CLOCK_GATE_DISABLE (1 << 11)
- # define PC_BE_CLOCK_GATE_DISABLE (1 << 10)
- # define WINDOWER_CLOCK_GATE_DISABLE (1 << 9)
- # define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8)
- # define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7)
- # define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6)
- # define MAG_CLOCK_GATE_DISABLE (1 << 5)
- /** This bit must be unset on 855,865 */
- # define MECI_CLOCK_GATE_DISABLE (1 << 4)
- # define DCMP_CLOCK_GATE_DISABLE (1 << 3)
- # define MEC_CLOCK_GATE_DISABLE (1 << 2)
- # define MECO_CLOCK_GATE_DISABLE (1 << 1)
- /** This bit must be set on 855,865. */
- # define SV_CLOCK_GATE_DISABLE (1 << 0)
- # define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16)
- # define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15)
- # define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14)
- # define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13)
- # define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12)
- # define I915_WM_CLOCK_GATE_DISABLE (1 << 11)
- # define I915_IZ_CLOCK_GATE_DISABLE (1 << 10)
- # define I915_PI_CLOCK_GATE_DISABLE (1 << 9)
- # define I915_DI_CLOCK_GATE_DISABLE (1 << 8)
- # define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7)
- # define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6)
- # define I915_SC_CLOCK_GATE_DISABLE (1 << 5)
- # define I915_FL_CLOCK_GATE_DISABLE (1 << 4)
- # define I915_DM_CLOCK_GATE_DISABLE (1 << 3)
- # define I915_PS_CLOCK_GATE_DISABLE (1 << 2)
- # define I915_CC_CLOCK_GATE_DISABLE (1 << 1)
- # define I915_BY_CLOCK_GATE_DISABLE (1 << 0)
- # define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30)
- /** This bit must always be set on 965G/965GM */
- # define I965_RCC_CLOCK_GATE_DISABLE (1 << 29)
- # define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28)
- # define I965_DAP_CLOCK_GATE_DISABLE (1 << 27)
- # define I965_ROC_CLOCK_GATE_DISABLE (1 << 26)
- # define I965_GW_CLOCK_GATE_DISABLE (1 << 25)
- # define I965_TD_CLOCK_GATE_DISABLE (1 << 24)
- /** This bit must always be set on 965G */
- # define I965_ISC_CLOCK_GATE_DISABLE (1 << 23)
- # define I965_IC_CLOCK_GATE_DISABLE (1 << 22)
- # define I965_EU_CLOCK_GATE_DISABLE (1 << 21)
- # define I965_IF_CLOCK_GATE_DISABLE (1 << 20)
- # define I965_TC_CLOCK_GATE_DISABLE (1 << 19)
- # define I965_SO_CLOCK_GATE_DISABLE (1 << 17)
- # define I965_FBC_CLOCK_GATE_DISABLE (1 << 16)
- # define I965_MARI_CLOCK_GATE_DISABLE (1 << 15)
- # define I965_MASF_CLOCK_GATE_DISABLE (1 << 14)
- # define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13)
- # define I965_EM_CLOCK_GATE_DISABLE (1 << 12)
- # define I965_UC_CLOCK_GATE_DISABLE (1 << 11)
- # define I965_SI_CLOCK_GATE_DISABLE (1 << 6)
- # define I965_MT_CLOCK_GATE_DISABLE (1 << 5)
- # define I965_PL_CLOCK_GATE_DISABLE (1 << 4)
- # define I965_DG_CLOCK_GATE_DISABLE (1 << 3)
- # define I965_QC_CLOCK_GATE_DISABLE (1 << 2)
- # define I965_FT_CLOCK_GATE_DISABLE (1 << 1)
- # define I965_DM_CLOCK_GATE_DISABLE (1 << 0)
- #define RENCLK_GATE_D2 0x6208
- #define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9)
- #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7)
- #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6)
- #define RAMCLK_GATE_D 0x6210 /* CRL only */
- #define DEUC 0x6214 /* CRL only */
- /*
- * Palette regs
- */
- #define _PALETTE_A 0x0a000
- #define _PALETTE_B 0x0a800
- #define PALETTE(pipe) _PIPE(pipe, _PALETTE_A, _PALETTE_B)
- /* MCH MMIO space */
- /*
- * MCHBAR mirror.
- *
- * This mirrors the MCHBAR MMIO space whose location is determined by
- * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
- * every way. It is not accessible from the CP register read instructions.
- *
- */
- #define MCHBAR_MIRROR_BASE 0x10000
- #define MCHBAR_MIRROR_BASE_SNB 0x140000
- /** 915-945 and GM965 MCH register controlling DRAM channel access */
- #define DCC 0x10200
- #define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0)
- #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0)
- #define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0)
- #define DCC_ADDRESSING_MODE_MASK (3 << 0)
- #define DCC_CHANNEL_XOR_DISABLE (1 << 10)
- #define DCC_CHANNEL_XOR_BIT_17 (1 << 9)
- /** Pineview MCH register contains DDR3 setting */
- #define CSHRDDR3CTL 0x101a8
- #define CSHRDDR3CTL_DDR3 (1 << 2)
- /** 965 MCH register controlling DRAM channel configuration */
- #define C0DRB3 0x10206
- #define C1DRB3 0x10606
- /** snb MCH registers for reading the DRAM channel configuration */
- #define MAD_DIMM_C0 (MCHBAR_MIRROR_BASE_SNB + 0x5004)
- #define MAD_DIMM_C1 (MCHBAR_MIRROR_BASE_SNB + 0x5008)
- #define MAD_DIMM_C2 (MCHBAR_MIRROR_BASE_SNB + 0x500C)
- #define MAD_DIMM_ECC_MASK (0x3 << 24)
- #define MAD_DIMM_ECC_OFF (0x0 << 24)
- #define MAD_DIMM_ECC_IO_ON_LOGIC_OFF (0x1 << 24)
- #define MAD_DIMM_ECC_IO_OFF_LOGIC_ON (0x2 << 24)
- #define MAD_DIMM_ECC_ON (0x3 << 24)
- #define MAD_DIMM_ENH_INTERLEAVE (0x1 << 22)
- #define MAD_DIMM_RANK_INTERLEAVE (0x1 << 21)
- #define MAD_DIMM_B_WIDTH_X16 (0x1 << 20) /* X8 chips if unset */
- #define MAD_DIMM_A_WIDTH_X16 (0x1 << 19) /* X8 chips if unset */
- #define MAD_DIMM_B_DUAL_RANK (0x1 << 18)
- #define MAD_DIMM_A_DUAL_RANK (0x1 << 17)
- #define MAD_DIMM_A_SELECT (0x1 << 16)
- /* DIMM sizes are in multiples of 256mb. */
- #define MAD_DIMM_B_SIZE_SHIFT 8
- #define MAD_DIMM_B_SIZE_MASK (0xff << MAD_DIMM_B_SIZE_SHIFT)
- #define MAD_DIMM_A_SIZE_SHIFT 0
- #define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT)
- /* Clocking configuration register */
- #define CLKCFG 0x10c00
- #define CLKCFG_FSB_400 (5 << 0) /* hrawclk 100 */
- #define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */
- #define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */
- #define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */
- #define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */
- #define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */
- /* Note, below two are guess */
- #define CLKCFG_FSB_1600 (4 << 0) /* hrawclk 400 */
- #define CLKCFG_FSB_1600_ALT (0 << 0) /* hrawclk 400 */
- #define CLKCFG_FSB_MASK (7 << 0)
- #define CLKCFG_MEM_533 (1 << 4)
- #define CLKCFG_MEM_667 (2 << 4)
- #define CLKCFG_MEM_800 (3 << 4)
- #define CLKCFG_MEM_MASK (7 << 4)
- #define TSC1 0x11001
- #define TSE (1<<0)
- #define I915_TR1 0x11006
- #define TSFS 0x11020
- #define TSFS_SLOPE_MASK 0x0000ff00
- #define TSFS_SLOPE_SHIFT 8
- #define TSFS_INTR_MASK 0x000000ff
- #define CRSTANDVID 0x11100
- #define PXVFREQ_BASE 0x11110 /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
- #define PXVFREQ_PX_MASK 0x7f000000
- #define PXVFREQ_PX_SHIFT 24
- #define VIDFREQ_BASE 0x11110
- #define VIDFREQ1 0x11110 /* VIDFREQ1-4 (0x1111c) (Cantiga) */
- #define VIDFREQ2 0x11114
- #define VIDFREQ3 0x11118
- #define VIDFREQ4 0x1111c
- #define VIDFREQ_P0_MASK 0x1f000000
- #define VIDFREQ_P0_SHIFT 24
- #define VIDFREQ_P0_CSCLK_MASK 0x00f00000
- #define VIDFREQ_P0_CSCLK_SHIFT 20
- #define VIDFREQ_P0_CRCLK_MASK 0x000f0000
- #define VIDFREQ_P0_CRCLK_SHIFT 16
- #define VIDFREQ_P1_MASK 0x00001f00
- #define VIDFREQ_P1_SHIFT 8
- #define VIDFREQ_P1_CSCLK_MASK 0x000000f0
- #define VIDFREQ_P1_CSCLK_SHIFT 4
- #define VIDFREQ_P1_CRCLK_MASK 0x0000000f
- #define INTTOEXT_BASE_ILK 0x11300
- #define INTTOEXT_BASE 0x11120 /* INTTOEXT1-8 (0x1113c) */
- #define INTTOEXT_MAP3_SHIFT 24
- #define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT)
- #define INTTOEXT_MAP2_SHIFT 16
- #define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT)
- #define INTTOEXT_MAP1_SHIFT 8
- #define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT)
- #define INTTOEXT_MAP0_SHIFT 0
- #define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT)
- #define MEMSWCTL 0x11170 /* Ironlake only */
- #define MEMCTL_CMD_MASK 0xe000
- #define MEMCTL_CMD_SHIFT 13
- #define MEMCTL_CMD_RCLK_OFF 0
- #define MEMCTL_CMD_RCLK_ON 1
- #define MEMCTL_CMD_CHFREQ 2
- #define MEMCTL_CMD_CHVID 3
- #define MEMCTL_CMD_VMMOFF 4
- #define MEMCTL_CMD_VMMON 5
- #define MEMCTL_CMD_STS (1<<12) /* write 1 triggers command, clears
- when command complete */
- #define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */
- #define MEMCTL_FREQ_SHIFT 8
- #define MEMCTL_SFCAVM (1<<7)
- #define MEMCTL_TGT_VID_MASK 0x007f
- #define MEMIHYST 0x1117c
- #define MEMINTREN 0x11180 /* 16 bits */
- #define MEMINT_RSEXIT_EN (1<<8)
- #define MEMINT_CX_SUPR_EN (1<<7)
- #define MEMINT_CONT_BUSY_EN (1<<6)
- #define MEMINT_AVG_BUSY_EN (1<<5)
- #define MEMINT_EVAL_CHG_EN (1<<4)
- #define MEMINT_MON_IDLE_EN (1<<3)
- #define MEMINT_UP_EVAL_EN (1<<2)
- #define MEMINT_DOWN_EVAL_EN (1<<1)
- #define MEMINT_SW_CMD_EN (1<<0)
- #define MEMINTRSTR 0x11182 /* 16 bits */
- #define MEM_RSEXIT_MASK 0xc000
- #define MEM_RSEXIT_SHIFT 14
- #define MEM_CONT_BUSY_MASK 0x3000
- #define MEM_CONT_BUSY_SHIFT 12
- #define MEM_AVG_BUSY_MASK 0x0c00
- #define MEM_AVG_BUSY_SHIFT 10
- #define MEM_EVAL_CHG_MASK 0x0300
- #define MEM_EVAL_BUSY_SHIFT 8
- #define MEM_MON_IDLE_MASK 0x00c0
- #define MEM_MON_IDLE_SHIFT 6
- #define MEM_UP_EVAL_MASK 0x0030
- #define MEM_UP_EVAL_SHIFT 4
- #define MEM_DOWN_EVAL_MASK 0x000c
- #define MEM_DOWN_EVAL_SHIFT 2
- #define MEM_SW_CMD_MASK 0x0003
- #define MEM_INT_STEER_GFX 0
- #define MEM_INT_STEER_CMR 1
- #define MEM_INT_STEER_SMI 2
- #define MEM_INT_STEER_SCI 3
- #define MEMINTRSTS 0x11184
- #define MEMINT_RSEXIT (1<<7)
- #define MEMINT_CONT_BUSY (1<<6)
- #define MEMINT_AVG_BUSY (1<<5)
- #define MEMINT_EVAL_CHG (1<<4)
- #define MEMINT_MON_IDLE (1<<3)
- #define MEMINT_UP_EVAL (1<<2)
- #define MEMINT_DOWN_EVAL (1<<1)
- #define MEMINT_SW_CMD (1<<0)
- #define MEMMODECTL 0x11190
- #define MEMMODE_BOOST_EN (1<<31)
- #define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */
- #define MEMMODE_BOOST_FREQ_SHIFT 24
- #define MEMMODE_IDLE_MODE_MASK 0x00030000
- #define MEMMODE_IDLE_MODE_SHIFT 16
- #define MEMMODE_IDLE_MODE_EVAL 0
- #define MEMMODE_IDLE_MODE_CONT 1
- #define MEMMODE_HWIDLE_EN (1<<15)
- #define MEMMODE_SWMODE_EN (1<<14)
- #define MEMMODE_RCLK_GATE (1<<13)
- #define MEMMODE_HW_UPDATE (1<<12)
- #define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */
- #define MEMMODE_FSTART_SHIFT 8
- #define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */
- #define MEMMODE_FMAX_SHIFT 4
- #define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */
- #define RCBMAXAVG 0x1119c
- #define MEMSWCTL2 0x1119e /* Cantiga only */
- #define SWMEMCMD_RENDER_OFF (0 << 13)
- #define SWMEMCMD_RENDER_ON (1 << 13)
- #define SWMEMCMD_SWFREQ (2 << 13)
- #define SWMEMCMD_TARVID (3 << 13)
- #define SWMEMCMD_VRM_OFF (4 << 13)
- #define SWMEMCMD_VRM_ON (5 << 13)
- #define CMDSTS (1<<12)
- #define SFCAVM (1<<11)
- #define SWFREQ_MASK 0x0380 /* P0-7 */
- #define SWFREQ_SHIFT 7
- #define TARVID_MASK 0x001f
- #define MEMSTAT_CTG 0x111a0
- #define RCBMINAVG 0x111a0
- #define RCUPEI 0x111b0
- #define RCDNEI 0x111b4
- #define RSTDBYCTL 0x111b8
- #define RS1EN (1<<31)
- #define RS2EN (1<<30)
- #define RS3EN (1<<29)
- #define D3RS3EN (1<<28) /* Display D3 imlies RS3 */
- #define SWPROMORSX (1<<27) /* RSx promotion timers ignored */
- #define RCWAKERW (1<<26) /* Resetwarn from PCH causes wakeup */
- #define DPRSLPVREN (1<<25) /* Fast voltage ramp enable */
- #define GFXTGHYST (1<<24) /* Hysteresis to allow trunk gating */
- #define RCX_SW_EXIT (1<<23) /* Leave RSx and prevent re-entry */
- #define RSX_STATUS_MASK (7<<20)
- #define RSX_STATUS_ON (0<<20)
- #define RSX_STATUS_RC1 (1<<20)
- #define RSX_STATUS_RC1E (2<<20)
- #define RSX_STATUS_RS1 (3<<20)
- #define RSX_STATUS_RS2 (4<<20) /* aka rc6 */
- #define RSX_STATUS_RSVD (5<<20) /* deep rc6 unsupported on ilk */
- #define RSX_STATUS_RS3 (6<<20) /* rs3 unsupported on ilk */
- #define RSX_STATUS_RSVD2 (7<<20)
- #define UWRCRSXE (1<<19) /* wake counter limit prevents rsx */
- #define RSCRP (1<<18) /* rs requests control on rs1/2 reqs */
- #define JRSC (1<<17) /* rsx coupled to cpu c-state */
- #define RS2INC0 (1<<16) /* allow rs2 in cpu c0 */
- #define RS1CONTSAV_MASK (3<<14)
- #define RS1CONTSAV_NO_RS1 (0<<14) /* rs1 doesn't save/restore context */
- #define RS1CONTSAV_RSVD (1<<14)
- #define RS1CONTSAV_SAVE_RS1 (2<<14) /* rs1 saves context */
- #define RS1CONTSAV_FULL_RS1 (3<<14) /* rs1 saves and restores context */
- #define NORMSLEXLAT_MASK (3<<12)
- #define SLOW_RS123 (0<<12)
- #define SLOW_RS23 (1<<12)
- #define SLOW_RS3 (2<<12)
- #define NORMAL_RS123 (3<<12)
- #define RCMODE_TIMEOUT (1<<11) /* 0 is eval interval method */
- #define IMPROMOEN (1<<10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */
- #define RCENTSYNC (1<<9) /* rs coupled to cpu c-state (3/6/7) */
- #define STATELOCK (1<<7) /* locked to rs_cstate if 0 */
- #define RS_CSTATE_MASK (3<<4)
- #define RS_CSTATE_C367_RS1 (0<<4)
- #define RS_CSTATE_C36_RS1_C7_RS2 (1<<4)
- #define RS_CSTATE_RSVD (2<<4)
- #define RS_CSTATE_C367_RS2 (3<<4)
- #define REDSAVES (1<<3) /* no context save if was idle during rs0 */
- #define REDRESTORES (1<<2) /* no restore if was idle during rs0 */
- #define VIDCTL 0x111c0
- #define VIDSTS 0x111c8
- #define VIDSTART 0x111cc /* 8 bits */
- #define MEMSTAT_ILK 0x111f8
- #define MEMSTAT_VID_MASK 0x7f00
- #define MEMSTAT_VID_SHIFT 8
- #define MEMSTAT_PSTATE_MASK 0x00f8
- #define MEMSTAT_PSTATE_SHIFT 3
- #define MEMSTAT_MON_ACTV (1<<2)
- #define MEMSTAT_SRC_CTL_MASK 0x0003
- #define MEMSTAT_SRC_CTL_CORE 0
- #define MEMSTAT_SRC_CTL_TRB 1
- #define MEMSTAT_SRC_CTL_THM 2
- #define MEMSTAT_SRC_CTL_STDBY 3
- #define RCPREVBSYTUPAVG 0x113b8
- …
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