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/ovm-2.0.1/examples/xbus/sv/xbus_master_driver.sv

http://camlet.googlecode.com/
SystemVerilog | 173 lines | 110 code | 22 blank | 41 comment | 7 complexity | e0b186484cad934693b9561c91154b58 MD5 | raw file
Possible License(s): Apache-2.0
  1// $Id: //dvt/vtech/dev/main/ovm/examples/xbus/sv/xbus_master_driver.sv#7 $
  2//----------------------------------------------------------------------
  3//   Copyright 2007-2008 Mentor Graphics Corporation
  4//   Copyright 2007-2008 Cadence Design Systems, Inc.
  5//   All Rights Reserved Worldwide
  6//
  7//   Licensed under the Apache License, Version 2.0 (the
  8//   "License"); you may not use this file except in
  9//   compliance with the License.  You may obtain a copy of
 10//   the License at
 11//
 12//       http://www.apache.org/licenses/LICENSE-2.0
 13//
 14//   Unless required by applicable law or agreed to in
 15//   writing, software distributed under the License is
 16//   distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
 17//   CONDITIONS OF ANY KIND, either express or implied.  See
 18//   the License for the specific language governing
 19//   permissions and limitations under the License.
 20//----------------------------------------------------------------------
 21
 22`ifndef XBUS_MASTER_DRIVER_SV
 23`define XBUS_MASTER_DRIVER_SV
 24
 25//------------------------------------------------------------------------------
 26//
 27// CLASS: xbus_master_driver
 28//
 29//------------------------------------------------------------------------------
 30
 31class xbus_master_driver extends ovm_driver #(xbus_transfer);
 32
 33  // The virtual interface used to drive and view HDL signals.
 34  protected virtual xbus_if xmi;
 35
 36  // Master Id
 37  protected int master_id;
 38
 39  // Provide implmentations of virtual methods such as get_type_name and create
 40  `ovm_component_utils_begin(xbus_master_driver)
 41    `ovm_field_int(master_id, OVM_ALL_ON)
 42  `ovm_component_utils_end
 43
 44  // new - constructor
 45  function new (string name, ovm_component parent);
 46    super.new(name, parent);
 47  endfunction : new
 48
 49  // assign_vi
 50  function void assign_vi(virtual interface xbus_if xmi);
 51    this.xmi = xmi;
 52  endfunction : assign_vi
 53
 54  // run phase
 55  virtual task run();
 56    fork
 57      get_and_drive();
 58      reset_signals();
 59    join
 60  endtask : run
 61
 62  // get_and_drive 
 63  virtual protected task get_and_drive();
 64    @(negedge xmi.sig_reset);
 65    forever begin
 66      @(posedge xmi.sig_clock);
 67      seq_item_port.get_next_item(req);
 68      $cast(rsp, req.clone());
 69      rsp.set_id_info(req);
 70      drive_transfer(rsp);
 71      seq_item_port.item_done(rsp);
 72    end
 73  endtask : get_and_drive
 74
 75  // reset_signals
 76  virtual protected task reset_signals();
 77    forever begin
 78      @(posedge xmi.sig_reset);
 79      xmi.sig_request[master_id]  <= 0;
 80      xmi.rw                      <= 'h0;
 81      xmi.sig_addr           <= 'hz;
 82      xmi.sig_data_out       <= 'hz;
 83      xmi.sig_size           <= 'bz;
 84      xmi.sig_read           <= 'bz;
 85      xmi.sig_write          <= 'bz;
 86      xmi.sig_bip            <= 'bz;
 87    end
 88  endtask : reset_signals
 89
 90  // drive_transfer
 91  virtual protected task drive_transfer (xbus_transfer trans);
 92    if (trans.transmit_delay > 0) begin
 93      repeat(trans.transmit_delay) @(posedge xmi.sig_clock);
 94    end
 95    arbitrate_for_bus();
 96    drive_address_phase(trans);
 97    drive_data_phase(trans);
 98  endtask : drive_transfer
 99
100  // arbitrate_for_bus
101  virtual protected task arbitrate_for_bus();
102    xmi.sig_request[master_id] <= 1;
103    @(posedge xmi.sig_clock iff xmi.sig_grant[master_id] === 1);
104    xmi.sig_request[master_id] <= 0;
105  endtask : arbitrate_for_bus
106
107  // drive_address_phase
108  virtual protected task drive_address_phase (xbus_transfer trans);
109    xmi.sig_addr <= trans.addr;
110    drive_size(trans.size);
111    drive_read_write(trans.read_write);
112    @(posedge xmi.sig_clock);
113    xmi.sig_addr <= 32'bz;
114    xmi.sig_size <= 2'bz;
115    xmi.sig_read <= 1'bz;
116    xmi.sig_write <= 1'bz;  
117  endtask : drive_address_phase
118
119  // drive_data_phase
120  virtual protected task drive_data_phase (xbus_transfer trans);
121    bit err;
122    for(int i = 0; i <= trans.size - 1; i ++) begin
123      if (i == (trans.size - 1))
124        xmi.sig_bip <= 0;
125      else
126        xmi.sig_bip <= 1;
127      case (trans.read_write)
128        READ    : read_byte(trans.data[i], err);
129        WRITE   : write_byte(trans.data[i], err);
130      endcase
131    end //for loop
132    xmi.sig_data_out <= 8'bz;
133    xmi.sig_bip <= 1'bz;
134  endtask : drive_data_phase
135
136  // read_byte
137  virtual protected task read_byte (output bit [7:0] data, output bit error);
138    xmi.rw <= 1'b0;
139    @(posedge xmi.sig_clock iff xmi.sig_wait === 0);
140    data = xmi.sig_data;
141  endtask : read_byte
142
143  // write_byte
144  virtual protected task write_byte (bit[7:0] data, output bit error);
145    xmi.rw <= 1'b1;
146    xmi.sig_data_out <= data;
147    @(posedge xmi.sig_clock iff xmi.sig_wait === 0);
148    xmi.rw <= 'h0;
149  endtask : write_byte
150
151  // drive_size
152  virtual protected task drive_size (int size);
153    case (size)
154      1: xmi.sig_size <=  2'b00;
155      2: xmi.sig_size <=  2'b01;
156      4: xmi.sig_size <=  2'b10;
157      8: xmi.sig_size <=  2'b11;
158    endcase
159  endtask : drive_size
160
161  // drive_read_write            
162  virtual protected task drive_read_write(xbus_read_write_enum rw);
163    case (rw)
164      NOP   : begin xmi.sig_read <= 0; xmi.sig_write <= 0; end
165      READ  : begin xmi.sig_read <= 1; xmi.sig_write <= 0; end
166      WRITE : begin xmi.sig_read <= 0; xmi.sig_write <= 1; end
167    endcase
168  endtask : drive_read_write
169
170endclass : xbus_master_driver
171
172`endif // XBUS_MASTER_DRIVER_SV
173