/and2/and2.sv

http://camlet.googlecode.com/ · SystemVerilog · 8 lines · 7 code · 1 blank · 0 comment · 1 complexity · c3c27c4f90616348ecd9d7b3f276d35a MD5 · raw file 

    

  1. module and2(Y, A, B);
    2. 

  2.         input A, B;
    3. 

  3.         output Y;
    4. 

  4.         reg Y;
    5. 

  5. 

  6.         always @(A or B)
    7. 

  7.                 Y = #1 A & B;
    8. 

  8. endmodule
    9.