/and2/and2.sv
SystemVerilog | 8 lines | 7 code | 1 blank | 0 comment | 1 complexity | c3c27c4f90616348ecd9d7b3f276d35a MD5 | raw file
Possible License(s): Apache-2.0
1module and2(Y, A, B); 2 input A, B; 3 output Y; 4 reg Y; 5 6 always @(A or B) 7 Y = #1 A & B; 8endmodule