/kern_2.6.32/arch/mips/include/asm/bitops.h

http://omnia2droid.googlecode.com/ · C++ Header · 710 lines · 526 code · 69 blank · 115 comment · 72 complexity · 72ce36c67771146f0031cc99c344f3e3 MD5 · raw file 

    

  1. /*
    2. 

  2.  * This file is subject to the terms and conditions of the GNU General Public
    3. 

  3.  * License.  See the file "COPYING" in the main directory of this archive
    4. 

  4.  * for more details.
    5. 

  5.  *
    6. 

  6.  * Copyright (c) 1994 - 1997, 99, 2000, 06, 07  Ralf Baechle (ralf@linux-mips.org)
    7. 

  7.  * Copyright (c) 1999, 2000  Silicon Graphics, Inc.
    8. 

  8.  */
    9. 

  9. #ifndef _ASM_BITOPS_H
    10. 

  10. #define _ASM_BITOPS_H
    11. 

  11. 

  12. #ifndef _LINUX_BITOPS_H
    13. 

  13. #error only <linux/bitops.h> can be included directly
    14. 

  14. #endif
    15. 

  15. 

  16. #include <linux/compiler.h>
    17. 

  17. #include <linux/irqflags.h>
    18. 

  18. #include <linux/types.h>
    19. 

  19. #include <asm/barrier.h>
    20. 

  20. #include <asm/bug.h>
    21. 

  21. #include <asm/byteorder.h>		/* sigh ... */
    22. 

  22. #include <asm/cpu-features.h>
    23. 

  23. #include <asm/sgidefs.h>
    24. 

  24. #include <asm/war.h>
    25. 

  25. 

  26. #if _MIPS_SZLONG == 32
    27. 

  27. #define SZLONG_LOG 5
    28. 

  28. #define SZLONG_MASK 31UL
    29. 

  29. #define __LL		"ll	"
    30. 

  30. #define __SC		"sc	"
    31. 

  31. #define __INS		"ins    "
    32. 

  32. #define __EXT		"ext    "
    33. 

  33. #elif _MIPS_SZLONG == 64
    34. 

  34. #define SZLONG_LOG 6
    35. 

  35. #define SZLONG_MASK 63UL
    36. 

  36. #define __LL		"lld	"
    37. 

  37. #define __SC		"scd	"
    38. 

  38. #define __INS		"dins    "
    39. 

  39. #define __EXT		"dext    "
    40. 

  40. #endif
    41. 

  41. 

  42. /*
    43. 

  43.  * clear_bit() doesn't provide any barrier for the compiler.
    44. 

  44.  */
    45. 

  45. #define smp_mb__before_clear_bit()	smp_llsc_mb()
    46. 

  46. #define smp_mb__after_clear_bit()	smp_llsc_mb()
    47. 

  47. 

  48. /*
    49. 

  49.  * set_bit - Atomically set a bit in memory
    50. 

  50.  * @nr: the bit to set
    51. 

  51.  * @addr: the address to start counting from
    52. 

  52.  *
    53. 

  53.  * This function is atomic and may not be reordered.  See __set_bit()
    54. 

  54.  * if you do not require the atomic guarantees.
    55. 

  55.  * Note that @nr may be almost arbitrarily large; this function is not
    56. 

  56.  * restricted to acting on a single-word quantity.
    57. 

  57.  */
    58. 

  58. static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
    59. 

  59. {
    60. 

  60. 	unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
    61. 

  61. 	unsigned short bit = nr & SZLONG_MASK;
    62. 

  62. 	unsigned long temp;
    63. 

  63. 

  64. 	if (kernel_uses_llsc && R10000_LLSC_WAR) {
    65. 

  65. 		__asm__ __volatile__(
    66. 

  66. 		"	.set	mips3					\n"
    67. 

  67. 		"1:	" __LL "%0, %1			# set_bit	\n"
    68. 

  68. 		"	or	%0, %2					\n"
    69. 

  69. 		"	" __SC	"%0, %1					\n"
    70. 

  70. 		"	beqzl	%0, 1b					\n"
    71. 

  71. 		"	.set	mips0					\n"
    72. 

  72. 		: "=&r" (temp), "=m" (*m)
    73. 

  73. 		: "ir" (1UL << bit), "m" (*m));
    74. 

  74. #ifdef CONFIG_CPU_MIPSR2
    75. 

  75. 	} else if (kernel_uses_llsc && __builtin_constant_p(bit)) {
    76. 

  76. 		__asm__ __volatile__(
    77. 

  77. 		"1:	" __LL "%0, %1			# set_bit	\n"
    78. 

  78. 		"	" __INS "%0, %4, %2, 1				\n"
    79. 

  79. 		"	" __SC "%0, %1					\n"
    80. 

  80. 		"	beqz	%0, 2f					\n"
    81. 

  81. 		"	.subsection 2					\n"
    82. 

  82. 		"2:	b	1b					\n"
    83. 

  83. 		"	.previous					\n"
    84. 

  84. 		: "=&r" (temp), "=m" (*m)
    85. 

  85. 		: "ir" (bit), "m" (*m), "r" (~0));
    86. 

  86. #endif /* CONFIG_CPU_MIPSR2 */
    87. 

  87. 	} else if (kernel_uses_llsc) {
    88. 

  88. 		__asm__ __volatile__(
    89. 

  89. 		"	.set	mips3					\n"
    90. 

  90. 		"1:	" __LL "%0, %1			# set_bit	\n"
    91. 

  91. 		"	or	%0, %2					\n"
    92. 

  92. 		"	" __SC	"%0, %1					\n"
    93. 

  93. 		"	beqz	%0, 2f					\n"
    94. 

  94. 		"	.subsection 2					\n"
    95. 

  95. 		"2:	b	1b					\n"
    96. 

  96. 		"	.previous					\n"
    97. 

  97. 		"	.set	mips0					\n"
    98. 

  98. 		: "=&r" (temp), "=m" (*m)
    99. 

  99. 		: "ir" (1UL << bit), "m" (*m));
    100. 

  100. 	} else {
    101. 

  101. 		volatile unsigned long *a = addr;
    102. 

  102. 		unsigned long mask;
    103. 

  103. 		unsigned long flags;
    104. 

  104. 

  105. 		a += nr >> SZLONG_LOG;
    106. 

  106. 		mask = 1UL << bit;
    107. 

  107. 		raw_local_irq_save(flags);
    108. 

  108. 		*a |= mask;
    109. 

  109. 		raw_local_irq_restore(flags);
    110. 

  110. 	}
    111. 

  111. }
    112. 

  112. 

  113. /*
    114. 

  114.  * clear_bit - Clears a bit in memory
    115. 

  115.  * @nr: Bit to clear
    116. 

  116.  * @addr: Address to start counting from
    117. 

  117.  *
    118. 

  118.  * clear_bit() is atomic and may not be reordered.  However, it does
    119. 

  119.  * not contain a memory barrier, so if it is used for locking purposes,
    120. 

  120.  * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit()
    121. 

  121.  * in order to ensure changes are visible on other processors.
    122. 

  122.  */
    123. 

  123. static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
    124. 

  124. {
    125. 

  125. 	unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
    126. 

  126. 	unsigned short bit = nr & SZLONG_MASK;
    127. 

  127. 	unsigned long temp;
    128. 

  128. 

  129. 	if (kernel_uses_llsc && R10000_LLSC_WAR) {
    130. 

  130. 		__asm__ __volatile__(
    131. 

  131. 		"	.set	mips3					\n"
    132. 

  132. 		"1:	" __LL "%0, %1			# clear_bit	\n"
    133. 

  133. 		"	and	%0, %2					\n"
    134. 

  134. 		"	" __SC "%0, %1					\n"
    135. 

  135. 		"	beqzl	%0, 1b					\n"
    136. 

  136. 		"	.set	mips0					\n"
    137. 

  137. 		: "=&r" (temp), "=m" (*m)
    138. 

  138. 		: "ir" (~(1UL << bit)), "m" (*m));
    139. 

  139. #ifdef CONFIG_CPU_MIPSR2
    140. 

  140. 	} else if (kernel_uses_llsc && __builtin_constant_p(bit)) {
    141. 

  141. 		__asm__ __volatile__(
    142. 

  142. 		"1:	" __LL "%0, %1			# clear_bit	\n"
    143. 

  143. 		"	" __INS "%0, $0, %2, 1				\n"
    144. 

  144. 		"	" __SC "%0, %1					\n"
    145. 

  145. 		"	beqz	%0, 2f					\n"
    146. 

  146. 		"	.subsection 2					\n"
    147. 

  147. 		"2:	b	1b					\n"
    148. 

  148. 		"	.previous					\n"
    149. 

  149. 		: "=&r" (temp), "=m" (*m)
    150. 

  150. 		: "ir" (bit), "m" (*m));
    151. 

  151. #endif /* CONFIG_CPU_MIPSR2 */
    152. 

  152. 	} else if (kernel_uses_llsc) {
    153. 

  153. 		__asm__ __volatile__(
    154. 

  154. 		"	.set	mips3					\n"
    155. 

  155. 		"1:	" __LL "%0, %1			# clear_bit	\n"
    156. 

  156. 		"	and	%0, %2					\n"
    157. 

  157. 		"	" __SC "%0, %1					\n"
    158. 

  158. 		"	beqz	%0, 2f					\n"
    159. 

  159. 		"	.subsection 2					\n"
    160. 

  160. 		"2:	b	1b					\n"
    161. 

  161. 		"	.previous					\n"
    162. 

  162. 		"	.set	mips0					\n"
    163. 

  163. 		: "=&r" (temp), "=m" (*m)
    164. 

  164. 		: "ir" (~(1UL << bit)), "m" (*m));
    165. 

  165. 	} else {
    166. 

  166. 		volatile unsigned long *a = addr;
    167. 

  167. 		unsigned long mask;
    168. 

  168. 		unsigned long flags;
    169. 

  169. 

  170. 		a += nr >> SZLONG_LOG;
    171. 

  171. 		mask = 1UL << bit;
    172. 

  172. 		raw_local_irq_save(flags);
    173. 

  173. 		*a &= ~mask;
    174. 

  174. 		raw_local_irq_restore(flags);
    175. 

  175. 	}
    176. 

  176. }
    177. 

  177. 

  178. /*
    179. 

  179.  * clear_bit_unlock - Clears a bit in memory
    180. 

  180.  * @nr: Bit to clear
    181. 

  181.  * @addr: Address to start counting from
    182. 

  182.  *
    183. 

  183.  * clear_bit() is atomic and implies release semantics before the memory
    184. 

  184.  * operation. It can be used for an unlock.
    185. 

  185.  */
    186. 

  186. static inline void clear_bit_unlock(unsigned long nr, volatile unsigned long *addr)
    187. 

  187. {
    188. 

  188. 	smp_mb__before_clear_bit();
    189. 

  189. 	clear_bit(nr, addr);
    190. 

  190. }
    191. 

  191. 

  192. /*
    193. 

  193.  * change_bit - Toggle a bit in memory
    194. 

  194.  * @nr: Bit to change
    195. 

  195.  * @addr: Address to start counting from
    196. 

  196.  *
    197. 

  197.  * change_bit() is atomic and may not be reordered.
    198. 

  198.  * Note that @nr may be almost arbitrarily large; this function is not
    199. 

  199.  * restricted to acting on a single-word quantity.
    200. 

  200.  */
    201. 

  201. static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
    202. 

  202. {
    203. 

  203. 	unsigned short bit = nr & SZLONG_MASK;
    204. 

  204. 

  205. 	if (kernel_uses_llsc && R10000_LLSC_WAR) {
    206. 

  206. 		unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
    207. 

  207. 		unsigned long temp;
    208. 

  208. 

  209. 		__asm__ __volatile__(
    210. 

  210. 		"	.set	mips3				\n"
    211. 

  211. 		"1:	" __LL "%0, %1		# change_bit	\n"
    212. 

  212. 		"	xor	%0, %2				\n"
    213. 

  213. 		"	" __SC	"%0, %1				\n"
    214. 

  214. 		"	beqzl	%0, 1b				\n"
    215. 

  215. 		"	.set	mips0				\n"
    216. 

  216. 		: "=&r" (temp), "=m" (*m)
    217. 

  217. 		: "ir" (1UL << bit), "m" (*m));
    218. 

  218. 	} else if (kernel_uses_llsc) {
    219. 

  219. 		unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
    220. 

  220. 		unsigned long temp;
    221. 

  221. 

  222. 		__asm__ __volatile__(
    223. 

  223. 		"	.set	mips3				\n"
    224. 

  224. 		"1:	" __LL "%0, %1		# change_bit	\n"
    225. 

  225. 		"	xor	%0, %2				\n"
    226. 

  226. 		"	" __SC	"%0, %1				\n"
    227. 

  227. 		"	beqz	%0, 2f				\n"
    228. 

  228. 		"	.subsection 2				\n"
    229. 

  229. 		"2:	b	1b				\n"
    230. 

  230. 		"	.previous				\n"
    231. 

  231. 		"	.set	mips0				\n"
    232. 

  232. 		: "=&r" (temp), "=m" (*m)
    233. 

  233. 		: "ir" (1UL << bit), "m" (*m));
    234. 

  234. 	} else {
    235. 

  235. 		volatile unsigned long *a = addr;
    236. 

  236. 		unsigned long mask;
    237. 

  237. 		unsigned long flags;
    238. 

  238. 

  239. 		a += nr >> SZLONG_LOG;
    240. 

  240. 		mask = 1UL << bit;
    241. 

  241. 		raw_local_irq_save(flags);
    242. 

  242. 		*a ^= mask;
    243. 

  243. 		raw_local_irq_restore(flags);
    244. 

  244. 	}
    245. 

  245. }
    246. 

  246. 

  247. /*
    248. 

  248.  * test_and_set_bit - Set a bit and return its old value
    249. 

  249.  * @nr: Bit to set
    250. 

  250.  * @addr: Address to count from
    251. 

  251.  *
    252. 

  252.  * This operation is atomic and cannot be reordered.
    253. 

  253.  * It also implies a memory barrier.
    254. 

  254.  */
    255. 

  255. static inline int test_and_set_bit(unsigned long nr,
    256. 

  256. 	volatile unsigned long *addr)
    257. 

  257. {
    258. 

  258. 	unsigned short bit = nr & SZLONG_MASK;
    259. 

  259. 	unsigned long res;
    260. 

  260. 

  261. 	smp_llsc_mb();
    262. 

  262. 

  263. 	if (kernel_uses_llsc && R10000_LLSC_WAR) {
    264. 

  264. 		unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
    265. 

  265. 		unsigned long temp;
    266. 

  266. 

  267. 		__asm__ __volatile__(
    268. 

  268. 		"	.set	mips3					\n"
    269. 

  269. 		"1:	" __LL "%0, %1		# test_and_set_bit	\n"
    270. 

  270. 		"	or	%2, %0, %3				\n"
    271. 

  271. 		"	" __SC	"%2, %1					\n"
    272. 

  272. 		"	beqzl	%2, 1b					\n"
    273. 

  273. 		"	and	%2, %0, %3				\n"
    274. 

  274. 		"	.set	mips0					\n"
    275. 

  275. 		: "=&r" (temp), "=m" (*m), "=&r" (res)
    276. 

  276. 		: "r" (1UL << bit), "m" (*m)
    277. 

  277. 		: "memory");
    278. 

  278. 	} else if (kernel_uses_llsc) {
    279. 

  279. 		unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
    280. 

  280. 		unsigned long temp;
    281. 

  281. 

  282. 		__asm__ __volatile__(
    283. 

  283. 		"	.set	push					\n"
    284. 

  284. 		"	.set	noreorder				\n"
    285. 

  285. 		"	.set	mips3					\n"
    286. 

  286. 		"1:	" __LL "%0, %1		# test_and_set_bit	\n"
    287. 

  287. 		"	or	%2, %0, %3				\n"
    288. 

  288. 		"	" __SC	"%2, %1					\n"
    289. 

  289. 		"	beqz	%2, 2f					\n"
    290. 

  290. 		"	 and	%2, %0, %3				\n"
    291. 

  291. 		"	.subsection 2					\n"
    292. 

  292. 		"2:	b	1b					\n"
    293. 

  293. 		"	 nop						\n"
    294. 

  294. 		"	.previous					\n"
    295. 

  295. 		"	.set	pop					\n"
    296. 

  296. 		: "=&r" (temp), "=m" (*m), "=&r" (res)
    297. 

  297. 		: "r" (1UL << bit), "m" (*m)
    298. 

  298. 		: "memory");
    299. 

  299. 	} else {
    300. 

  300. 		volatile unsigned long *a = addr;
    301. 

  301. 		unsigned long mask;
    302. 

  302. 		unsigned long flags;
    303. 

  303. 

  304. 		a += nr >> SZLONG_LOG;
    305. 

  305. 		mask = 1UL << bit;
    306. 

  306. 		raw_local_irq_save(flags);
    307. 

  307. 		res = (mask & *a);
    308. 

  308. 		*a |= mask;
    309. 

  309. 		raw_local_irq_restore(flags);
    310. 

  310. 	}
    311. 

  311. 

  312. 	smp_llsc_mb();
    313. 

  313. 

  314. 	return res != 0;
    315. 

  315. }
    316. 

  316. 

  317. /*
    318. 

  318.  * test_and_set_bit_lock - Set a bit and return its old value
    319. 

  319.  * @nr: Bit to set
    320. 

  320.  * @addr: Address to count from
    321. 

  321.  *
    322. 

  322.  * This operation is atomic and implies acquire ordering semantics
    323. 

  323.  * after the memory operation.
    324. 

  324.  */
    325. 

  325. static inline int test_and_set_bit_lock(unsigned long nr,
    326. 

  326. 	volatile unsigned long *addr)
    327. 

  327. {
    328. 

  328. 	unsigned short bit = nr & SZLONG_MASK;
    329. 

  329. 	unsigned long res;
    330. 

  330. 

  331. 	if (kernel_uses_llsc && R10000_LLSC_WAR) {
    332. 

  332. 		unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
    333. 

  333. 		unsigned long temp;
    334. 

  334. 

  335. 		__asm__ __volatile__(
    336. 

  336. 		"	.set	mips3					\n"
    337. 

  337. 		"1:	" __LL "%0, %1		# test_and_set_bit	\n"
    338. 

  338. 		"	or	%2, %0, %3				\n"
    339. 

  339. 		"	" __SC	"%2, %1					\n"
    340. 

  340. 		"	beqzl	%2, 1b					\n"
    341. 

  341. 		"	and	%2, %0, %3				\n"
    342. 

  342. 		"	.set	mips0					\n"
    343. 

  343. 		: "=&r" (temp), "=m" (*m), "=&r" (res)
    344. 

  344. 		: "r" (1UL << bit), "m" (*m)
    345. 

  345. 		: "memory");
    346. 

  346. 	} else if (kernel_uses_llsc) {
    347. 

  347. 		unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
    348. 

  348. 		unsigned long temp;
    349. 

  349. 

  350. 		__asm__ __volatile__(
    351. 

  351. 		"	.set	push					\n"
    352. 

  352. 		"	.set	noreorder				\n"
    353. 

  353. 		"	.set	mips3					\n"
    354. 

  354. 		"1:	" __LL "%0, %1		# test_and_set_bit	\n"
    355. 

  355. 		"	or	%2, %0, %3				\n"
    356. 

  356. 		"	" __SC	"%2, %1					\n"
    357. 

  357. 		"	beqz	%2, 2f					\n"
    358. 

  358. 		"	 and	%2, %0, %3				\n"
    359. 

  359. 		"	.subsection 2					\n"
    360. 

  360. 		"2:	b	1b					\n"
    361. 

  361. 		"	 nop						\n"
    362. 

  362. 		"	.previous					\n"
    363. 

  363. 		"	.set	pop					\n"
    364. 

  364. 		: "=&r" (temp), "=m" (*m), "=&r" (res)
    365. 

  365. 		: "r" (1UL << bit), "m" (*m)
    366. 

  366. 		: "memory");
    367. 

  367. 	} else {
    368. 

  368. 		volatile unsigned long *a = addr;
    369. 

  369. 		unsigned long mask;
    370. 

  370. 		unsigned long flags;
    371. 

  371. 

  372. 		a += nr >> SZLONG_LOG;
    373. 

  373. 		mask = 1UL << bit;
    374. 

  374. 		raw_local_irq_save(flags);
    375. 

  375. 		res = (mask & *a);
    376. 

  376. 		*a |= mask;
    377. 

  377. 		raw_local_irq_restore(flags);
    378. 

  378. 	}
    379. 

  379. 

  380. 	smp_llsc_mb();
    381. 

  381. 

  382. 	return res != 0;
    383. 

  383. }
    384. 

  384. /*
    385. 

  385.  * test_and_clear_bit - Clear a bit and return its old value
    386. 

  386.  * @nr: Bit to clear
    387. 

  387.  * @addr: Address to count from
    388. 

  388.  *
    389. 

  389.  * This operation is atomic and cannot be reordered.
    390. 

  390.  * It also implies a memory barrier.
    391. 

  391.  */
    392. 

  392. static inline int test_and_clear_bit(unsigned long nr,
    393. 

  393. 	volatile unsigned long *addr)
    394. 

  394. {
    395. 

  395. 	unsigned short bit = nr & SZLONG_MASK;
    396. 

  396. 	unsigned long res;
    397. 

  397. 

  398. 	smp_llsc_mb();
    399. 

  399. 

  400. 	if (kernel_uses_llsc && R10000_LLSC_WAR) {
    401. 

  401. 		unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
    402. 

  402. 		unsigned long temp;
    403. 

  403. 

  404. 		__asm__ __volatile__(
    405. 

  405. 		"	.set	mips3					\n"
    406. 

  406. 		"1:	" __LL	"%0, %1		# test_and_clear_bit	\n"
    407. 

  407. 		"	or	%2, %0, %3				\n"
    408. 

  408. 		"	xor	%2, %3					\n"
    409. 

  409. 		"	" __SC 	"%2, %1					\n"
    410. 

  410. 		"	beqzl	%2, 1b					\n"
    411. 

  411. 		"	and	%2, %0, %3				\n"
    412. 

  412. 		"	.set	mips0					\n"
    413. 

  413. 		: "=&r" (temp), "=m" (*m), "=&r" (res)
    414. 

  414. 		: "r" (1UL << bit), "m" (*m)
    415. 

  415. 		: "memory");
    416. 

  416. #ifdef CONFIG_CPU_MIPSR2
    417. 

  417. 	} else if (kernel_uses_llsc && __builtin_constant_p(nr)) {
    418. 

  418. 		unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
    419. 

  419. 		unsigned long temp;
    420. 

  420. 

  421. 		__asm__ __volatile__(
    422. 

  422. 		"1:	" __LL	"%0, %1		# test_and_clear_bit	\n"
    423. 

  423. 		"	" __EXT "%2, %0, %3, 1				\n"
    424. 

  424. 		"	" __INS	"%0, $0, %3, 1				\n"
    425. 

  425. 		"	" __SC 	"%0, %1					\n"
    426. 

  426. 		"	beqz	%0, 2f					\n"
    427. 

  427. 		"	.subsection 2					\n"
    428. 

  428. 		"2:	b	1b					\n"
    429. 

  429. 		"	.previous					\n"
    430. 

  430. 		: "=&r" (temp), "=m" (*m), "=&r" (res)
    431. 

  431. 		: "ir" (bit), "m" (*m)
    432. 

  432. 		: "memory");
    433. 

  433. #endif
    434. 

  434. 	} else if (kernel_uses_llsc) {
    435. 

  435. 		unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
    436. 

  436. 		unsigned long temp;
    437. 

  437. 

  438. 		__asm__ __volatile__(
    439. 

  439. 		"	.set	push					\n"
    440. 

  440. 		"	.set	noreorder				\n"
    441. 

  441. 		"	.set	mips3					\n"
    442. 

  442. 		"1:	" __LL	"%0, %1		# test_and_clear_bit	\n"
    443. 

  443. 		"	or	%2, %0, %3				\n"
    444. 

  444. 		"	xor	%2, %3					\n"
    445. 

  445. 		"	" __SC 	"%2, %1					\n"
    446. 

  446. 		"	beqz	%2, 2f					\n"
    447. 

  447. 		"	 and	%2, %0, %3				\n"
    448. 

  448. 		"	.subsection 2					\n"
    449. 

  449. 		"2:	b	1b					\n"
    450. 

  450. 		"	 nop						\n"
    451. 

  451. 		"	.previous					\n"
    452. 

  452. 		"	.set	pop					\n"
    453. 

  453. 		: "=&r" (temp), "=m" (*m), "=&r" (res)
    454. 

  454. 		: "r" (1UL << bit), "m" (*m)
    455. 

  455. 		: "memory");
    456. 

  456. 	} else {
    457. 

  457. 		volatile unsigned long *a = addr;
    458. 

  458. 		unsigned long mask;
    459. 

  459. 		unsigned long flags;
    460. 

  460. 

  461. 		a += nr >> SZLONG_LOG;
    462. 

  462. 		mask = 1UL << bit;
    463. 

  463. 		raw_local_irq_save(flags);
    464. 

  464. 		res = (mask & *a);
    465. 

  465. 		*a &= ~mask;
    466. 

  466. 		raw_local_irq_restore(flags);
    467. 

  467. 	}
    468. 

  468. 

  469. 	smp_llsc_mb();
    470. 

  470. 

  471. 	return res != 0;
    472. 

  472. }
    473. 

  473. 

  474. /*
    475. 

  475.  * test_and_change_bit - Change a bit and return its old value
    476. 

  476.  * @nr: Bit to change
    477. 

  477.  * @addr: Address to count from
    478. 

  478.  *
    479. 

  479.  * This operation is atomic and cannot be reordered.
    480. 

  480.  * It also implies a memory barrier.
    481. 

  481.  */
    482. 

  482. static inline int test_and_change_bit(unsigned long nr,
    483. 

  483. 	volatile unsigned long *addr)
    484. 

  484. {
    485. 

  485. 	unsigned short bit = nr & SZLONG_MASK;
    486. 

  486. 	unsigned long res;
    487. 

  487. 

  488. 	smp_llsc_mb();
    489. 

  489. 

  490. 	if (kernel_uses_llsc && R10000_LLSC_WAR) {
    491. 

  491. 		unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
    492. 

  492. 		unsigned long temp;
    493. 

  493. 

  494. 		__asm__ __volatile__(
    495. 

  495. 		"	.set	mips3					\n"
    496. 

  496. 		"1:	" __LL	"%0, %1		# test_and_change_bit	\n"
    497. 

  497. 		"	xor	%2, %0, %3				\n"
    498. 

  498. 		"	" __SC	"%2, %1					\n"
    499. 

  499. 		"	beqzl	%2, 1b					\n"
    500. 

  500. 		"	and	%2, %0, %3				\n"
    501. 

  501. 		"	.set	mips0					\n"
    502. 

  502. 		: "=&r" (temp), "=m" (*m), "=&r" (res)
    503. 

  503. 		: "r" (1UL << bit), "m" (*m)
    504. 

  504. 		: "memory");
    505. 

  505. 	} else if (kernel_uses_llsc) {
    506. 

  506. 		unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
    507. 

  507. 		unsigned long temp;
    508. 

  508. 

  509. 		__asm__ __volatile__(
    510. 

  510. 		"	.set	push					\n"
    511. 

  511. 		"	.set	noreorder				\n"
    512. 

  512. 		"	.set	mips3					\n"
    513. 

  513. 		"1:	" __LL	"%0, %1		# test_and_change_bit	\n"
    514. 

  514. 		"	xor	%2, %0, %3				\n"
    515. 

  515. 		"	" __SC	"\t%2, %1				\n"
    516. 

  516. 		"	beqz	%2, 2f					\n"
    517. 

  517. 		"	 and	%2, %0, %3				\n"
    518. 

  518. 		"	.subsection 2					\n"
    519. 

  519. 		"2:	b	1b					\n"
    520. 

  520. 		"	 nop						\n"
    521. 

  521. 		"	.previous					\n"
    522. 

  522. 		"	.set	pop					\n"
    523. 

  523. 		: "=&r" (temp), "=m" (*m), "=&r" (res)
    524. 

  524. 		: "r" (1UL << bit), "m" (*m)
    525. 

  525. 		: "memory");
    526. 

  526. 	} else {
    527. 

  527. 		volatile unsigned long *a = addr;
    528. 

  528. 		unsigned long mask;
    529. 

  529. 		unsigned long flags;
    530. 

  530. 

  531. 		a += nr >> SZLONG_LOG;
    532. 

  532. 		mask = 1UL << bit;
    533. 

  533. 		raw_local_irq_save(flags);
    534. 

  534. 		res = (mask & *a);
    535. 

  535. 		*a ^= mask;
    536. 

  536. 		raw_local_irq_restore(flags);
    537. 

  537. 	}
    538. 

  538. 

  539. 	smp_llsc_mb();
    540. 

  540. 

  541. 	return res != 0;
    542. 

  542. }
    543. 

  543. 

  544. #include <asm-generic/bitops/non-atomic.h>
    545. 

  545. 

  546. /*
    547. 

  547.  * __clear_bit_unlock - Clears a bit in memory
    548. 

  548.  * @nr: Bit to clear
    549. 

  549.  * @addr: Address to start counting from
    550. 

  550.  *
    551. 

  551.  * __clear_bit() is non-atomic and implies release semantics before the memory
    552. 

  552.  * operation. It can be used for an unlock if no other CPUs can concurrently
    553. 

  553.  * modify other bits in the word.
    554. 

  554.  */
    555. 

  555. static inline void __clear_bit_unlock(unsigned long nr, volatile unsigned long *addr)
    556. 

  556. {
    557. 

  557. 	smp_mb();
    558. 

  558. 	__clear_bit(nr, addr);
    559. 

  559. }
    560. 

  560. 

  561. /*
    562. 

  562.  * Return the bit position (0..63) of the most significant 1 bit in a word
    563. 

  563.  * Returns -1 if no 1 bit exists
    564. 

  564.  */
    565. 

  565. static inline unsigned long __fls(unsigned long word)
    566. 

  566. {
    567. 

  567. 	int num;
    568. 

  568. 

  569. 	if (BITS_PER_LONG == 32 &&
    570. 

  570. 	    __builtin_constant_p(cpu_has_clo_clz) && cpu_has_clo_clz) {
    571. 

  571. 		__asm__(
    572. 

  572. 		"	.set	push					\n"
    573. 

  573. 		"	.set	mips32					\n"
    574. 

  574. 		"	clz	%0, %1					\n"
    575. 

  575. 		"	.set	pop					\n"
    576. 

  576. 		: "=r" (num)
    577. 

  577. 		: "r" (word));
    578. 

  578. 

  579. 		return 31 - num;
    580. 

  580. 	}
    581. 

  581. 

  582. 	if (BITS_PER_LONG == 64 &&
    583. 

  583. 	    __builtin_constant_p(cpu_has_mips64) && cpu_has_mips64) {
    584. 

  584. 		__asm__(
    585. 

  585. 		"	.set	push					\n"
    586. 

  586. 		"	.set	mips64					\n"
    587. 

  587. 		"	dclz	%0, %1					\n"
    588. 

  588. 		"	.set	pop					\n"
    589. 

  589. 		: "=r" (num)
    590. 

  590. 		: "r" (word));
    591. 

  591. 

  592. 		return 63 - num;
    593. 

  593. 	}
    594. 

  594. 

  595. 	num = BITS_PER_LONG - 1;
    596. 

  596. 

  597. #if BITS_PER_LONG == 64
    598. 

  598. 	if (!(word & (~0ul << 32))) {
    599. 

  599. 		num -= 32;
    600. 

  600. 		word <<= 32;
    601. 

  601. 	}
    602. 

  602. #endif
    603. 

  603. 	if (!(word & (~0ul << (BITS_PER_LONG-16)))) {
    604. 

  604. 		num -= 16;
    605. 

  605. 		word <<= 16;
    606. 

  606. 	}
    607. 

  607. 	if (!(word & (~0ul << (BITS_PER_LONG-8)))) {
    608. 

  608. 		num -= 8;
    609. 

  609. 		word <<= 8;
    610. 

  610. 	}
    611. 

  611. 	if (!(word & (~0ul << (BITS_PER_LONG-4)))) {
    612. 

  612. 		num -= 4;
    613. 

  613. 		word <<= 4;
    614. 

  614. 	}
    615. 

  615. 	if (!(word & (~0ul << (BITS_PER_LONG-2)))) {
    616. 

  616. 		num -= 2;
    617. 

  617. 		word <<= 2;
    618. 

  618. 	}
    619. 

  619. 	if (!(word & (~0ul << (BITS_PER_LONG-1))))
    620. 

  620. 		num -= 1;
    621. 

  621. 	return num;
    622. 

  622. }
    623. 

  623. 

  624. /*
    625. 

  625.  * __ffs - find first bit in word.
    626. 

  626.  * @word: The word to search
    627. 

  627.  *
    628. 

  628.  * Returns 0..SZLONG-1
    629. 

  629.  * Undefined if no bit exists, so code should check against 0 first.
    630. 

  630.  */
    631. 

  631. static inline unsigned long __ffs(unsigned long word)
    632. 

  632. {
    633. 

  633. 	return __fls(word & -word);
    634. 

  634. }
    635. 

  635. 

  636. /*
    637. 

  637.  * fls - find last bit set.
    638. 

  638.  * @word: The word to search
    639. 

  639.  *
    640. 

  640.  * This is defined the same way as ffs.
    641. 

  641.  * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
    642. 

  642.  */
    643. 

  643. static inline int fls(int x)
    644. 

  644. {
    645. 

  645. 	int r;
    646. 

  646. 

  647. 	if (__builtin_constant_p(cpu_has_clo_clz) && cpu_has_clo_clz) {
    648. 

  648. 		__asm__("clz %0, %1" : "=r" (x) : "r" (x));
    649. 

  649. 

  650. 		return 32 - x;
    651. 

  651. 	}
    652. 

  652. 

  653. 	r = 32;
    654. 

  654. 	if (!x)
    655. 

  655. 		return 0;
    656. 

  656. 	if (!(x & 0xffff0000u)) {
    657. 

  657. 		x <<= 16;
    658. 

  658. 		r -= 16;
    659. 

  659. 	}
    660. 

  660. 	if (!(x & 0xff000000u)) {
    661. 

  661. 		x <<= 8;
    662. 

  662. 		r -= 8;
    663. 

  663. 	}
    664. 

  664. 	if (!(x & 0xf0000000u)) {
    665. 

  665. 		x <<= 4;
    666. 

  666. 		r -= 4;
    667. 

  667. 	}
    668. 

  668. 	if (!(x & 0xc0000000u)) {
    669. 

  669. 		x <<= 2;
    670. 

  670. 		r -= 2;
    671. 

  671. 	}
    672. 

  672. 	if (!(x & 0x80000000u)) {
    673. 

  673. 		x <<= 1;
    674. 

  674. 		r -= 1;
    675. 

  675. 	}
    676. 

  676. 	return r;
    677. 

  677. }
    678. 

  678. 

  679. #include <asm-generic/bitops/fls64.h>
    680. 

  680. 

  681. /*
    682. 

  682.  * ffs - find first bit set.
    683. 

  683.  * @word: The word to search
    684. 

  684.  *
    685. 

  685.  * This is defined the same way as
    686. 

  686.  * the libc and compiler builtin ffs routines, therefore
    687. 

  687.  * differs in spirit from the above ffz (man ffs).
    688. 

  688.  */
    689. 

  689. static inline int ffs(int word)
    690. 

  690. {
    691. 

  691. 	if (!word)
    692. 

  692. 		return 0;
    693. 

  693. 

  694. 	return fls(word & -word);
    695. 

  695. }
    696. 

  696. 

  697. #include <asm-generic/bitops/ffz.h>
    698. 

  698. #include <asm-generic/bitops/find.h>
    699. 

  699. 

  700. #ifdef __KERNEL__
    701. 

  701. 

  702. #include <asm-generic/bitops/sched.h>
    703. 

  703. #include <asm-generic/bitops/hweight.h>
    704. 

  704. #include <asm-generic/bitops/ext2-non-atomic.h>
    705. 

  705. #include <asm-generic/bitops/ext2-atomic.h>
    706. 

  706. #include <asm-generic/bitops/minix.h>
    707. 

  707. 

  708. #endif /* __KERNEL__ */
    709. 

  709. 

  710. #endif /* _ASM_BITOPS_H */
    711.