/kern_2.6.32/drivers/usb/gadget/s3c2410_udc.c

http://omnia2droid.googlecode.com/ · C · 2054 lines · 1492 code · 382 blank · 180 comment · 272 complexity · 3d1e267c79d5ddfbb9e93db9c4e4e456 MD5 · raw file

  1. /*
  2. * linux/drivers/usb/gadget/s3c2410_udc.c
  3. *
  4. * Samsung S3C24xx series on-chip full speed USB device controllers
  5. *
  6. * Copyright (C) 2004-2007 Herbert Pötzl - Arnaud Patard
  7. * Additional cleanups by Ben Dooks <ben-linux@fluff.org>
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; either version 2 of the License, or
  12. * (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  22. *
  23. */
  24. #include <linux/module.h>
  25. #include <linux/kernel.h>
  26. #include <linux/delay.h>
  27. #include <linux/ioport.h>
  28. #include <linux/sched.h>
  29. #include <linux/slab.h>
  30. #include <linux/errno.h>
  31. #include <linux/init.h>
  32. #include <linux/timer.h>
  33. #include <linux/list.h>
  34. #include <linux/interrupt.h>
  35. #include <linux/platform_device.h>
  36. #include <linux/clk.h>
  37. #include <linux/gpio.h>
  38. #include <linux/debugfs.h>
  39. #include <linux/seq_file.h>
  40. #include <linux/usb.h>
  41. #include <linux/usb/gadget.h>
  42. #include <asm/byteorder.h>
  43. #include <asm/io.h>
  44. #include <asm/irq.h>
  45. #include <asm/system.h>
  46. #include <asm/unaligned.h>
  47. #include <mach/irqs.h>
  48. #include <mach/hardware.h>
  49. #include <plat/regs-udc.h>
  50. #include <plat/udc.h>
  51. #include "s3c2410_udc.h"
  52. #define DRIVER_DESC "S3C2410 USB Device Controller Gadget"
  53. #define DRIVER_VERSION "29 Apr 2007"
  54. #define DRIVER_AUTHOR "Herbert Pötzl <herbert@13thfloor.at>, " \
  55. "Arnaud Patard <arnaud.patard@rtp-net.org>"
  56. static const char gadget_name[] = "s3c2410_udc";
  57. static const char driver_desc[] = DRIVER_DESC;
  58. static struct s3c2410_udc *the_controller;
  59. static struct clk *udc_clock;
  60. static struct clk *usb_bus_clock;
  61. static void __iomem *base_addr;
  62. static u64 rsrc_start;
  63. static u64 rsrc_len;
  64. static struct dentry *s3c2410_udc_debugfs_root;
  65. static inline u32 udc_read(u32 reg)
  66. {
  67. return readb(base_addr + reg);
  68. }
  69. static inline void udc_write(u32 value, u32 reg)
  70. {
  71. writeb(value, base_addr + reg);
  72. }
  73. static inline void udc_writeb(void __iomem *base, u32 value, u32 reg)
  74. {
  75. writeb(value, base + reg);
  76. }
  77. static struct s3c2410_udc_mach_info *udc_info;
  78. /*************************** DEBUG FUNCTION ***************************/
  79. #define DEBUG_NORMAL 1
  80. #define DEBUG_VERBOSE 2
  81. #ifdef CONFIG_USB_S3C2410_DEBUG
  82. #define USB_S3C2410_DEBUG_LEVEL 0
  83. static uint32_t s3c2410_ticks = 0;
  84. static int dprintk(int level, const char *fmt, ...)
  85. {
  86. static char printk_buf[1024];
  87. static long prevticks;
  88. static int invocation;
  89. va_list args;
  90. int len;
  91. if (level > USB_S3C2410_DEBUG_LEVEL)
  92. return 0;
  93. if (s3c2410_ticks != prevticks) {
  94. prevticks = s3c2410_ticks;
  95. invocation = 0;
  96. }
  97. len = scnprintf(printk_buf,
  98. sizeof(printk_buf), "%1lu.%02d USB: ",
  99. prevticks, invocation++);
  100. va_start(args, fmt);
  101. len = vscnprintf(printk_buf+len,
  102. sizeof(printk_buf)-len, fmt, args);
  103. va_end(args);
  104. return printk(KERN_DEBUG "%s", printk_buf);
  105. }
  106. #else
  107. static int dprintk(int level, const char *fmt, ...)
  108. {
  109. return 0;
  110. }
  111. #endif
  112. static int s3c2410_udc_debugfs_seq_show(struct seq_file *m, void *p)
  113. {
  114. u32 addr_reg,pwr_reg,ep_int_reg,usb_int_reg;
  115. u32 ep_int_en_reg, usb_int_en_reg, ep0_csr;
  116. u32 ep1_i_csr1,ep1_i_csr2,ep1_o_csr1,ep1_o_csr2;
  117. u32 ep2_i_csr1,ep2_i_csr2,ep2_o_csr1,ep2_o_csr2;
  118. addr_reg = udc_read(S3C2410_UDC_FUNC_ADDR_REG);
  119. pwr_reg = udc_read(S3C2410_UDC_PWR_REG);
  120. ep_int_reg = udc_read(S3C2410_UDC_EP_INT_REG);
  121. usb_int_reg = udc_read(S3C2410_UDC_USB_INT_REG);
  122. ep_int_en_reg = udc_read(S3C2410_UDC_EP_INT_EN_REG);
  123. usb_int_en_reg = udc_read(S3C2410_UDC_USB_INT_EN_REG);
  124. udc_write(0, S3C2410_UDC_INDEX_REG);
  125. ep0_csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
  126. udc_write(1, S3C2410_UDC_INDEX_REG);
  127. ep1_i_csr1 = udc_read(S3C2410_UDC_IN_CSR1_REG);
  128. ep1_i_csr2 = udc_read(S3C2410_UDC_IN_CSR2_REG);
  129. ep1_o_csr1 = udc_read(S3C2410_UDC_IN_CSR1_REG);
  130. ep1_o_csr2 = udc_read(S3C2410_UDC_IN_CSR2_REG);
  131. udc_write(2, S3C2410_UDC_INDEX_REG);
  132. ep2_i_csr1 = udc_read(S3C2410_UDC_IN_CSR1_REG);
  133. ep2_i_csr2 = udc_read(S3C2410_UDC_IN_CSR2_REG);
  134. ep2_o_csr1 = udc_read(S3C2410_UDC_IN_CSR1_REG);
  135. ep2_o_csr2 = udc_read(S3C2410_UDC_IN_CSR2_REG);
  136. seq_printf(m, "FUNC_ADDR_REG : 0x%04X\n"
  137. "PWR_REG : 0x%04X\n"
  138. "EP_INT_REG : 0x%04X\n"
  139. "USB_INT_REG : 0x%04X\n"
  140. "EP_INT_EN_REG : 0x%04X\n"
  141. "USB_INT_EN_REG : 0x%04X\n"
  142. "EP0_CSR : 0x%04X\n"
  143. "EP1_I_CSR1 : 0x%04X\n"
  144. "EP1_I_CSR2 : 0x%04X\n"
  145. "EP1_O_CSR1 : 0x%04X\n"
  146. "EP1_O_CSR2 : 0x%04X\n"
  147. "EP2_I_CSR1 : 0x%04X\n"
  148. "EP2_I_CSR2 : 0x%04X\n"
  149. "EP2_O_CSR1 : 0x%04X\n"
  150. "EP2_O_CSR2 : 0x%04X\n",
  151. addr_reg,pwr_reg,ep_int_reg,usb_int_reg,
  152. ep_int_en_reg, usb_int_en_reg, ep0_csr,
  153. ep1_i_csr1,ep1_i_csr2,ep1_o_csr1,ep1_o_csr2,
  154. ep2_i_csr1,ep2_i_csr2,ep2_o_csr1,ep2_o_csr2
  155. );
  156. return 0;
  157. }
  158. static int s3c2410_udc_debugfs_fops_open(struct inode *inode,
  159. struct file *file)
  160. {
  161. return single_open(file, s3c2410_udc_debugfs_seq_show, NULL);
  162. }
  163. static const struct file_operations s3c2410_udc_debugfs_fops = {
  164. .open = s3c2410_udc_debugfs_fops_open,
  165. .read = seq_read,
  166. .llseek = seq_lseek,
  167. .release = single_release,
  168. .owner = THIS_MODULE,
  169. };
  170. /* io macros */
  171. static inline void s3c2410_udc_clear_ep0_opr(void __iomem *base)
  172. {
  173. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  174. udc_writeb(base, S3C2410_UDC_EP0_CSR_SOPKTRDY,
  175. S3C2410_UDC_EP0_CSR_REG);
  176. }
  177. static inline void s3c2410_udc_clear_ep0_sst(void __iomem *base)
  178. {
  179. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  180. writeb(0x00, base + S3C2410_UDC_EP0_CSR_REG);
  181. }
  182. static inline void s3c2410_udc_clear_ep0_se(void __iomem *base)
  183. {
  184. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  185. udc_writeb(base, S3C2410_UDC_EP0_CSR_SSE, S3C2410_UDC_EP0_CSR_REG);
  186. }
  187. static inline void s3c2410_udc_set_ep0_ipr(void __iomem *base)
  188. {
  189. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  190. udc_writeb(base, S3C2410_UDC_EP0_CSR_IPKRDY, S3C2410_UDC_EP0_CSR_REG);
  191. }
  192. static inline void s3c2410_udc_set_ep0_de(void __iomem *base)
  193. {
  194. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  195. udc_writeb(base, S3C2410_UDC_EP0_CSR_DE, S3C2410_UDC_EP0_CSR_REG);
  196. }
  197. inline void s3c2410_udc_set_ep0_ss(void __iomem *b)
  198. {
  199. udc_writeb(b, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  200. udc_writeb(b, S3C2410_UDC_EP0_CSR_SENDSTL, S3C2410_UDC_EP0_CSR_REG);
  201. }
  202. static inline void s3c2410_udc_set_ep0_de_out(void __iomem *base)
  203. {
  204. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  205. udc_writeb(base,(S3C2410_UDC_EP0_CSR_SOPKTRDY
  206. | S3C2410_UDC_EP0_CSR_DE),
  207. S3C2410_UDC_EP0_CSR_REG);
  208. }
  209. static inline void s3c2410_udc_set_ep0_sse_out(void __iomem *base)
  210. {
  211. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  212. udc_writeb(base, (S3C2410_UDC_EP0_CSR_SOPKTRDY
  213. | S3C2410_UDC_EP0_CSR_SSE),
  214. S3C2410_UDC_EP0_CSR_REG);
  215. }
  216. static inline void s3c2410_udc_set_ep0_de_in(void __iomem *base)
  217. {
  218. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  219. udc_writeb(base, (S3C2410_UDC_EP0_CSR_IPKRDY
  220. | S3C2410_UDC_EP0_CSR_DE),
  221. S3C2410_UDC_EP0_CSR_REG);
  222. }
  223. /*------------------------- I/O ----------------------------------*/
  224. /*
  225. * s3c2410_udc_done
  226. */
  227. static void s3c2410_udc_done(struct s3c2410_ep *ep,
  228. struct s3c2410_request *req, int status)
  229. {
  230. unsigned halted = ep->halted;
  231. list_del_init(&req->queue);
  232. if (likely (req->req.status == -EINPROGRESS))
  233. req->req.status = status;
  234. else
  235. status = req->req.status;
  236. ep->halted = 1;
  237. req->req.complete(&ep->ep, &req->req);
  238. ep->halted = halted;
  239. }
  240. static void s3c2410_udc_nuke(struct s3c2410_udc *udc,
  241. struct s3c2410_ep *ep, int status)
  242. {
  243. /* Sanity check */
  244. if (&ep->queue == NULL)
  245. return;
  246. while (!list_empty (&ep->queue)) {
  247. struct s3c2410_request *req;
  248. req = list_entry (ep->queue.next, struct s3c2410_request,
  249. queue);
  250. s3c2410_udc_done(ep, req, status);
  251. }
  252. }
  253. static inline void s3c2410_udc_clear_ep_state(struct s3c2410_udc *dev)
  254. {
  255. unsigned i;
  256. /* hardware SET_{CONFIGURATION,INTERFACE} automagic resets endpoint
  257. * fifos, and pending transactions mustn't be continued in any case.
  258. */
  259. for (i = 1; i < S3C2410_ENDPOINTS; i++)
  260. s3c2410_udc_nuke(dev, &dev->ep[i], -ECONNABORTED);
  261. }
  262. static inline int s3c2410_udc_fifo_count_out(void)
  263. {
  264. int tmp;
  265. tmp = udc_read(S3C2410_UDC_OUT_FIFO_CNT2_REG) << 8;
  266. tmp |= udc_read(S3C2410_UDC_OUT_FIFO_CNT1_REG);
  267. return tmp;
  268. }
  269. /*
  270. * s3c2410_udc_write_packet
  271. */
  272. static inline int s3c2410_udc_write_packet(int fifo,
  273. struct s3c2410_request *req,
  274. unsigned max)
  275. {
  276. unsigned len = min(req->req.length - req->req.actual, max);
  277. u8 *buf = req->req.buf + req->req.actual;
  278. prefetch(buf);
  279. dprintk(DEBUG_VERBOSE, "%s %d %d %d %d\n", __func__,
  280. req->req.actual, req->req.length, len, req->req.actual + len);
  281. req->req.actual += len;
  282. udelay(5);
  283. writesb(base_addr + fifo, buf, len);
  284. return len;
  285. }
  286. /*
  287. * s3c2410_udc_write_fifo
  288. *
  289. * return: 0 = still running, 1 = completed, negative = errno
  290. */
  291. static int s3c2410_udc_write_fifo(struct s3c2410_ep *ep,
  292. struct s3c2410_request *req)
  293. {
  294. unsigned count;
  295. int is_last;
  296. u32 idx;
  297. int fifo_reg;
  298. u32 ep_csr;
  299. idx = ep->bEndpointAddress & 0x7F;
  300. switch (idx) {
  301. default:
  302. idx = 0;
  303. case 0:
  304. fifo_reg = S3C2410_UDC_EP0_FIFO_REG;
  305. break;
  306. case 1:
  307. fifo_reg = S3C2410_UDC_EP1_FIFO_REG;
  308. break;
  309. case 2:
  310. fifo_reg = S3C2410_UDC_EP2_FIFO_REG;
  311. break;
  312. case 3:
  313. fifo_reg = S3C2410_UDC_EP3_FIFO_REG;
  314. break;
  315. case 4:
  316. fifo_reg = S3C2410_UDC_EP4_FIFO_REG;
  317. break;
  318. }
  319. count = s3c2410_udc_write_packet(fifo_reg, req, ep->ep.maxpacket);
  320. /* last packet is often short (sometimes a zlp) */
  321. if (count != ep->ep.maxpacket)
  322. is_last = 1;
  323. else if (req->req.length != req->req.actual || req->req.zero)
  324. is_last = 0;
  325. else
  326. is_last = 2;
  327. /* Only ep0 debug messages are interesting */
  328. if (idx == 0)
  329. dprintk(DEBUG_NORMAL,
  330. "Written ep%d %d.%d of %d b [last %d,z %d]\n",
  331. idx, count, req->req.actual, req->req.length,
  332. is_last, req->req.zero);
  333. if (is_last) {
  334. /* The order is important. It prevents sending 2 packets
  335. * at the same time */
  336. if (idx == 0) {
  337. /* Reset signal => no need to say 'data sent' */
  338. if (! (udc_read(S3C2410_UDC_USB_INT_REG)
  339. & S3C2410_UDC_USBINT_RESET))
  340. s3c2410_udc_set_ep0_de_in(base_addr);
  341. ep->dev->ep0state=EP0_IDLE;
  342. } else {
  343. udc_write(idx, S3C2410_UDC_INDEX_REG);
  344. ep_csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
  345. udc_write(idx, S3C2410_UDC_INDEX_REG);
  346. udc_write(ep_csr | S3C2410_UDC_ICSR1_PKTRDY,
  347. S3C2410_UDC_IN_CSR1_REG);
  348. }
  349. s3c2410_udc_done(ep, req, 0);
  350. is_last = 1;
  351. } else {
  352. if (idx == 0) {
  353. /* Reset signal => no need to say 'data sent' */
  354. if (! (udc_read(S3C2410_UDC_USB_INT_REG)
  355. & S3C2410_UDC_USBINT_RESET))
  356. s3c2410_udc_set_ep0_ipr(base_addr);
  357. } else {
  358. udc_write(idx, S3C2410_UDC_INDEX_REG);
  359. ep_csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
  360. udc_write(idx, S3C2410_UDC_INDEX_REG);
  361. udc_write(ep_csr | S3C2410_UDC_ICSR1_PKTRDY,
  362. S3C2410_UDC_IN_CSR1_REG);
  363. }
  364. }
  365. return is_last;
  366. }
  367. static inline int s3c2410_udc_read_packet(int fifo, u8 *buf,
  368. struct s3c2410_request *req, unsigned avail)
  369. {
  370. unsigned len;
  371. len = min(req->req.length - req->req.actual, avail);
  372. req->req.actual += len;
  373. readsb(fifo + base_addr, buf, len);
  374. return len;
  375. }
  376. /*
  377. * return: 0 = still running, 1 = queue empty, negative = errno
  378. */
  379. static int s3c2410_udc_read_fifo(struct s3c2410_ep *ep,
  380. struct s3c2410_request *req)
  381. {
  382. u8 *buf;
  383. u32 ep_csr;
  384. unsigned bufferspace;
  385. int is_last=1;
  386. unsigned avail;
  387. int fifo_count = 0;
  388. u32 idx;
  389. int fifo_reg;
  390. idx = ep->bEndpointAddress & 0x7F;
  391. switch (idx) {
  392. default:
  393. idx = 0;
  394. case 0:
  395. fifo_reg = S3C2410_UDC_EP0_FIFO_REG;
  396. break;
  397. case 1:
  398. fifo_reg = S3C2410_UDC_EP1_FIFO_REG;
  399. break;
  400. case 2:
  401. fifo_reg = S3C2410_UDC_EP2_FIFO_REG;
  402. break;
  403. case 3:
  404. fifo_reg = S3C2410_UDC_EP3_FIFO_REG;
  405. break;
  406. case 4:
  407. fifo_reg = S3C2410_UDC_EP4_FIFO_REG;
  408. break;
  409. }
  410. if (!req->req.length)
  411. return 1;
  412. buf = req->req.buf + req->req.actual;
  413. bufferspace = req->req.length - req->req.actual;
  414. if (!bufferspace) {
  415. dprintk(DEBUG_NORMAL, "%s: buffer full!\n", __func__);
  416. return -1;
  417. }
  418. udc_write(idx, S3C2410_UDC_INDEX_REG);
  419. fifo_count = s3c2410_udc_fifo_count_out();
  420. dprintk(DEBUG_NORMAL, "%s fifo count : %d\n", __func__, fifo_count);
  421. if (fifo_count > ep->ep.maxpacket)
  422. avail = ep->ep.maxpacket;
  423. else
  424. avail = fifo_count;
  425. fifo_count = s3c2410_udc_read_packet(fifo_reg, buf, req, avail);
  426. /* checking this with ep0 is not accurate as we already
  427. * read a control request
  428. **/
  429. if (idx != 0 && fifo_count < ep->ep.maxpacket) {
  430. is_last = 1;
  431. /* overflowed this request? flush extra data */
  432. if (fifo_count != avail)
  433. req->req.status = -EOVERFLOW;
  434. } else {
  435. is_last = (req->req.length <= req->req.actual) ? 1 : 0;
  436. }
  437. udc_write(idx, S3C2410_UDC_INDEX_REG);
  438. fifo_count = s3c2410_udc_fifo_count_out();
  439. /* Only ep0 debug messages are interesting */
  440. if (idx == 0)
  441. dprintk(DEBUG_VERBOSE, "%s fifo count : %d [last %d]\n",
  442. __func__, fifo_count,is_last);
  443. if (is_last) {
  444. if (idx == 0) {
  445. s3c2410_udc_set_ep0_de_out(base_addr);
  446. ep->dev->ep0state = EP0_IDLE;
  447. } else {
  448. udc_write(idx, S3C2410_UDC_INDEX_REG);
  449. ep_csr = udc_read(S3C2410_UDC_OUT_CSR1_REG);
  450. udc_write(idx, S3C2410_UDC_INDEX_REG);
  451. udc_write(ep_csr & ~S3C2410_UDC_OCSR1_PKTRDY,
  452. S3C2410_UDC_OUT_CSR1_REG);
  453. }
  454. s3c2410_udc_done(ep, req, 0);
  455. } else {
  456. if (idx == 0) {
  457. s3c2410_udc_clear_ep0_opr(base_addr);
  458. } else {
  459. udc_write(idx, S3C2410_UDC_INDEX_REG);
  460. ep_csr = udc_read(S3C2410_UDC_OUT_CSR1_REG);
  461. udc_write(idx, S3C2410_UDC_INDEX_REG);
  462. udc_write(ep_csr & ~S3C2410_UDC_OCSR1_PKTRDY,
  463. S3C2410_UDC_OUT_CSR1_REG);
  464. }
  465. }
  466. return is_last;
  467. }
  468. static int s3c2410_udc_read_fifo_crq(struct usb_ctrlrequest *crq)
  469. {
  470. unsigned char *outbuf = (unsigned char*)crq;
  471. int bytes_read = 0;
  472. udc_write(0, S3C2410_UDC_INDEX_REG);
  473. bytes_read = s3c2410_udc_fifo_count_out();
  474. dprintk(DEBUG_NORMAL, "%s: fifo_count=%d\n", __func__, bytes_read);
  475. if (bytes_read > sizeof(struct usb_ctrlrequest))
  476. bytes_read = sizeof(struct usb_ctrlrequest);
  477. readsb(S3C2410_UDC_EP0_FIFO_REG + base_addr, outbuf, bytes_read);
  478. dprintk(DEBUG_VERBOSE, "%s: len=%d %02x:%02x {%x,%x,%x}\n", __func__,
  479. bytes_read, crq->bRequest, crq->bRequestType,
  480. crq->wValue, crq->wIndex, crq->wLength);
  481. return bytes_read;
  482. }
  483. static int s3c2410_udc_get_status(struct s3c2410_udc *dev,
  484. struct usb_ctrlrequest *crq)
  485. {
  486. u16 status = 0;
  487. u8 ep_num = crq->wIndex & 0x7F;
  488. u8 is_in = crq->wIndex & USB_DIR_IN;
  489. switch (crq->bRequestType & USB_RECIP_MASK) {
  490. case USB_RECIP_INTERFACE:
  491. break;
  492. case USB_RECIP_DEVICE:
  493. status = dev->devstatus;
  494. break;
  495. case USB_RECIP_ENDPOINT:
  496. if (ep_num > 4 || crq->wLength > 2)
  497. return 1;
  498. if (ep_num == 0) {
  499. udc_write(0, S3C2410_UDC_INDEX_REG);
  500. status = udc_read(S3C2410_UDC_IN_CSR1_REG);
  501. status = status & S3C2410_UDC_EP0_CSR_SENDSTL;
  502. } else {
  503. udc_write(ep_num, S3C2410_UDC_INDEX_REG);
  504. if (is_in) {
  505. status = udc_read(S3C2410_UDC_IN_CSR1_REG);
  506. status = status & S3C2410_UDC_ICSR1_SENDSTL;
  507. } else {
  508. status = udc_read(S3C2410_UDC_OUT_CSR1_REG);
  509. status = status & S3C2410_UDC_OCSR1_SENDSTL;
  510. }
  511. }
  512. status = status ? 1 : 0;
  513. break;
  514. default:
  515. return 1;
  516. }
  517. /* Seems to be needed to get it working. ouch :( */
  518. udelay(5);
  519. udc_write(status & 0xFF, S3C2410_UDC_EP0_FIFO_REG);
  520. udc_write(status >> 8, S3C2410_UDC_EP0_FIFO_REG);
  521. s3c2410_udc_set_ep0_de_in(base_addr);
  522. return 0;
  523. }
  524. /*------------------------- usb state machine -------------------------------*/
  525. static int s3c2410_udc_set_halt(struct usb_ep *_ep, int value);
  526. static void s3c2410_udc_handle_ep0_idle(struct s3c2410_udc *dev,
  527. struct s3c2410_ep *ep,
  528. struct usb_ctrlrequest *crq,
  529. u32 ep0csr)
  530. {
  531. int len, ret, tmp;
  532. /* start control request? */
  533. if (!(ep0csr & S3C2410_UDC_EP0_CSR_OPKRDY))
  534. return;
  535. s3c2410_udc_nuke(dev, ep, -EPROTO);
  536. len = s3c2410_udc_read_fifo_crq(crq);
  537. if (len != sizeof(*crq)) {
  538. dprintk(DEBUG_NORMAL, "setup begin: fifo READ ERROR"
  539. " wanted %d bytes got %d. Stalling out...\n",
  540. sizeof(*crq), len);
  541. s3c2410_udc_set_ep0_ss(base_addr);
  542. return;
  543. }
  544. dprintk(DEBUG_NORMAL, "bRequest = %d bRequestType %d wLength = %d\n",
  545. crq->bRequest, crq->bRequestType, crq->wLength);
  546. /* cope with automagic for some standard requests. */
  547. dev->req_std = (crq->bRequestType & USB_TYPE_MASK)
  548. == USB_TYPE_STANDARD;
  549. dev->req_config = 0;
  550. dev->req_pending = 1;
  551. switch (crq->bRequest) {
  552. case USB_REQ_SET_CONFIGURATION:
  553. dprintk(DEBUG_NORMAL, "USB_REQ_SET_CONFIGURATION ... \n");
  554. if (crq->bRequestType == USB_RECIP_DEVICE) {
  555. dev->req_config = 1;
  556. s3c2410_udc_set_ep0_de_out(base_addr);
  557. }
  558. break;
  559. case USB_REQ_SET_INTERFACE:
  560. dprintk(DEBUG_NORMAL, "USB_REQ_SET_INTERFACE ... \n");
  561. if (crq->bRequestType == USB_RECIP_INTERFACE) {
  562. dev->req_config = 1;
  563. s3c2410_udc_set_ep0_de_out(base_addr);
  564. }
  565. break;
  566. case USB_REQ_SET_ADDRESS:
  567. dprintk(DEBUG_NORMAL, "USB_REQ_SET_ADDRESS ... \n");
  568. if (crq->bRequestType == USB_RECIP_DEVICE) {
  569. tmp = crq->wValue & 0x7F;
  570. dev->address = tmp;
  571. udc_write((tmp | S3C2410_UDC_FUNCADDR_UPDATE),
  572. S3C2410_UDC_FUNC_ADDR_REG);
  573. s3c2410_udc_set_ep0_de_out(base_addr);
  574. return;
  575. }
  576. break;
  577. case USB_REQ_GET_STATUS:
  578. dprintk(DEBUG_NORMAL, "USB_REQ_GET_STATUS ... \n");
  579. s3c2410_udc_clear_ep0_opr(base_addr);
  580. if (dev->req_std) {
  581. if (!s3c2410_udc_get_status(dev, crq)) {
  582. return;
  583. }
  584. }
  585. break;
  586. case USB_REQ_CLEAR_FEATURE:
  587. s3c2410_udc_clear_ep0_opr(base_addr);
  588. if (crq->bRequestType != USB_RECIP_ENDPOINT)
  589. break;
  590. if (crq->wValue != USB_ENDPOINT_HALT || crq->wLength != 0)
  591. break;
  592. s3c2410_udc_set_halt(&dev->ep[crq->wIndex & 0x7f].ep, 0);
  593. s3c2410_udc_set_ep0_de_out(base_addr);
  594. return;
  595. case USB_REQ_SET_FEATURE:
  596. s3c2410_udc_clear_ep0_opr(base_addr);
  597. if (crq->bRequestType != USB_RECIP_ENDPOINT)
  598. break;
  599. if (crq->wValue != USB_ENDPOINT_HALT || crq->wLength != 0)
  600. break;
  601. s3c2410_udc_set_halt(&dev->ep[crq->wIndex & 0x7f].ep, 1);
  602. s3c2410_udc_set_ep0_de_out(base_addr);
  603. return;
  604. default:
  605. s3c2410_udc_clear_ep0_opr(base_addr);
  606. break;
  607. }
  608. if (crq->bRequestType & USB_DIR_IN)
  609. dev->ep0state = EP0_IN_DATA_PHASE;
  610. else
  611. dev->ep0state = EP0_OUT_DATA_PHASE;
  612. ret = dev->driver->setup(&dev->gadget, crq);
  613. if (ret < 0) {
  614. if (dev->req_config) {
  615. dprintk(DEBUG_NORMAL, "config change %02x fail %d?\n",
  616. crq->bRequest, ret);
  617. return;
  618. }
  619. if (ret == -EOPNOTSUPP)
  620. dprintk(DEBUG_NORMAL, "Operation not supported\n");
  621. else
  622. dprintk(DEBUG_NORMAL,
  623. "dev->driver->setup failed. (%d)\n", ret);
  624. udelay(5);
  625. s3c2410_udc_set_ep0_ss(base_addr);
  626. s3c2410_udc_set_ep0_de_out(base_addr);
  627. dev->ep0state = EP0_IDLE;
  628. /* deferred i/o == no response yet */
  629. } else if (dev->req_pending) {
  630. dprintk(DEBUG_VERBOSE, "dev->req_pending... what now?\n");
  631. dev->req_pending=0;
  632. }
  633. dprintk(DEBUG_VERBOSE, "ep0state %s\n", ep0states[dev->ep0state]);
  634. }
  635. static void s3c2410_udc_handle_ep0(struct s3c2410_udc *dev)
  636. {
  637. u32 ep0csr;
  638. struct s3c2410_ep *ep = &dev->ep[0];
  639. struct s3c2410_request *req;
  640. struct usb_ctrlrequest crq;
  641. if (list_empty(&ep->queue))
  642. req = NULL;
  643. else
  644. req = list_entry(ep->queue.next, struct s3c2410_request, queue);
  645. /* We make the assumption that S3C2410_UDC_IN_CSR1_REG equal to
  646. * S3C2410_UDC_EP0_CSR_REG when index is zero */
  647. udc_write(0, S3C2410_UDC_INDEX_REG);
  648. ep0csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
  649. dprintk(DEBUG_NORMAL, "ep0csr %x ep0state %s\n",
  650. ep0csr, ep0states[dev->ep0state]);
  651. /* clear stall status */
  652. if (ep0csr & S3C2410_UDC_EP0_CSR_SENTSTL) {
  653. s3c2410_udc_nuke(dev, ep, -EPIPE);
  654. dprintk(DEBUG_NORMAL, "... clear SENT_STALL ...\n");
  655. s3c2410_udc_clear_ep0_sst(base_addr);
  656. dev->ep0state = EP0_IDLE;
  657. return;
  658. }
  659. /* clear setup end */
  660. if (ep0csr & S3C2410_UDC_EP0_CSR_SE) {
  661. dprintk(DEBUG_NORMAL, "... serviced SETUP_END ...\n");
  662. s3c2410_udc_nuke(dev, ep, 0);
  663. s3c2410_udc_clear_ep0_se(base_addr);
  664. dev->ep0state = EP0_IDLE;
  665. }
  666. switch (dev->ep0state) {
  667. case EP0_IDLE:
  668. s3c2410_udc_handle_ep0_idle(dev, ep, &crq, ep0csr);
  669. break;
  670. case EP0_IN_DATA_PHASE: /* GET_DESCRIPTOR etc */
  671. dprintk(DEBUG_NORMAL, "EP0_IN_DATA_PHASE ... what now?\n");
  672. if (!(ep0csr & S3C2410_UDC_EP0_CSR_IPKRDY) && req) {
  673. s3c2410_udc_write_fifo(ep, req);
  674. }
  675. break;
  676. case EP0_OUT_DATA_PHASE: /* SET_DESCRIPTOR etc */
  677. dprintk(DEBUG_NORMAL, "EP0_OUT_DATA_PHASE ... what now?\n");
  678. if ((ep0csr & S3C2410_UDC_EP0_CSR_OPKRDY) && req ) {
  679. s3c2410_udc_read_fifo(ep,req);
  680. }
  681. break;
  682. case EP0_END_XFER:
  683. dprintk(DEBUG_NORMAL, "EP0_END_XFER ... what now?\n");
  684. dev->ep0state = EP0_IDLE;
  685. break;
  686. case EP0_STALL:
  687. dprintk(DEBUG_NORMAL, "EP0_STALL ... what now?\n");
  688. dev->ep0state = EP0_IDLE;
  689. break;
  690. }
  691. }
  692. /*
  693. * handle_ep - Manage I/O endpoints
  694. */
  695. static void s3c2410_udc_handle_ep(struct s3c2410_ep *ep)
  696. {
  697. struct s3c2410_request *req;
  698. int is_in = ep->bEndpointAddress & USB_DIR_IN;
  699. u32 ep_csr1;
  700. u32 idx;
  701. if (likely (!list_empty(&ep->queue)))
  702. req = list_entry(ep->queue.next,
  703. struct s3c2410_request, queue);
  704. else
  705. req = NULL;
  706. idx = ep->bEndpointAddress & 0x7F;
  707. if (is_in) {
  708. udc_write(idx, S3C2410_UDC_INDEX_REG);
  709. ep_csr1 = udc_read(S3C2410_UDC_IN_CSR1_REG);
  710. dprintk(DEBUG_VERBOSE, "ep%01d write csr:%02x %d\n",
  711. idx, ep_csr1, req ? 1 : 0);
  712. if (ep_csr1 & S3C2410_UDC_ICSR1_SENTSTL) {
  713. dprintk(DEBUG_VERBOSE, "st\n");
  714. udc_write(idx, S3C2410_UDC_INDEX_REG);
  715. udc_write(ep_csr1 & ~S3C2410_UDC_ICSR1_SENTSTL,
  716. S3C2410_UDC_IN_CSR1_REG);
  717. return;
  718. }
  719. if (!(ep_csr1 & S3C2410_UDC_ICSR1_PKTRDY) && req) {
  720. s3c2410_udc_write_fifo(ep,req);
  721. }
  722. } else {
  723. udc_write(idx, S3C2410_UDC_INDEX_REG);
  724. ep_csr1 = udc_read(S3C2410_UDC_OUT_CSR1_REG);
  725. dprintk(DEBUG_VERBOSE, "ep%01d rd csr:%02x\n", idx, ep_csr1);
  726. if (ep_csr1 & S3C2410_UDC_OCSR1_SENTSTL) {
  727. udc_write(idx, S3C2410_UDC_INDEX_REG);
  728. udc_write(ep_csr1 & ~S3C2410_UDC_OCSR1_SENTSTL,
  729. S3C2410_UDC_OUT_CSR1_REG);
  730. return;
  731. }
  732. if ((ep_csr1 & S3C2410_UDC_OCSR1_PKTRDY) && req) {
  733. s3c2410_udc_read_fifo(ep,req);
  734. }
  735. }
  736. }
  737. #include <mach/regs-irq.h>
  738. /*
  739. * s3c2410_udc_irq - interrupt handler
  740. */
  741. static irqreturn_t s3c2410_udc_irq(int dummy, void *_dev)
  742. {
  743. struct s3c2410_udc *dev = _dev;
  744. int usb_status;
  745. int usbd_status;
  746. int pwr_reg;
  747. int ep0csr;
  748. int i;
  749. u32 idx;
  750. unsigned long flags;
  751. spin_lock_irqsave(&dev->lock, flags);
  752. /* Driver connected ? */
  753. if (!dev->driver) {
  754. /* Clear interrupts */
  755. udc_write(udc_read(S3C2410_UDC_USB_INT_REG),
  756. S3C2410_UDC_USB_INT_REG);
  757. udc_write(udc_read(S3C2410_UDC_EP_INT_REG),
  758. S3C2410_UDC_EP_INT_REG);
  759. }
  760. /* Save index */
  761. idx = udc_read(S3C2410_UDC_INDEX_REG);
  762. /* Read status registers */
  763. usb_status = udc_read(S3C2410_UDC_USB_INT_REG);
  764. usbd_status = udc_read(S3C2410_UDC_EP_INT_REG);
  765. pwr_reg = udc_read(S3C2410_UDC_PWR_REG);
  766. udc_writeb(base_addr, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  767. ep0csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
  768. dprintk(DEBUG_NORMAL, "usbs=%02x, usbds=%02x, pwr=%02x ep0csr=%02x\n",
  769. usb_status, usbd_status, pwr_reg, ep0csr);
  770. /*
  771. * Now, handle interrupts. There's two types :
  772. * - Reset, Resume, Suspend coming -> usb_int_reg
  773. * - EP -> ep_int_reg
  774. */
  775. /* RESET */
  776. if (usb_status & S3C2410_UDC_USBINT_RESET) {
  777. /* two kind of reset :
  778. * - reset start -> pwr reg = 8
  779. * - reset end -> pwr reg = 0
  780. **/
  781. dprintk(DEBUG_NORMAL, "USB reset csr %x pwr %x\n",
  782. ep0csr, pwr_reg);
  783. dev->gadget.speed = USB_SPEED_UNKNOWN;
  784. udc_write(0x00, S3C2410_UDC_INDEX_REG);
  785. udc_write((dev->ep[0].ep.maxpacket & 0x7ff) >> 3,
  786. S3C2410_UDC_MAXP_REG);
  787. dev->address = 0;
  788. dev->ep0state = EP0_IDLE;
  789. dev->gadget.speed = USB_SPEED_FULL;
  790. /* clear interrupt */
  791. udc_write(S3C2410_UDC_USBINT_RESET,
  792. S3C2410_UDC_USB_INT_REG);
  793. udc_write(idx, S3C2410_UDC_INDEX_REG);
  794. spin_unlock_irqrestore(&dev->lock, flags);
  795. return IRQ_HANDLED;
  796. }
  797. /* RESUME */
  798. if (usb_status & S3C2410_UDC_USBINT_RESUME) {
  799. dprintk(DEBUG_NORMAL, "USB resume\n");
  800. /* clear interrupt */
  801. udc_write(S3C2410_UDC_USBINT_RESUME,
  802. S3C2410_UDC_USB_INT_REG);
  803. if (dev->gadget.speed != USB_SPEED_UNKNOWN
  804. && dev->driver
  805. && dev->driver->resume)
  806. dev->driver->resume(&dev->gadget);
  807. }
  808. /* SUSPEND */
  809. if (usb_status & S3C2410_UDC_USBINT_SUSPEND) {
  810. dprintk(DEBUG_NORMAL, "USB suspend\n");
  811. /* clear interrupt */
  812. udc_write(S3C2410_UDC_USBINT_SUSPEND,
  813. S3C2410_UDC_USB_INT_REG);
  814. if (dev->gadget.speed != USB_SPEED_UNKNOWN
  815. && dev->driver
  816. && dev->driver->suspend)
  817. dev->driver->suspend(&dev->gadget);
  818. dev->ep0state = EP0_IDLE;
  819. }
  820. /* EP */
  821. /* control traffic */
  822. /* check on ep0csr != 0 is not a good idea as clearing in_pkt_ready
  823. * generate an interrupt
  824. */
  825. if (usbd_status & S3C2410_UDC_INT_EP0) {
  826. dprintk(DEBUG_VERBOSE, "USB ep0 irq\n");
  827. /* Clear the interrupt bit by setting it to 1 */
  828. udc_write(S3C2410_UDC_INT_EP0, S3C2410_UDC_EP_INT_REG);
  829. s3c2410_udc_handle_ep0(dev);
  830. }
  831. /* endpoint data transfers */
  832. for (i = 1; i < S3C2410_ENDPOINTS; i++) {
  833. u32 tmp = 1 << i;
  834. if (usbd_status & tmp) {
  835. dprintk(DEBUG_VERBOSE, "USB ep%d irq\n", i);
  836. /* Clear the interrupt bit by setting it to 1 */
  837. udc_write(tmp, S3C2410_UDC_EP_INT_REG);
  838. s3c2410_udc_handle_ep(&dev->ep[i]);
  839. }
  840. }
  841. dprintk(DEBUG_VERBOSE, "irq: %d s3c2410_udc_done.\n", IRQ_USBD);
  842. /* Restore old index */
  843. udc_write(idx, S3C2410_UDC_INDEX_REG);
  844. spin_unlock_irqrestore(&dev->lock, flags);
  845. return IRQ_HANDLED;
  846. }
  847. /*------------------------- s3c2410_ep_ops ----------------------------------*/
  848. static inline struct s3c2410_ep *to_s3c2410_ep(struct usb_ep *ep)
  849. {
  850. return container_of(ep, struct s3c2410_ep, ep);
  851. }
  852. static inline struct s3c2410_udc *to_s3c2410_udc(struct usb_gadget *gadget)
  853. {
  854. return container_of(gadget, struct s3c2410_udc, gadget);
  855. }
  856. static inline struct s3c2410_request *to_s3c2410_req(struct usb_request *req)
  857. {
  858. return container_of(req, struct s3c2410_request, req);
  859. }
  860. /*
  861. * s3c2410_udc_ep_enable
  862. */
  863. static int s3c2410_udc_ep_enable(struct usb_ep *_ep,
  864. const struct usb_endpoint_descriptor *desc)
  865. {
  866. struct s3c2410_udc *dev;
  867. struct s3c2410_ep *ep;
  868. u32 max, tmp;
  869. unsigned long flags;
  870. u32 csr1,csr2;
  871. u32 int_en_reg;
  872. ep = to_s3c2410_ep(_ep);
  873. if (!_ep || !desc || ep->desc
  874. || _ep->name == ep0name
  875. || desc->bDescriptorType != USB_DT_ENDPOINT)
  876. return -EINVAL;
  877. dev = ep->dev;
  878. if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)
  879. return -ESHUTDOWN;
  880. max = le16_to_cpu(desc->wMaxPacketSize) & 0x1fff;
  881. local_irq_save (flags);
  882. _ep->maxpacket = max & 0x7ff;
  883. ep->desc = desc;
  884. ep->halted = 0;
  885. ep->bEndpointAddress = desc->bEndpointAddress;
  886. /* set max packet */
  887. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  888. udc_write(max >> 3, S3C2410_UDC_MAXP_REG);
  889. /* set type, direction, address; reset fifo counters */
  890. if (desc->bEndpointAddress & USB_DIR_IN) {
  891. csr1 = S3C2410_UDC_ICSR1_FFLUSH|S3C2410_UDC_ICSR1_CLRDT;
  892. csr2 = S3C2410_UDC_ICSR2_MODEIN|S3C2410_UDC_ICSR2_DMAIEN;
  893. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  894. udc_write(csr1, S3C2410_UDC_IN_CSR1_REG);
  895. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  896. udc_write(csr2, S3C2410_UDC_IN_CSR2_REG);
  897. } else {
  898. /* don't flush in fifo or it will cause endpoint interrupt */
  899. csr1 = S3C2410_UDC_ICSR1_CLRDT;
  900. csr2 = S3C2410_UDC_ICSR2_DMAIEN;
  901. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  902. udc_write(csr1, S3C2410_UDC_IN_CSR1_REG);
  903. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  904. udc_write(csr2, S3C2410_UDC_IN_CSR2_REG);
  905. csr1 = S3C2410_UDC_OCSR1_FFLUSH | S3C2410_UDC_OCSR1_CLRDT;
  906. csr2 = S3C2410_UDC_OCSR2_DMAIEN;
  907. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  908. udc_write(csr1, S3C2410_UDC_OUT_CSR1_REG);
  909. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  910. udc_write(csr2, S3C2410_UDC_OUT_CSR2_REG);
  911. }
  912. /* enable irqs */
  913. int_en_reg = udc_read(S3C2410_UDC_EP_INT_EN_REG);
  914. udc_write(int_en_reg | (1 << ep->num), S3C2410_UDC_EP_INT_EN_REG);
  915. /* print some debug message */
  916. tmp = desc->bEndpointAddress;
  917. dprintk (DEBUG_NORMAL, "enable %s(%d) ep%x%s-blk max %02x\n",
  918. _ep->name,ep->num, tmp,
  919. desc->bEndpointAddress & USB_DIR_IN ? "in" : "out", max);
  920. local_irq_restore (flags);
  921. s3c2410_udc_set_halt(_ep, 0);
  922. return 0;
  923. }
  924. /*
  925. * s3c2410_udc_ep_disable
  926. */
  927. static int s3c2410_udc_ep_disable(struct usb_ep *_ep)
  928. {
  929. struct s3c2410_ep *ep = to_s3c2410_ep(_ep);
  930. unsigned long flags;
  931. u32 int_en_reg;
  932. if (!_ep || !ep->desc) {
  933. dprintk(DEBUG_NORMAL, "%s not enabled\n",
  934. _ep ? ep->ep.name : NULL);
  935. return -EINVAL;
  936. }
  937. local_irq_save(flags);
  938. dprintk(DEBUG_NORMAL, "ep_disable: %s\n", _ep->name);
  939. ep->desc = NULL;
  940. ep->halted = 1;
  941. s3c2410_udc_nuke (ep->dev, ep, -ESHUTDOWN);
  942. /* disable irqs */
  943. int_en_reg = udc_read(S3C2410_UDC_EP_INT_EN_REG);
  944. udc_write(int_en_reg & ~(1<<ep->num), S3C2410_UDC_EP_INT_EN_REG);
  945. local_irq_restore(flags);
  946. dprintk(DEBUG_NORMAL, "%s disabled\n", _ep->name);
  947. return 0;
  948. }
  949. /*
  950. * s3c2410_udc_alloc_request
  951. */
  952. static struct usb_request *
  953. s3c2410_udc_alloc_request(struct usb_ep *_ep, gfp_t mem_flags)
  954. {
  955. struct s3c2410_request *req;
  956. dprintk(DEBUG_VERBOSE,"%s(%p,%d)\n", __func__, _ep, mem_flags);
  957. if (!_ep)
  958. return NULL;
  959. req = kzalloc (sizeof(struct s3c2410_request), mem_flags);
  960. if (!req)
  961. return NULL;
  962. INIT_LIST_HEAD (&req->queue);
  963. return &req->req;
  964. }
  965. /*
  966. * s3c2410_udc_free_request
  967. */
  968. static void
  969. s3c2410_udc_free_request(struct usb_ep *_ep, struct usb_request *_req)
  970. {
  971. struct s3c2410_ep *ep = to_s3c2410_ep(_ep);
  972. struct s3c2410_request *req = to_s3c2410_req(_req);
  973. dprintk(DEBUG_VERBOSE, "%s(%p,%p)\n", __func__, _ep, _req);
  974. if (!ep || !_req || (!ep->desc && _ep->name != ep0name))
  975. return;
  976. WARN_ON (!list_empty (&req->queue));
  977. kfree(req);
  978. }
  979. /*
  980. * s3c2410_udc_queue
  981. */
  982. static int s3c2410_udc_queue(struct usb_ep *_ep, struct usb_request *_req,
  983. gfp_t gfp_flags)
  984. {
  985. struct s3c2410_request *req = to_s3c2410_req(_req);
  986. struct s3c2410_ep *ep = to_s3c2410_ep(_ep);
  987. struct s3c2410_udc *dev;
  988. u32 ep_csr = 0;
  989. int fifo_count = 0;
  990. unsigned long flags;
  991. if (unlikely (!_ep || (!ep->desc && ep->ep.name != ep0name))) {
  992. dprintk(DEBUG_NORMAL, "%s: invalid args\n", __func__);
  993. return -EINVAL;
  994. }
  995. dev = ep->dev;
  996. if (unlikely (!dev->driver
  997. || dev->gadget.speed == USB_SPEED_UNKNOWN)) {
  998. return -ESHUTDOWN;
  999. }
  1000. local_irq_save (flags);
  1001. if (unlikely(!_req || !_req->complete
  1002. || !_req->buf || !list_empty(&req->queue))) {
  1003. if (!_req)
  1004. dprintk(DEBUG_NORMAL, "%s: 1 X X X\n", __func__);
  1005. else {
  1006. dprintk(DEBUG_NORMAL, "%s: 0 %01d %01d %01d\n",
  1007. __func__, !_req->complete,!_req->buf,
  1008. !list_empty(&req->queue));
  1009. }
  1010. local_irq_restore(flags);
  1011. return -EINVAL;
  1012. }
  1013. _req->status = -EINPROGRESS;
  1014. _req->actual = 0;
  1015. dprintk(DEBUG_VERBOSE, "%s: ep%x len %d\n",
  1016. __func__, ep->bEndpointAddress, _req->length);
  1017. if (ep->bEndpointAddress) {
  1018. udc_write(ep->bEndpointAddress & 0x7F, S3C2410_UDC_INDEX_REG);
  1019. ep_csr = udc_read((ep->bEndpointAddress & USB_DIR_IN)
  1020. ? S3C2410_UDC_IN_CSR1_REG
  1021. : S3C2410_UDC_OUT_CSR1_REG);
  1022. fifo_count = s3c2410_udc_fifo_count_out();
  1023. } else {
  1024. udc_write(0, S3C2410_UDC_INDEX_REG);
  1025. ep_csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
  1026. fifo_count = s3c2410_udc_fifo_count_out();
  1027. }
  1028. /* kickstart this i/o queue? */
  1029. if (list_empty(&ep->queue) && !ep->halted) {
  1030. if (ep->bEndpointAddress == 0 /* ep0 */) {
  1031. switch (dev->ep0state) {
  1032. case EP0_IN_DATA_PHASE:
  1033. if (!(ep_csr&S3C2410_UDC_EP0_CSR_IPKRDY)
  1034. && s3c2410_udc_write_fifo(ep,
  1035. req)) {
  1036. dev->ep0state = EP0_IDLE;
  1037. req = NULL;
  1038. }
  1039. break;
  1040. case EP0_OUT_DATA_PHASE:
  1041. if ((!_req->length)
  1042. || ((ep_csr & S3C2410_UDC_OCSR1_PKTRDY)
  1043. && s3c2410_udc_read_fifo(ep,
  1044. req))) {
  1045. dev->ep0state = EP0_IDLE;
  1046. req = NULL;
  1047. }
  1048. break;
  1049. default:
  1050. local_irq_restore(flags);
  1051. return -EL2HLT;
  1052. }
  1053. } else if ((ep->bEndpointAddress & USB_DIR_IN) != 0
  1054. && (!(ep_csr&S3C2410_UDC_OCSR1_PKTRDY))
  1055. && s3c2410_udc_write_fifo(ep, req)) {
  1056. req = NULL;
  1057. } else if ((ep_csr & S3C2410_UDC_OCSR1_PKTRDY)
  1058. && fifo_count
  1059. && s3c2410_udc_read_fifo(ep, req)) {
  1060. req = NULL;
  1061. }
  1062. }
  1063. /* pio or dma irq handler advances the queue. */
  1064. if (likely (req != 0))
  1065. list_add_tail(&req->queue, &ep->queue);
  1066. local_irq_restore(flags);
  1067. dprintk(DEBUG_VERBOSE, "%s ok\n", __func__);
  1068. return 0;
  1069. }
  1070. /*
  1071. * s3c2410_udc_dequeue
  1072. */
  1073. static int s3c2410_udc_dequeue(struct usb_ep *_ep, struct usb_request *_req)
  1074. {
  1075. struct s3c2410_ep *ep = to_s3c2410_ep(_ep);
  1076. struct s3c2410_udc *udc;
  1077. int retval = -EINVAL;
  1078. unsigned long flags;
  1079. struct s3c2410_request *req = NULL;
  1080. dprintk(DEBUG_VERBOSE, "%s(%p,%p)\n", __func__, _ep, _req);
  1081. if (!the_controller->driver)
  1082. return -ESHUTDOWN;
  1083. if (!_ep || !_req)
  1084. return retval;
  1085. udc = to_s3c2410_udc(ep->gadget);
  1086. local_irq_save (flags);
  1087. list_for_each_entry (req, &ep->queue, queue) {
  1088. if (&req->req == _req) {
  1089. list_del_init (&req->queue);
  1090. _req->status = -ECONNRESET;
  1091. retval = 0;
  1092. break;
  1093. }
  1094. }
  1095. if (retval == 0) {
  1096. dprintk(DEBUG_VERBOSE,
  1097. "dequeued req %p from %s, len %d buf %p\n",
  1098. req, _ep->name, _req->length, _req->buf);
  1099. s3c2410_udc_done(ep, req, -ECONNRESET);
  1100. }
  1101. local_irq_restore (flags);
  1102. return retval;
  1103. }
  1104. /*
  1105. * s3c2410_udc_set_halt
  1106. */
  1107. static int s3c2410_udc_set_halt(struct usb_ep *_ep, int value)
  1108. {
  1109. struct s3c2410_ep *ep = to_s3c2410_ep(_ep);
  1110. u32 ep_csr = 0;
  1111. unsigned long flags;
  1112. u32 idx;
  1113. if (unlikely (!_ep || (!ep->desc && ep->ep.name != ep0name))) {
  1114. dprintk(DEBUG_NORMAL, "%s: inval 2\n", __func__);
  1115. return -EINVAL;
  1116. }
  1117. local_irq_save (flags);
  1118. idx = ep->bEndpointAddress & 0x7F;
  1119. if (idx == 0) {
  1120. s3c2410_udc_set_ep0_ss(base_addr);
  1121. s3c2410_udc_set_ep0_de_out(base_addr);
  1122. } else {
  1123. udc_write(idx, S3C2410_UDC_INDEX_REG);
  1124. ep_csr = udc_read((ep->bEndpointAddress &USB_DIR_IN)
  1125. ? S3C2410_UDC_IN_CSR1_REG
  1126. : S3C2410_UDC_OUT_CSR1_REG);
  1127. if ((ep->bEndpointAddress & USB_DIR_IN) != 0) {
  1128. if (value)
  1129. udc_write(ep_csr | S3C2410_UDC_ICSR1_SENDSTL,
  1130. S3C2410_UDC_IN_CSR1_REG);
  1131. else {
  1132. ep_csr &= ~S3C2410_UDC_ICSR1_SENDSTL;
  1133. udc_write(ep_csr, S3C2410_UDC_IN_CSR1_REG);
  1134. ep_csr |= S3C2410_UDC_ICSR1_CLRDT;
  1135. udc_write(ep_csr, S3C2410_UDC_IN_CSR1_REG);
  1136. }
  1137. } else {
  1138. if (value)
  1139. udc_write(ep_csr | S3C2410_UDC_OCSR1_SENDSTL,
  1140. S3C2410_UDC_OUT_CSR1_REG);
  1141. else {
  1142. ep_csr &= ~S3C2410_UDC_OCSR1_SENDSTL;
  1143. udc_write(ep_csr, S3C2410_UDC_OUT_CSR1_REG);
  1144. ep_csr |= S3C2410_UDC_OCSR1_CLRDT;
  1145. udc_write(ep_csr, S3C2410_UDC_OUT_CSR1_REG);
  1146. }
  1147. }
  1148. }
  1149. ep->halted = value ? 1 : 0;
  1150. local_irq_restore (flags);
  1151. return 0;
  1152. }
  1153. static const struct usb_ep_ops s3c2410_ep_ops = {
  1154. .enable = s3c2410_udc_ep_enable,
  1155. .disable = s3c2410_udc_ep_disable,
  1156. .alloc_request = s3c2410_udc_alloc_request,
  1157. .free_request = s3c2410_udc_free_request,
  1158. .queue = s3c2410_udc_queue,
  1159. .dequeue = s3c2410_udc_dequeue,
  1160. .set_halt = s3c2410_udc_set_halt,
  1161. };
  1162. /*------------------------- usb_gadget_ops ----------------------------------*/
  1163. /*
  1164. * s3c2410_udc_get_frame
  1165. */
  1166. static int s3c2410_udc_get_frame(struct usb_gadget *_gadget)
  1167. {
  1168. int tmp;
  1169. dprintk(DEBUG_VERBOSE, "%s()\n", __func__);
  1170. tmp = udc_read(S3C2410_UDC_FRAME_NUM2_REG) << 8;
  1171. tmp |= udc_read(S3C2410_UDC_FRAME_NUM1_REG);
  1172. return tmp;
  1173. }
  1174. /*
  1175. * s3c2410_udc_wakeup
  1176. */
  1177. static int s3c2410_udc_wakeup(struct usb_gadget *_gadget)
  1178. {
  1179. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1180. return 0;
  1181. }
  1182. /*
  1183. * s3c2410_udc_set_selfpowered
  1184. */
  1185. static int s3c2410_udc_set_selfpowered(struct usb_gadget *gadget, int value)
  1186. {
  1187. struct s3c2410_udc *udc = to_s3c2410_udc(gadget);
  1188. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1189. if (value)
  1190. udc->devstatus |= (1 << USB_DEVICE_SELF_POWERED);
  1191. else
  1192. udc->devstatus &= ~(1 << USB_DEVICE_SELF_POWERED);
  1193. return 0;
  1194. }
  1195. static void s3c2410_udc_disable(struct s3c2410_udc *dev);
  1196. static void s3c2410_udc_enable(struct s3c2410_udc *dev);
  1197. static int s3c2410_udc_set_pullup(struct s3c2410_udc *udc, int is_on)
  1198. {
  1199. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1200. if (udc_info && udc_info->udc_command) {
  1201. if (is_on)
  1202. s3c2410_udc_enable(udc);
  1203. else {
  1204. if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
  1205. if (udc->driver && udc->driver->disconnect)
  1206. udc->driver->disconnect(&udc->gadget);
  1207. }
  1208. s3c2410_udc_disable(udc);
  1209. }
  1210. }
  1211. else
  1212. return -EOPNOTSUPP;
  1213. return 0;
  1214. }
  1215. static int s3c2410_udc_vbus_session(struct usb_gadget *gadget, int is_active)
  1216. {
  1217. struct s3c2410_udc *udc = to_s3c2410_udc(gadget);
  1218. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1219. udc->vbus = (is_active != 0);
  1220. s3c2410_udc_set_pullup(udc, is_active);
  1221. return 0;
  1222. }
  1223. static int s3c2410_udc_pullup(struct usb_gadget *gadget, int is_on)
  1224. {
  1225. struct s3c2410_udc *udc = to_s3c2410_udc(gadget);
  1226. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1227. s3c2410_udc_set_pullup(udc, is_on ? 0 : 1);
  1228. return 0;
  1229. }
  1230. static irqreturn_t s3c2410_udc_vbus_irq(int irq, void *_dev)
  1231. {
  1232. struct s3c2410_udc *dev = _dev;
  1233. unsigned int value;
  1234. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1235. value = gpio_get_value(udc_info->vbus_pin) ? 1 : 0;
  1236. if (udc_info->vbus_pin_inverted)
  1237. value = !value;
  1238. if (value != dev->vbus)
  1239. s3c2410_udc_vbus_session(&dev->gadget, value);
  1240. return IRQ_HANDLED;
  1241. }
  1242. static int s3c2410_vbus_draw(struct usb_gadget *_gadget, unsigned ma)
  1243. {
  1244. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1245. if (udc_info && udc_info->vbus_draw) {
  1246. udc_info->vbus_draw(ma);
  1247. return 0;
  1248. }
  1249. return -ENOTSUPP;
  1250. }
  1251. static const struct usb_gadget_ops s3c2410_ops = {
  1252. .get_frame = s3c2410_udc_get_frame,
  1253. .wakeup = s3c2410_udc_wakeup,
  1254. .set_selfpowered = s3c2410_udc_set_selfpowered,
  1255. .pullup = s3c2410_udc_pullup,
  1256. .vbus_session = s3c2410_udc_vbus_session,
  1257. .vbus_draw = s3c2410_vbus_draw,
  1258. };
  1259. /*------------------------- gadget driver handling---------------------------*/
  1260. /*
  1261. * s3c2410_udc_disable
  1262. */
  1263. static void s3c2410_udc_disable(struct s3c2410_udc *dev)
  1264. {
  1265. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1266. /* Disable all interrupts */
  1267. udc_write(0x00, S3C2410_UDC_USB_INT_EN_REG);
  1268. udc_write(0x00, S3C2410_UDC_EP_INT_EN_REG);
  1269. /* Clear the interrupt registers */
  1270. udc_write(S3C2410_UDC_USBINT_RESET
  1271. | S3C2410_UDC_USBINT_RESUME
  1272. | S3C2410_UDC_USBINT_SUSPEND,
  1273. S3C2410_UDC_USB_INT_REG);
  1274. udc_write(0x1F, S3C2410_UDC_EP_INT_REG);
  1275. /* Good bye, cruel world */
  1276. if (udc_info && udc_info->udc_command)
  1277. udc_info->udc_command(S3C2410_UDC_P_DISABLE);
  1278. /* Set speed to unknown */
  1279. dev->gadget.speed = USB_SPEED_UNKNOWN;
  1280. }
  1281. /*
  1282. * s3c2410_udc_reinit
  1283. */
  1284. static void s3c2410_udc_reinit(struct s3c2410_udc *dev)
  1285. {
  1286. u32 i;
  1287. /* device/ep0 records init */
  1288. INIT_LIST_HEAD (&dev->gadget.ep_list);
  1289. INIT_LIST_HEAD (&dev->gadget.ep0->ep_list);
  1290. dev->ep0state = EP0_IDLE;
  1291. for (i = 0; i < S3C2410_ENDPOINTS; i++) {
  1292. struct s3c2410_ep *ep = &dev->ep[i];
  1293. if (i != 0)
  1294. list_add_tail (&ep->ep.ep_list, &dev->gadget.ep_list);
  1295. ep->dev = dev;
  1296. ep->desc = NULL;
  1297. ep->halted = 0;
  1298. INIT_LIST_HEAD (&ep->queue);
  1299. }
  1300. }
  1301. /*
  1302. * s3c2410_udc_enable
  1303. */
  1304. static void s3c2410_udc_enable(struct s3c2410_udc *dev)
  1305. {
  1306. int i;
  1307. dprintk(DEBUG_NORMAL, "s3c2410_udc_enable called\n");
  1308. /* dev->gadget.speed = USB_SPEED_UNKNOWN; */
  1309. dev->gadget.speed = USB_SPEED_FULL;
  1310. /* Set MAXP for all endpoints */
  1311. for (i = 0; i < S3C2410_ENDPOINTS; i++) {
  1312. udc_write(i, S3C2410_UDC_INDEX_REG);
  1313. udc_write((dev->ep[i].ep.maxpacket & 0x7ff) >> 3,
  1314. S3C2410_UDC_MAXP_REG);
  1315. }
  1316. /* Set default power state */
  1317. udc_write(DEFAULT_POWER_STATE, S3C2410_UDC_PWR_REG);
  1318. /* Enable reset and suspend interrupt interrupts */
  1319. udc_write(S3C2410_UDC_USBINT_RESET | S3C2410_UDC_USBINT_SUSPEND,
  1320. S3C2410_UDC_USB_INT_EN_REG);
  1321. /* Enable ep0 interrupt */
  1322. udc_write(S3C2410_UDC_INT_EP0, S3C2410_UDC_EP_INT_EN_REG);
  1323. /* time to say "hello, world" */
  1324. if (udc_info && udc_info->udc_command)
  1325. udc_info->udc_command(S3C2410_UDC_P_ENABLE);
  1326. }
  1327. /*
  1328. * usb_gadget_register_driver
  1329. */
  1330. int usb_gadget_register_driver(struct usb_gadget_driver *driver)
  1331. {
  1332. struct s3c2410_udc *udc = the_controller;
  1333. int retval;
  1334. dprintk(DEBUG_NORMAL, "usb_gadget_register_driver() '%s'\n",
  1335. driver->driver.name);
  1336. /* Sanity checks */
  1337. if (!udc)
  1338. return -ENODEV;
  1339. if (udc->driver)
  1340. return -EBUSY;
  1341. if (!driver->bind || !driver->setup
  1342. || driver->speed < USB_SPEED_FULL) {
  1343. printk(KERN_ERR "Invalid driver: bind %p setup %p speed %d\n",
  1344. driver->bind, driver->setup, driver->speed);
  1345. return -EINVAL;
  1346. }
  1347. #if defined(MODULE)
  1348. if (!driver->unbind) {
  1349. printk(KERN_ERR "Invalid driver: no unbind method\n");
  1350. return -EINVAL;
  1351. }
  1352. #endif
  1353. /* Hook the driver */
  1354. udc->driver = driver;
  1355. udc->gadget.dev.driver = &driver->driver;
  1356. /* Bind the driver */
  1357. if ((retval = device_add(&udc->gadget.dev)) != 0) {
  1358. printk(KERN_ERR "Error in device_add() : %d\n",retval);
  1359. goto register_error;
  1360. }
  1361. dprintk(DEBUG_NORMAL, "binding gadget driver '%s'\n",
  1362. driver->driver.name);
  1363. if ((retval = driver->bind (&udc->gadget)) != 0) {
  1364. device_del(&udc->gadget.dev);
  1365. goto register_error;
  1366. }
  1367. /* Enable udc */
  1368. s3c2410_udc_enable(udc);
  1369. return 0;
  1370. register_error:
  1371. udc->driver = NULL;
  1372. udc->gadget.dev.driver = NULL;
  1373. return retval;
  1374. }
  1375. /*
  1376. * usb_gadget_unregister_driver
  1377. */
  1378. int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
  1379. {
  1380. struct s3c2410_udc *udc = the_controller;
  1381. if (!udc)
  1382. return -ENODEV;
  1383. if (!driver || driver != udc->driver || !driver->unbind)
  1384. return -EINVAL;
  1385. dprintk(DEBUG_NORMAL,"usb_gadget_register_driver() '%s'\n",
  1386. driver->driver.name);
  1387. driver->unbind(&udc->gadget);
  1388. device_del(&udc->gadget.dev);
  1389. udc->driver = NULL;
  1390. /* Disable udc */
  1391. s3c2410_udc_disable(udc);
  1392. return 0;
  1393. }
  1394. /*---------------------------------------------------------------------------*/
  1395. static struct s3c2410_udc memory = {
  1396. .gadget = {
  1397. .ops = &s3c2410_ops,
  1398. .ep0 = &memory.ep[0].ep,
  1399. .name = gadget_name,
  1400. .dev = {
  1401. .init_name = "gadget",
  1402. },
  1403. },
  1404. /* control endpoint */
  1405. .ep[0] = {
  1406. .num = 0,
  1407. .ep = {
  1408. .name = ep0name,
  1409. .ops = &s3c2410_ep_ops,
  1410. .maxpacket = EP0_FIFO_SIZE,
  1411. },
  1412. .dev = &memory,
  1413. },
  1414. /* first group of endpoints */
  1415. .ep[1] = {
  1416. .num = 1,
  1417. .ep = {
  1418. .name = "ep1-bulk",
  1419. .ops = &s3c2410_ep_ops,
  1420. .maxpacket = EP_FIFO_SIZE,
  1421. },
  1422. .dev = &memory,
  1423. .fifo_size = EP_FIFO_SIZE,
  1424. .bEndpointAddress = 1,
  1425. .bmAttributes = USB_ENDPOINT_XFER_BULK,
  1426. },
  1427. .ep[2] = {
  1428. .num = 2,
  1429. .ep = {
  1430. .name = "ep2-bulk",
  1431. .ops = &s3c2410_ep_ops,
  1432. .maxpacket = EP_FIFO_SIZE,
  1433. },
  1434. .dev = &memory,
  1435. .fifo_size = EP_FIFO_SIZE,
  1436. .bEndpointAddress = 2,
  1437. .bmAttributes = USB_ENDPOINT_XFER_BULK,
  1438. },
  1439. .ep[3] = {
  1440. .num = 3,
  1441. .ep = {
  1442. .name = "ep3-bulk",
  1443. .ops = &s3c2410_ep_ops,
  1444. .maxpacket = EP_FIFO_SIZE,
  1445. },
  1446. .dev = &memory,
  1447. .fifo_size = EP_FIFO_SIZE,
  1448. .bEndpointAddress = 3,
  1449. .bmAttributes = USB_ENDPOINT_XFER_BULK,
  1450. },
  1451. .ep[4] = {
  1452. .num = 4,
  1453. .ep = {
  1454. .name = "ep4-bulk",
  1455. .ops = &s3c2410_ep_ops,
  1456. .maxpacket = EP_FIFO_SIZE,
  1457. },
  1458. .dev = &memory,
  1459. .fifo_size = EP_FIFO_SIZE,
  1460. .bEndpointAddress = 4,
  1461. .bmAttributes = USB_ENDPOINT_XFER_BULK,
  1462. }
  1463. };
  1464. /*
  1465. * probe - binds to the platform device
  1466. */
  1467. static int s3c2410_udc_probe(struct platform_device *pdev)
  1468. {
  1469. struct s3c2410_udc *udc = &memory;
  1470. struct device *dev = &pdev->dev;
  1471. int retval;
  1472. int irq;
  1473. dev_dbg(dev, "%s()\n", __func__);
  1474. usb_bus_clock = clk_get(NULL, "usb-bus-gadget");
  1475. if (IS_ERR(usb_bus_clock)) {
  1476. dev_err(dev, "failed to get usb bus clock source\n");
  1477. return PTR_ERR(usb_bus_clock);
  1478. }
  1479. clk_enable(usb_bus_clock);
  1480. udc_clock = clk_get(NULL, "usb-device");
  1481. if (IS_ERR(udc_clock)) {
  1482. dev_err(dev, "failed to get udc clock source\n");
  1483. return PTR_ERR(udc_clock);
  1484. }
  1485. clk_enable(udc_clock);
  1486. mdelay(10);
  1487. dev_dbg(dev, "got and enabled clocks\n");
  1488. if (strncmp(pdev->name, "s3c2440", 7) == 0) {
  1489. dev_info(dev, "S3C2440: increasing FIFO to 128 bytes\n");
  1490. memory.ep[1].fifo_size = S3C2440_EP_FIFO_SIZE;
  1491. memory.ep[2].fifo_size = S3C2440_EP_FIFO_SIZE;
  1492. memory.ep[3].fifo_size = S3C2440_EP_FIFO_SIZE;
  1493. memory.ep[4].fifo_size = S3C2440_EP_FIFO_SIZE;
  1494. }
  1495. spin_lock_init (&udc->lock);
  1496. udc_info = pdev->dev.platform_data;
  1497. rsrc_start = S3C2410_PA_USBDEV;
  1498. rsrc_len = S3C24XX_SZ_USBDEV;
  1499. if (!request_mem_region(rsrc_start, rsrc_len, gadget_name))
  1500. return -EBUSY;
  1501. base_addr = ioremap(rsrc_start, rsrc_len);
  1502. if (!base_addr) {
  1503. retval = -ENOMEM;
  1504. goto err_mem;
  1505. }
  1506. device_initialize(&udc->gadget.dev);
  1507. udc->gadget.dev.parent = &pdev->dev;
  1508. udc->gadget.dev.dma_mask = pdev->dev.dma_mask;
  1509. the_controller = udc;
  1510. platform_set_drvdata(pdev, udc);
  1511. s3c2410_udc_disable(udc);
  1512. s3c2410_udc_reinit(udc);
  1513. /* irq setup after old hardware state is cleaned up */
  1514. retval = request_irq(IRQ_USBD, s3c2410_udc_irq,
  1515. IRQF_DISABLED, gadget_name, udc);
  1516. if (retval != 0) {
  1517. dev_err(dev, "cannot get irq %i, err %d\n", IRQ_USBD, retval);
  1518. retval = -EBUSY;
  1519. goto err_map;
  1520. }
  1521. dev_dbg(dev, "got irq %i\n", IRQ_USBD);
  1522. if (udc_info && udc_info->vbus_pin > 0) {
  1523. retval = gpio_request(udc_info->vbus_pin, "udc vbus");
  1524. if (retval < 0) {
  1525. dev_err(dev, "cannot claim vbus pin\n");
  1526. goto err_int;
  1527. }
  1528. irq = gpio_to_irq(udc_info->vbus_pin);
  1529. if (irq < 0) {
  1530. dev_err(dev, "no irq for gpio vbus pin\n");
  1531. goto err_gpio_claim;
  1532. }
  1533. retval = request_irq(irq, s3c2410_udc_vbus_irq,
  1534. IRQF_DISABLED | IRQF_TRIGGER_RISING
  1535. | IRQF_TRIGGER_FALLING | IRQF_SHARED,
  1536. gadget_name, udc);
  1537. if (retval != 0) {
  1538. dev_err(dev, "can't get vbus irq %d, err %d\n",
  1539. irq, retval);
  1540. retval = -EBUSY;
  1541. goto err_gpio_claim;
  1542. }
  1543. dev_dbg(dev, "got irq %i\n", irq);
  1544. } else {
  1545. udc->vbus = 1;
  1546. }
  1547. if (s3c2410_udc_debugfs_root) {
  1548. udc->regs_info = debugfs_create_file("registers", S_IRUGO,
  1549. s3c2410_udc_debugfs_root,
  1550. udc, &s3c2410_udc_debugfs_fops);
  1551. if (!udc->regs_info)
  1552. dev_warn(dev, "debugfs file creation failed\n");
  1553. }
  1554. dev_dbg(dev, "probe ok\n");
  1555. return 0;
  1556. err_gpio_claim:
  1557. if (udc_info && udc_info->vbus_pin > 0)
  1558. gpio_free(udc_info->vbus_pin);
  1559. err_int:
  1560. free_irq(IRQ_USBD, udc);
  1561. err_map:
  1562. iounmap(base_addr);
  1563. err_mem:
  1564. release_mem_region(rsrc_start, rsrc_len);
  1565. return retval;
  1566. }
  1567. /*
  1568. * s3c2410_udc_remove
  1569. */
  1570. static int s3c2410_udc_remove(struct platform_device *pdev)
  1571. {
  1572. struct s3c2410_udc *udc = platform_get_drvdata(pdev);
  1573. unsigned int irq;
  1574. dev_dbg(&pdev->dev, "%s()\n", __func__);
  1575. if (udc->driver)
  1576. return -EBUSY;
  1577. debugfs_remove(udc->regs_info);
  1578. if (udc_info && udc_info->vbus_pin > 0) {
  1579. irq = gpio_to_irq(udc_info->vbus_pin);
  1580. free_irq(irq, udc);
  1581. }
  1582. free_irq(IRQ_USBD, udc);
  1583. iounmap(base_addr);
  1584. release_mem_region(rsrc_start, rsrc_len);
  1585. platform_set_drvdata(pdev, NULL);
  1586. if (!IS_ERR(udc_clock) && udc_clock != NULL) {
  1587. clk_disable(udc_clock);
  1588. clk_put(udc_clock);
  1589. udc_clock = NULL;
  1590. }
  1591. if (!IS_ERR(usb_bus_clock) && usb_bus_clock != NULL) {
  1592. clk_disable(usb_bus_clock);
  1593. clk_put(usb_bus_clock);
  1594. usb_bus_clock = NULL;
  1595. }
  1596. dev_dbg(&pdev->dev, "%s: remove ok\n", __func__);
  1597. return 0;
  1598. }
  1599. #ifdef CONFIG_PM
  1600. static int s3c2410_udc_suspend(struct platform_device *pdev, pm_message_t message)
  1601. {
  1602. if (udc_info && udc_info->udc_command)
  1603. udc_info->udc_command(S3C2410_UDC_P_DISABLE);
  1604. return 0;
  1605. }
  1606. static int s3c2410_udc_resume(struct platform_device *pdev)
  1607. {
  1608. if (udc_info && udc_info->udc_command)
  1609. udc_info->udc_command(S3C2410_UDC_P_ENABLE);
  1610. return 0;
  1611. }
  1612. #else
  1613. #define s3c2410_udc_suspend NULL
  1614. #define s3c2410_udc_resume NULL
  1615. #endif
  1616. static struct platform_driver udc_driver_2410 = {
  1617. .driver = {
  1618. .name = "s3c2410-usbgadget",
  1619. .owner = THIS_MODULE,
  1620. },
  1621. .probe = s3c2410_udc_probe,
  1622. .remove = s3c2410_udc_remove,
  1623. .suspend = s3c2410_udc_suspend,
  1624. .resume = s3c2410_udc_resume,
  1625. };
  1626. static struct platform_driver udc_driver_2440 = {
  1627. .driver = {
  1628. .name = "s3c2440-usbgadget",
  1629. .owner = THIS_MODULE,
  1630. },
  1631. .probe = s3c2410_udc_probe,
  1632. .remove = s3c2410_udc_remove,
  1633. .suspend = s3c2410_udc_suspend,
  1634. .resume = s3c2410_udc_resume,
  1635. };
  1636. static int __init udc_init(void)
  1637. {
  1638. int retval;
  1639. dprintk(DEBUG_NORMAL, "%s: version %s\n", gadget_name, DRIVER_VERSION);
  1640. s3c2410_udc_debugfs_root = debugfs_create_dir(gadget_name, NULL);
  1641. if (IS_ERR(s3c2410_udc_debugfs_root)) {
  1642. printk(KERN_ERR "%s: debugfs dir creation failed %ld\n",
  1643. gadget_name, PTR_ERR(s3c2410_udc_debugfs_root));
  1644. s3c2410_udc_debugfs_root = NULL;
  1645. }
  1646. retval = platform_driver_register(&udc_driver_2410);
  1647. if (retval)
  1648. goto err;
  1649. retval = platform_driver_register(&udc_driver_2440);
  1650. if (retval)
  1651. goto err;
  1652. return 0;
  1653. err:
  1654. debugfs_remove(s3c2410_udc_debugfs_root);
  1655. return retval;
  1656. }
  1657. static void __exit udc_exit(void)
  1658. {
  1659. platform_driver_unregister(&udc_driver_2410);
  1660. platform_driver_unregister(&udc_driver_2440);
  1661. debugfs_remove(s3c2410_udc_debugfs_root);
  1662. }
  1663. EXPORT_SYMBOL(usb_gadget_unregister_driver);
  1664. EXPORT_SYMBOL(usb_gadget_register_driver);
  1665. module_init(udc_init);
  1666. module_exit(udc_exit);
  1667. MODULE_AUTHOR(DRIVER_AUTHOR);
  1668. MODULE_DESCRIPTION(DRIVER_DESC);
  1669. MODULE_VERSION(DRIVER_VERSION);
  1670. MODULE_LICENSE("GPL");
  1671. MODULE_ALIAS("platform:s3c2410-usbgadget");
  1672. MODULE_ALIAS("platform:s3c2440-usbgadget");