/kern_oII/drivers/watchdog/s3c2410_wdt.c

http://omnia2droid.googlecode.com/ · C · 551 lines · 384 code · 111 blank · 56 comment · 44 complexity · 3e415d101a4cc54d8e985e1e44682dbd MD5 · raw file

  1. /* linux/drivers/char/watchdog/s3c2410_wdt.c
  2. *
  3. * Copyright (c) 2004 Simtec Electronics
  4. * Ben Dooks <ben@simtec.co.uk>
  5. *
  6. * S3C2410 Watchdog Timer Support
  7. *
  8. * Based on, softdog.c by Alan Cox,
  9. * (c) Copyright 1996 Alan Cox <alan@lxorguk.ukuu.org.uk>
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License as published by
  13. * the Free Software Foundation; either version 2 of the License, or
  14. * (at your option) any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  24. */
  25. #include <linux/module.h>
  26. #include <linux/moduleparam.h>
  27. #include <linux/types.h>
  28. #include <linux/timer.h>
  29. #include <linux/miscdevice.h>
  30. #include <linux/watchdog.h>
  31. #include <linux/fs.h>
  32. #include <linux/init.h>
  33. #include <linux/platform_device.h>
  34. #include <linux/interrupt.h>
  35. #include <linux/clk.h>
  36. #include <linux/uaccess.h>
  37. #include <linux/io.h>
  38. #include <mach/map.h>
  39. #undef S3C_VA_WATCHDOG
  40. #define S3C_VA_WATCHDOG (0)
  41. #include <plat/regs-watchdog.h>
  42. #define PFX "s3c2410-wdt: "
  43. #define CONFIG_S3C2410_WATCHDOG_ATBOOT (0)
  44. #define CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME (15)
  45. static int nowayout = WATCHDOG_NOWAYOUT;
  46. static int tmr_margin = CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME;
  47. static int tmr_atboot = CONFIG_S3C2410_WATCHDOG_ATBOOT;
  48. static int soft_noboot;
  49. static int debug;
  50. module_param(tmr_margin, int, 0);
  51. module_param(tmr_atboot, int, 0);
  52. module_param(nowayout, int, 0);
  53. module_param(soft_noboot, int, 0);
  54. module_param(debug, int, 0);
  55. MODULE_PARM_DESC(tmr_margin, "Watchdog tmr_margin in seconds. default="
  56. __MODULE_STRING(CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME) ")");
  57. MODULE_PARM_DESC(tmr_atboot,
  58. "Watchdog is started at boot time if set to 1, default="
  59. __MODULE_STRING(CONFIG_S3C2410_WATCHDOG_ATBOOT));
  60. MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
  61. __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
  62. MODULE_PARM_DESC(soft_noboot, "Watchdog action, set to 1 to ignore reboots, 0 to reboot (default depends on ONLY_TESTING)");
  63. MODULE_PARM_DESC(debug, "Watchdog debug, set to >1 for debug, (default 0)");
  64. typedef enum close_state {
  65. CLOSE_STATE_NOT,
  66. CLOSE_STATE_ALLOW = 0x4021
  67. } close_state_t;
  68. static unsigned long open_lock;
  69. static struct device *wdt_dev; /* platform device attached to */
  70. static struct resource *wdt_mem;
  71. static struct resource *wdt_irq;
  72. static struct clk *wdt_clock;
  73. static void __iomem *wdt_base;
  74. static unsigned int wdt_count;
  75. static close_state_t allow_close;
  76. static DEFINE_SPINLOCK(wdt_lock);
  77. /* watchdog control routines */
  78. #define DBG(msg...) do { \
  79. if (debug) \
  80. printk(KERN_INFO msg); \
  81. } while (0)
  82. /* functions */
  83. static void s3c2410wdt_keepalive(void)
  84. {
  85. spin_lock(&wdt_lock);
  86. writel(wdt_count, wdt_base + S3C2410_WTCNT);
  87. spin_unlock(&wdt_lock);
  88. }
  89. static void __s3c2410wdt_stop(void)
  90. {
  91. unsigned long wtcon;
  92. wtcon = readl(wdt_base + S3C2410_WTCON);
  93. wtcon &= ~(S3C2410_WTCON_ENABLE | S3C2410_WTCON_RSTEN);
  94. writel(wtcon, wdt_base + S3C2410_WTCON);
  95. }
  96. static void s3c2410wdt_stop(void)
  97. {
  98. spin_lock(&wdt_lock);
  99. __s3c2410wdt_stop();
  100. spin_unlock(&wdt_lock);
  101. }
  102. static void s3c2410wdt_start(void)
  103. {
  104. unsigned long wtcon;
  105. spin_lock(&wdt_lock);
  106. __s3c2410wdt_stop();
  107. wtcon = readl(wdt_base + S3C2410_WTCON);
  108. wtcon |= S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128;
  109. if (soft_noboot) {
  110. wtcon |= S3C2410_WTCON_INTEN;
  111. wtcon &= ~S3C2410_WTCON_RSTEN;
  112. } else {
  113. wtcon &= ~S3C2410_WTCON_INTEN;
  114. wtcon |= S3C2410_WTCON_RSTEN;
  115. }
  116. DBG("%s: wdt_count=0x%08x, wtcon=%08lx\n",
  117. __func__, wdt_count, wtcon);
  118. writel(wdt_count, wdt_base + S3C2410_WTDAT);
  119. writel(wdt_count, wdt_base + S3C2410_WTCNT);
  120. writel(wtcon, wdt_base + S3C2410_WTCON);
  121. spin_unlock(&wdt_lock);
  122. }
  123. static int s3c2410wdt_set_heartbeat(int timeout)
  124. {
  125. unsigned int freq = clk_get_rate(wdt_clock);
  126. unsigned int count;
  127. unsigned int divisor = 1;
  128. unsigned long wtcon;
  129. if (timeout < 1)
  130. return -EINVAL;
  131. freq /= 128;
  132. count = timeout * freq;
  133. DBG("%s: count=%d, timeout=%d, freq=%d\n",
  134. __func__, count, timeout, freq);
  135. /* if the count is bigger than the watchdog register,
  136. then work out what we need to do (and if) we can
  137. actually make this value
  138. */
  139. if (count >= 0x10000) {
  140. for (divisor = 1; divisor <= 0x100; divisor++) {
  141. if ((count / divisor) < 0x10000)
  142. break;
  143. }
  144. if ((count / divisor) >= 0x10000) {
  145. dev_err(wdt_dev, "timeout %d too big\n", timeout);
  146. return -EINVAL;
  147. }
  148. }
  149. tmr_margin = timeout;
  150. DBG("%s: timeout=%d, divisor=%d, count=%d (%08x)\n",
  151. __func__, timeout, divisor, count, count/divisor);
  152. count /= divisor;
  153. wdt_count = count;
  154. /* update the pre-scaler */
  155. wtcon = readl(wdt_base + S3C2410_WTCON);
  156. wtcon &= ~S3C2410_WTCON_PRESCALE_MASK;
  157. wtcon |= S3C2410_WTCON_PRESCALE(divisor-1);
  158. writel(count, wdt_base + S3C2410_WTDAT);
  159. writel(wtcon, wdt_base + S3C2410_WTCON);
  160. return 0;
  161. }
  162. /*
  163. * /dev/watchdog handling
  164. */
  165. static int s3c2410wdt_open(struct inode *inode, struct file *file)
  166. {
  167. if (test_and_set_bit(0, &open_lock))
  168. return -EBUSY;
  169. if (nowayout)
  170. __module_get(THIS_MODULE);
  171. allow_close = CLOSE_STATE_NOT;
  172. /* start the timer */
  173. s3c2410wdt_start();
  174. return nonseekable_open(inode, file);
  175. }
  176. static int s3c2410wdt_release(struct inode *inode, struct file *file)
  177. {
  178. /*
  179. * Shut off the timer.
  180. * Lock it in if it's a module and we set nowayout
  181. */
  182. if (allow_close == CLOSE_STATE_ALLOW)
  183. s3c2410wdt_stop();
  184. else {
  185. dev_err(wdt_dev, "Unexpected close, not stopping watchdog\n");
  186. s3c2410wdt_keepalive();
  187. }
  188. allow_close = CLOSE_STATE_NOT;
  189. clear_bit(0, &open_lock);
  190. return 0;
  191. }
  192. static ssize_t s3c2410wdt_write(struct file *file, const char __user *data,
  193. size_t len, loff_t *ppos)
  194. {
  195. /*
  196. * Refresh the timer.
  197. */
  198. if (len) {
  199. if (!nowayout) {
  200. size_t i;
  201. /* In case it was set long ago */
  202. allow_close = CLOSE_STATE_NOT;
  203. for (i = 0; i != len; i++) {
  204. char c;
  205. if (get_user(c, data + i))
  206. return -EFAULT;
  207. if (c == 'V')
  208. allow_close = CLOSE_STATE_ALLOW;
  209. }
  210. }
  211. s3c2410wdt_keepalive();
  212. }
  213. return len;
  214. }
  215. #define OPTIONS WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE
  216. static const struct watchdog_info s3c2410_wdt_ident = {
  217. .options = OPTIONS,
  218. .firmware_version = 0,
  219. .identity = "S3C2410 Watchdog",
  220. };
  221. static long s3c2410wdt_ioctl(struct file *file, unsigned int cmd,
  222. unsigned long arg)
  223. {
  224. void __user *argp = (void __user *)arg;
  225. int __user *p = argp;
  226. int new_margin;
  227. switch (cmd) {
  228. case WDIOC_GETSUPPORT:
  229. return copy_to_user(argp, &s3c2410_wdt_ident,
  230. sizeof(s3c2410_wdt_ident)) ? -EFAULT : 0;
  231. case WDIOC_GETSTATUS:
  232. case WDIOC_GETBOOTSTATUS:
  233. return put_user(0, p);
  234. case WDIOC_KEEPALIVE:
  235. s3c2410wdt_keepalive();
  236. return 0;
  237. case WDIOC_SETTIMEOUT:
  238. if (get_user(new_margin, p))
  239. return -EFAULT;
  240. if (s3c2410wdt_set_heartbeat(new_margin))
  241. return -EINVAL;
  242. s3c2410wdt_keepalive();
  243. return put_user(tmr_margin, p);
  244. case WDIOC_GETTIMEOUT:
  245. return put_user(tmr_margin, p);
  246. default:
  247. return -ENOTTY;
  248. }
  249. }
  250. /* kernel interface */
  251. static const struct file_operations s3c2410wdt_fops = {
  252. .owner = THIS_MODULE,
  253. .llseek = no_llseek,
  254. .write = s3c2410wdt_write,
  255. .unlocked_ioctl = s3c2410wdt_ioctl,
  256. .open = s3c2410wdt_open,
  257. .release = s3c2410wdt_release,
  258. };
  259. static struct miscdevice s3c2410wdt_miscdev = {
  260. .minor = WATCHDOG_MINOR,
  261. .name = "watchdog",
  262. .fops = &s3c2410wdt_fops,
  263. };
  264. /* interrupt handler code */
  265. static irqreturn_t s3c2410wdt_irq(int irqno, void *param)
  266. {
  267. dev_info(wdt_dev, "watchdog timer expired (irq)\n");
  268. s3c2410wdt_keepalive();
  269. return IRQ_HANDLED;
  270. }
  271. /* device interface */
  272. static int s3c2410wdt_probe(struct platform_device *pdev)
  273. {
  274. struct resource *res;
  275. struct device *dev;
  276. unsigned int wtcon;
  277. int started = 0;
  278. int ret;
  279. int size;
  280. DBG("%s: probe=%p\n", __func__, pdev);
  281. dev = &pdev->dev;
  282. wdt_dev = &pdev->dev;
  283. /* get the memory region for the watchdog timer */
  284. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  285. if (res == NULL) {
  286. dev_err(dev, "no memory resource specified\n");
  287. return -ENOENT;
  288. }
  289. size = (res->end - res->start) + 1;
  290. wdt_mem = request_mem_region(res->start, size, pdev->name);
  291. if (wdt_mem == NULL) {
  292. dev_err(dev, "failed to get memory region\n");
  293. ret = -ENOENT;
  294. goto err_req;
  295. }
  296. wdt_base = ioremap(res->start, size);
  297. if (wdt_base == NULL) {
  298. dev_err(dev, "failed to ioremap() region\n");
  299. ret = -EINVAL;
  300. goto err_req;
  301. }
  302. DBG("probe: mapped wdt_base=%p\n", wdt_base);
  303. wdt_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  304. if (wdt_irq == NULL) {
  305. dev_err(dev, "no irq resource specified\n");
  306. ret = -ENOENT;
  307. goto err_map;
  308. }
  309. ret = request_irq(wdt_irq->start, s3c2410wdt_irq, 0, pdev->name, pdev);
  310. if (ret != 0) {
  311. dev_err(dev, "failed to install irq (%d)\n", ret);
  312. goto err_map;
  313. }
  314. wdt_clock = clk_get(&pdev->dev, "watchdog");
  315. if (IS_ERR(wdt_clock)) {
  316. dev_err(dev, "failed to find watchdog clock source\n");
  317. ret = PTR_ERR(wdt_clock);
  318. goto err_irq;
  319. }
  320. clk_enable(wdt_clock);
  321. /* see if we can actually set the requested timer margin, and if
  322. * not, try the default value */
  323. if (s3c2410wdt_set_heartbeat(tmr_margin)) {
  324. started = s3c2410wdt_set_heartbeat(
  325. CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME);
  326. if (started == 0)
  327. dev_info(dev,
  328. "tmr_margin value out of range, default %d used\n",
  329. CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME);
  330. else
  331. dev_info(dev, "default timer value is out of range, cannot start\n");
  332. }
  333. ret = misc_register(&s3c2410wdt_miscdev);
  334. if (ret) {
  335. dev_err(dev, "cannot register miscdev on minor=%d (%d)\n",
  336. WATCHDOG_MINOR, ret);
  337. goto err_clk;
  338. }
  339. if (tmr_atboot && started == 0) {
  340. dev_info(dev, "starting watchdog timer\n");
  341. s3c2410wdt_start();
  342. } else if (!tmr_atboot) {
  343. /* if we're not enabling the watchdog, then ensure it is
  344. * disabled if it has been left running from the bootloader
  345. * or other source */
  346. s3c2410wdt_stop();
  347. }
  348. /* print out a statement of readiness */
  349. wtcon = readl(wdt_base + S3C2410_WTCON);
  350. dev_info(dev, "watchdog %sactive, reset %sabled, irq %sabled\n",
  351. (wtcon & S3C2410_WTCON_ENABLE) ? "" : "in",
  352. (wtcon & S3C2410_WTCON_RSTEN) ? "" : "dis",
  353. (wtcon & S3C2410_WTCON_INTEN) ? "" : "en");
  354. return 0;
  355. err_clk:
  356. clk_disable(wdt_clock);
  357. clk_put(wdt_clock);
  358. err_irq:
  359. free_irq(wdt_irq->start, pdev);
  360. err_map:
  361. iounmap(wdt_base);
  362. err_req:
  363. release_resource(wdt_mem);
  364. kfree(wdt_mem);
  365. return ret;
  366. }
  367. static int s3c2410wdt_remove(struct platform_device *dev)
  368. {
  369. release_resource(wdt_mem);
  370. kfree(wdt_mem);
  371. wdt_mem = NULL;
  372. free_irq(wdt_irq->start, dev);
  373. wdt_irq = NULL;
  374. clk_disable(wdt_clock);
  375. clk_put(wdt_clock);
  376. wdt_clock = NULL;
  377. iounmap(wdt_base);
  378. misc_deregister(&s3c2410wdt_miscdev);
  379. return 0;
  380. }
  381. static void s3c2410wdt_shutdown(struct platform_device *dev)
  382. {
  383. s3c2410wdt_stop();
  384. }
  385. #ifdef CONFIG_PM
  386. static unsigned long wtcon_save;
  387. static unsigned long wtdat_save;
  388. static int s3c2410wdt_suspend(struct platform_device *dev, pm_message_t state)
  389. {
  390. /* Save watchdog state, and turn it off. */
  391. wtcon_save = readl(wdt_base + S3C2410_WTCON);
  392. wtdat_save = readl(wdt_base + S3C2410_WTDAT);
  393. /* Note that WTCNT doesn't need to be saved. */
  394. s3c2410wdt_stop();
  395. return 0;
  396. }
  397. static int s3c2410wdt_resume(struct platform_device *dev)
  398. {
  399. /* Restore watchdog state. */
  400. writel(wtdat_save, wdt_base + S3C2410_WTDAT);
  401. writel(wtdat_save, wdt_base + S3C2410_WTCNT); /* Reset count */
  402. writel(wtcon_save, wdt_base + S3C2410_WTCON);
  403. printk(KERN_INFO PFX "watchdog %sabled\n",
  404. (wtcon_save & S3C2410_WTCON_ENABLE) ? "en" : "dis");
  405. return 0;
  406. }
  407. #else
  408. #define s3c2410wdt_suspend NULL
  409. #define s3c2410wdt_resume NULL
  410. #endif /* CONFIG_PM */
  411. static struct platform_driver s3c2410wdt_driver = {
  412. .probe = s3c2410wdt_probe,
  413. .remove = s3c2410wdt_remove,
  414. .shutdown = s3c2410wdt_shutdown,
  415. .suspend = s3c2410wdt_suspend,
  416. .resume = s3c2410wdt_resume,
  417. .driver = {
  418. .owner = THIS_MODULE,
  419. .name = "s3c2410-wdt",
  420. },
  421. };
  422. static char banner[] __initdata =
  423. KERN_INFO "S3C2410 Watchdog Timer, (c) 2004 Simtec Electronics\n";
  424. static int __init watchdog_init(void)
  425. {
  426. printk(banner);
  427. return platform_driver_register(&s3c2410wdt_driver);
  428. }
  429. static void __exit watchdog_exit(void)
  430. {
  431. platform_driver_unregister(&s3c2410wdt_driver);
  432. }
  433. module_init(watchdog_init);
  434. module_exit(watchdog_exit);
  435. MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, "
  436. "Dimitry Andric <dimitry.andric@tomtom.com>");
  437. MODULE_DESCRIPTION("S3C2410 Watchdog Device Driver");
  438. MODULE_LICENSE("GPL");
  439. MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
  440. MODULE_ALIAS("platform:s3c2410-wdt");