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/testbed/atapi/atavar.h

http://rtems-atapi.googlecode.com/
C++ Header | 466 lines | 275 code | 65 blank | 126 comment | 0 complexity | 3fd4c5ac4f8b26da3058b243219d33f6 MD5 | raw file
  1/*	$NetBSD: atavar.h,v 1.80 2009/10/19 18:41:12 bouyer Exp $	*/
  2
  3/*
  4 * Copyright (c) 1998, 2001 Manuel Bouyer.
  5 *
  6 * Redistribution and use in source and binary forms, with or without
  7 * modification, are permitted provided that the following conditions
  8 * are met:
  9 * 1. Redistributions of source code must retain the above copyright
 10 *    notice, this list of conditions and the following disclaimer.
 11 * 2. Redistributions in binary form must reproduce the above copyright
 12 *    notice, this list of conditions and the following disclaimer in the
 13 *    documentation and/or other materials provided with the distribution.
 14 *
 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 25 */
 26
 27#ifndef _DEV_ATA_ATAVAR_H_
 28#define	_DEV_ATA_ATAVAR_H_
 29
 30#include <sys/lock.h>
 31#include <rtems/bsd/sys/queue.h>
 32
 33#include "ataconf.h"
 34
 35/* XXX For scsipi_adapter and scsipi_channel. */
 36#include "scsipi/scsipi_all.h"
 37#include "scsipi/atapiconf.h"
 38
 39/*
 40 * Max number of drives per channel.
 41 */
 42#define	ATA_MAXDRIVES		2
 43
 44/*
 45 * Description of a command to be handled by an ATA controller.  These
 46 * commands are queued in a list.
 47 */
 48struct ata_xfer {
 49	volatile u_int c_flags;	/* command state flags */
 50
 51	/* Channel and drive that are to process the request. */
 52	struct ata_channel *c_chp;
 53	int	c_drive;
 54
 55	void	*c_cmd;			/* private request structure pointer */
 56	void	*c_databuf;		/* pointer to data buffer */
 57	int	c_bcount;		/* byte count left */
 58	int	c_skip;			/* bytes already transferred */
 59	int	c_dscpoll;		/* counter for dsc polling (ATAPI) */
 60	int	c_lenoff;		/* offset to c_bcount (ATAPI) */
 61
 62	/* Link on the command queue. */
 63	TAILQ_ENTRY(ata_xfer) c_xferchain;
 64
 65	/* Low-level protocol handlers. */
 66	void	(*c_start)(struct ata_channel *, struct ata_xfer *);
 67	int	(*c_intr)(struct ata_channel *, struct ata_xfer *, int);
 68	void	(*c_kill_xfer)(struct ata_channel *, struct ata_xfer *, int);
 69};
 70
 71/* flags in c_flags */
 72#define	C_ATAPI		0x0001		/* xfer is ATAPI request */
 73#define	C_TIMEOU	0x0002		/* xfer processing timed out */
 74#define	C_POLL		0x0004		/* command is polled */
 75#define	C_DMA		0x0008		/* command uses DMA */
 76#define C_WAIT		0x0010		/* can use tsleep */
 77#define C_WAITACT	0x0020		/* wakeup when active */
 78#define C_FREE		0x0040		/* call ata_free_xfer() asap */
 79#define C_PIOBM		0x0080		/* command uses busmastering PIO */
 80
 81/* reasons for c_kill_xfer() */
 82#define KILL_GONE 1 /* device is gone */
 83#define KILL_RESET 2 /* xfer was reset */
 84
 85/* Per-channel queue of ata_xfers.  May be shared by multiple channels. */
 86struct ata_queue {
 87	TAILQ_HEAD(, ata_xfer) queue_xfer; /* queue of pending commands */
 88	int queue_freeze; /* freeze count for the queue */
 89	struct ata_xfer *active_xfer; /* active command */
 90	int queue_flags;	/* flags for this queue */
 91#define QF_IDLE_WAIT   0x01    /* someone is wants the controller idle */
 92};
 93
 94/* ATA bus instance state information. */
 95struct atabus_softc {
 96	device_t sc_dev;
 97	struct ata_channel *sc_chan;
 98	int sc_flags;
 99#define ATABUSCF_OPEN	0x01
100};
101
102/*
103 * A queue of atabus instances, used to ensure the same bus probe order
104 * for a given hardware configuration at each boot.
105 */
106struct atabus_initq {
107	TAILQ_ENTRY(atabus_initq) atabus_initq;
108	struct atabus_softc *atabus_sc;
109};
110
111//ifdef _KERNEL
112TAILQ_HEAD(atabus_initq_head, atabus_initq);
113extern struct atabus_initq_head atabus_initq_head;
114extern struct simplelock atabus_interlock;
115//#endif /* _KERNEL */
116
117/* High-level functions and structures used by both ATA and ATAPI devices */
118struct ataparams;
119
120/* Datas common to drives and controller drivers */
121struct ata_drive_datas {
122	u_int8_t drive;		/* drive number */
123	int8_t ata_vers;	/* ATA version supported */
124	u_int16_t drive_flags;	/* bitmask for drives present/absent and cap */
125
126#define	DRIVE_ATA	0x0001
127#define	DRIVE_ATAPI	0x0002
128#define	DRIVE_OLD	0x0004
129#define	DRIVE		(DRIVE_ATA|DRIVE_ATAPI|DRIVE_OLD)
130#define	DRIVE_CAP32	0x0008
131#define	DRIVE_DMA	0x0010
132#define	DRIVE_UDMA	0x0020
133#define	DRIVE_MODE	0x0040	/* the drive reported its mode */
134#define	DRIVE_RESET	0x0080	/* reset the drive state at next xfer */
135#define	DRIVE_WAITDRAIN	0x0100	/* device is waiting for the queue to drain */
136#define	DRIVE_ATAPIST	0x0200	/* device is an ATAPI tape drive */
137#define	DRIVE_NOSTREAM	0x0400	/* no stream methods on this drive */
138
139	/*
140	 * Current setting of drive's PIO, DMA and UDMA modes.
141	 * Is initialised by the disks drivers at attach time, and may be
142	 * changed later by the controller's code if needed
143	 */
144	u_int8_t PIO_mode;	/* Current setting of drive's PIO mode */
145#if NATA_DMA
146	u_int8_t DMA_mode;	/* Current setting of drive's DMA mode */
147#if NATA_UDMA
148	u_int8_t UDMA_mode;	/* Current setting of drive's UDMA mode */
149#endif
150#endif
151
152	/* Supported modes for this drive */
153	u_int8_t PIO_cap;	/* supported drive's PIO mode */
154#if NATA_DMA
155	u_int8_t DMA_cap;	/* supported drive's DMA mode */
156#if NATA_UDMA
157	u_int8_t UDMA_cap;	/* supported drive's UDMA mode */
158#endif
159#endif
160
161	/*
162	 * Drive state.
163	 * This is reset to 0 after a channel reset.
164	 */
165	u_int8_t state;
166
167#define RESET          0
168#define READY          1
169
170#if NATA_DMA
171	/* numbers of xfers and DMA errs. Used by ata_dmaerr() */
172	u_int8_t n_dmaerrs;
173	u_int32_t n_xfers;
174
175	/* Downgrade after NERRS_MAX errors in at most NXFER xfers */
176#define NERRS_MAX 4
177#define NXFER 4000
178#endif
179
180	/* Callbacks into the drive's driver. */
181	void	(*drv_done)(void *);	/* transfer is done */
182
183	device_t drv_softc;	/* ATA drives softc, if any */
184	void *chnl_softc;		/* channel softc */
185};
186
187/* User config flags that force (or disable) the use of a mode */
188#define ATA_CONFIG_PIO_MODES	0x0007
189#define ATA_CONFIG_PIO_SET	0x0008
190#define ATA_CONFIG_PIO_OFF	0
191#define ATA_CONFIG_DMA_MODES	0x0070
192#define ATA_CONFIG_DMA_SET	0x0080
193#define ATA_CONFIG_DMA_DISABLE	0x0070
194#define ATA_CONFIG_DMA_OFF	4
195#define ATA_CONFIG_UDMA_MODES	0x0700
196#define ATA_CONFIG_UDMA_SET	0x0800
197#define ATA_CONFIG_UDMA_DISABLE	0x0700
198#define ATA_CONFIG_UDMA_OFF	8
199
200/*
201 * Parameters/state needed by the controller to perform an ATA bio.
202 */
203struct ata_bio {
204	volatile u_int16_t flags;/* cmd flags */
205#define	ATA_NOSLEEP	0x0001	/* Can't sleep */
206#define	ATA_POLL	0x0002	/* poll for completion */
207#define	ATA_ITSDONE	0x0004	/* the transfer is as done as it gets */
208#define	ATA_SINGLE	0x0008	/* transfer must be done in singlesector mode */
209#define	ATA_LBA		0x0010	/* transfer uses LBA addressing */
210#define	ATA_READ	0x0020	/* transfer is a read (otherwise a write) */
211#define	ATA_CORR	0x0040	/* transfer had a corrected error */
212#define	ATA_LBA48	0x0080	/* transfer uses 48-bit LBA addressing */
213	int		multi;	/* # of blocks to transfer in multi-mode */
214	struct disklabel *lp;	/* pointer to drive's label info */
215	daddr_t		blkno;	/* block addr */
216	daddr_t		blkdone;/* number of blks transferred */
217	daddr_t		nblks;	/* number of block currently transferring */
218	int		nbytes;	/* number of bytes currently transferring */
219	long		bcount;	/* total number of bytes */
220	char		*databuf;/* data buffer address */
221	volatile int	error;
222#define	NOERROR 	0	/* There was no error (r_error invalid) */
223#define	ERROR		1	/* check r_error */
224#define	ERR_DF		2	/* Drive fault */
225#define	ERR_DMA		3	/* DMA error */
226#define	TIMEOUT		4	/* device timed out */
227#define	ERR_NODEV	5	/* device has been gone */
228#define ERR_RESET	6	/* command was terminated by channel reset */
229	u_int8_t	r_error;/* copy of error register */
230	daddr_t		badsect[127];/* 126 plus trailing -1 marker */
231};
232
233/*
234 * ATA/ATAPI commands description
235 *
236 * This structure defines the interface between the ATA/ATAPI device driver
237 * and the controller for short commands. It contains the command's parameter,
238 * the len of data's to read/write (if any), and a function to call upon
239 * completion.
240 * If no sleep is allowed, the driver can poll for command completion.
241 * Once the command completed, if the error registed is valid, the flag
242 * AT_ERROR is set and the error register value is copied to r_error .
243 * A separate interface is needed for read/write or ATAPI packet commands
244 * (which need multiple interrupts per commands).
245 */
246struct ata_command {
247	u_int8_t r_command;	/* Parameters to upload to registers */
248	u_int8_t r_head;
249	u_int16_t r_cyl;
250	u_int8_t r_sector;
251	u_int8_t r_count;
252	u_int8_t r_features;
253	u_int8_t r_st_bmask;	/* status register mask to wait for before
254				   command */
255	u_int8_t r_st_pmask;	/* status register mask to wait for after
256				   command */
257	u_int8_t r_error;	/* error register after command done */
258	volatile u_int16_t flags;
259
260#define AT_READ     0x0001 /* There is data to read */
261#define AT_WRITE    0x0002 /* There is data to write (excl. with AT_READ) */
262#define AT_WAIT     0x0008 /* wait in controller code for command completion */
263#define AT_POLL     0x0010 /* poll for command completion (no interrupts) */
264#define AT_DONE     0x0020 /* command is done */
265#define AT_XFDONE   0x0040 /* data xfer is done */
266#define AT_ERROR    0x0080 /* command is done with error */
267#define AT_TIMEOU   0x0100 /* command timed out */
268#define AT_DF       0x0200 /* Drive fault */
269#define AT_RESET    0x0400 /* command terminated by channel reset */
270#define AT_GONE     0x0800 /* command terminated because device is gone */
271#define AT_READREG  0x1000 /* Read registers on completion */
272
273	int timeout;		/* timeout (in ms) */
274	void *data;		/* Data buffer address */
275	int bcount;		/* number of bytes to transfer */
276	void (*callback)(void *); /* command to call once command completed */
277	void *callback_arg;	/* argument passed to *callback() */
278};
279
280/*
281 * ata_bustype.  The first field must be compatible with scsipi_bustype,
282 * as it's used for autoconfig by both ata and atapi drivers.
283 */
284struct ata_bustype {
285	int	bustype_type;	/* symbolic name of type */
286	int	(*ata_bio)(struct ata_drive_datas *, struct ata_bio *);
287	void	(*ata_reset_drive)(struct ata_drive_datas *, int);
288	void	(*ata_reset_channel)(struct ata_channel *, int);
289/* extra flags for ata_reset_*(), in addition to AT_* */
290#define AT_RST_EMERG 0x10000 /* emergency - e.g. for a dump */
291#define	AT_RST_NOCMD 0x20000 /* XXX has to go - temporary until we have tagged queuing */
292
293	int	(*ata_exec_command)(struct ata_drive_datas *,
294				    struct ata_command *);
295
296#define	ATACMD_COMPLETE		0x01
297#define	ATACMD_QUEUED		0x02
298#define	ATACMD_TRY_AGAIN	0x03
299
300	int	(*ata_get_params)(struct ata_drive_datas *, u_int8_t,
301				  struct ataparams *);
302	int	(*ata_addref)(struct ata_drive_datas *);
303	void	(*ata_delref)(struct ata_drive_datas *);
304	void	(*ata_killpending)(struct ata_drive_datas *);
305};
306
307/* bustype_type */	/* XXX XXX XXX */
308/* #define SCSIPI_BUSTYPE_SCSI	0 */
309/* #define SCSIPI_BUSTYPE_ATAPI	1 */
310#define	SCSIPI_BUSTYPE_ATA	2
311
312/*
313 * Describe an ATA device.  Has to be compatible with scsipi_channel, so
314 * start with a pointer to ata_bustype.
315 */
316struct ata_device {
317	const struct ata_bustype *adev_bustype;
318	int adev_channel;
319	int adev_openings;
320	struct ata_drive_datas *adev_drv_data;
321};
322
323/*
324 * Per-channel data
325 */
326struct ata_channel {
327	struct callout ch_callout;	/* callout handle */
328	int ch_channel;			/* location */
329	struct atac_softc *ch_atac;	/* ATA controller softc */
330
331	/* Our state */
332	volatile int ch_flags;
333#define ATACH_SHUTDOWN 0x02	/* channel is shutting down */
334#define ATACH_IRQ_WAIT 0x10	/* controller is waiting for irq */
335#define ATACH_DMA_WAIT 0x20	/* controller is waiting for DMA */
336#define ATACH_PIOBM_WAIT 0x40	/* controller is waiting for busmastering PIO */
337#define	ATACH_DISABLED 0x80	/* channel is disabled */
338#define ATACH_TH_RUN   0x100	/* the kernel thread is working */
339#define ATACH_TH_RESET 0x200	/* someone ask the thread to reset */
340	u_int8_t ch_status;	/* copy of status register */
341	u_int8_t ch_error;	/* copy of error register */
342
343	/* for the reset callback */
344	int ch_reset_flags;
345
346	/* per-drive info */
347	int ch_ndrive;
348	struct ata_drive_datas ch_drive[ATA_MAXDRIVES];
349
350	device_t atabus;	/* self */
351
352	/* ATAPI children */
353	device_t atapibus;
354	struct scsipi_channel ch_atapi_channel;
355
356	/* ATA children */
357	device_t ata_drives[ATA_MAXDRIVES];
358
359	/*
360	 * Channel queues.  May be the same for all channels, if hw
361	 * channels are not independent.
362	 */
363	struct ata_queue *ch_queue;
364
365	/* The channel kernel thread */
366	struct lwp *ch_thread;
367};
368
369/*
370 * ATA controller softc.
371 *
372 * This contains a bunch of generic info that all ATA controllers need
373 * to have.
374 *
375 * XXX There is still some lingering wdc-centricity here.
376 */
377struct atac_softc {
378	device_t atac_dev;		/* generic device info */
379
380	int	atac_cap;		/* controller capabilities */
381
382#define	ATAC_CAP_DATA16	0x0001		/* can do 16-bit data access */
383#define	ATAC_CAP_DATA32	0x0002		/* can do 32-bit data access */
384#define	ATAC_CAP_DMA	0x0008		/* can do ATA DMA modes */
385#define	ATAC_CAP_UDMA	0x0010		/* can do ATA Ultra DMA modes */
386#define	ATAC_CAP_PIOBM	0x0020		/* can do busmastering PIO transfer */
387#define	ATAC_CAP_ATA_NOSTREAM 0x0040	/* don't use stream funcs on ATA */
388#define	ATAC_CAP_ATAPI_NOSTREAM 0x0080	/* don't use stream funcs on ATAPI */
389#define	ATAC_CAP_NOIRQ	0x1000		/* controller never interrupts */
390#define	ATAC_CAP_RAID	0x4000		/* controller "supports" RAID */
391
392	uint8_t	atac_pio_cap;		/* highest PIO mode supported */
393#if NATA_DMA
394	uint8_t	atac_dma_cap;		/* highest DMA mode supported */
395#if NATA_UDMA
396	uint8_t	atac_udma_cap;		/* highest UDMA mode supported */
397#endif
398#endif
399
400	/* Array of pointers to channel-specific data. */
401	struct ata_channel **atac_channels;
402	int		     atac_nchannels;
403
404	const struct ata_bustype *atac_bustype_ata;
405
406	/*
407	 * Glue between ATA and SCSIPI for the benefit of ATAPI.
408	 *
409	 * Note: The reference count here is used for both ATA and ATAPI
410	 * devices.
411	 */
412	struct atapi_adapter atac_atapi_adapter;
413	void (*atac_atapibus_attach)(struct atabus_softc *);
414
415	/* Driver callback to probe for drives. */
416	void (*atac_probe)(struct ata_channel *);
417
418	/* Optional callbacks to lock/unlock hardware. */
419	int  (*atac_claim_hw)(struct ata_channel *, int);
420	void (*atac_free_hw)(struct ata_channel *);
421
422	/*
423	 * Optional callbacks to set drive mode.  Required for anything
424	 * but basic PIO operation.
425	 */
426	void (*atac_set_modes)(struct ata_channel *);
427};
428
429#ifdef _KERNEL
430void	ata_channel_attach(struct ata_channel *);
431int	atabusprint(void *aux, const char *);
432int	ataprint(void *aux, const char *);
433
434struct ataparams;
435int	ata_get_params(struct ata_drive_datas *, u_int8_t, struct ataparams *);
436int	ata_set_mode(struct ata_drive_datas *, u_int8_t, u_int8_t);
437/* return code for these cmds */
438#define CMD_OK    0
439#define CMD_ERR   1
440#define CMD_AGAIN 2
441
442struct ata_xfer *ata_get_xfer(int);
443void	ata_free_xfer(struct ata_channel *, struct ata_xfer *);
444#define	ATAXF_CANSLEEP	0x00
445#define	ATAXF_NOSLEEP	0x01
446
447void	ata_exec_xfer(struct ata_channel *, struct ata_xfer *);
448void	ata_kill_pending(struct ata_drive_datas *);
449void	ata_reset_channel(struct ata_channel *, int);
450
451int	ata_addref(struct ata_channel *);
452void	ata_delref(struct ata_channel *);
453void	atastart(struct ata_channel *);
454void	ata_print_modes(struct ata_channel *);
455#if NATA_DMA
456int	ata_downgrade_mode(struct ata_drive_datas *, int);
457#endif
458void	ata_probe_caps(struct ata_drive_datas *);
459
460#if NATA_DMA
461void	ata_dmaerr(struct ata_drive_datas *, int);
462#endif
463void	ata_queue_idle(struct ata_queue *);
464#endif /* _KERNEL */
465
466#endif /* _DEV_ATA_ATAVAR_H_ */