/testbed/ic/wdcvar.h

  1/*	$NetBSD: wdcvar.h,v 1.89 2008/04/28 20:23:51 martin Exp $	*/
  2
  3/*-
  4 * Copyright (c) 1998, 2003, 2004 The NetBSD Foundation, Inc.
  5 * All rights reserved.
  6 *
  7 * This code is derived from software contributed to The NetBSD Foundation
  8 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer.
  9 *
 10 * Redistribution and use in source and binary forms, with or without
 11 * modification, are permitted provided that the following conditions
 12 * are met:
 13 * 1. Redistributions of source code must retain the above copyright
 14 *	notice, this list of conditions and the following disclaimer.
 15 * 2. Redistributions in binary form must reproduce the above copyright
 16 *	notice, this list of conditions and the following disclaimer in the
 17 *	documentation and/or other materials provided with the distribution.
 18 *
 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 22 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 29 * POSSIBILITY OF SUCH DAMAGE.
 30 */
 31
 32#ifndef _DEV_IC_WDCVAR_H_
 33#define	_DEV_IC_WDCVAR_H_
 34
 35#include "../sys/callout.h"
 36
 37#include "../atapi/ataconf.h"
 38#include "wdcreg.h"
 39
 40#define	WAITTIME    (10 * hz)    /* time to wait for a completion */
 41	/* this is a lot for hard drives, but not for cdroms */
 42
 43#define WDC_NREG	8 /* number of command registers */
 44#define	WDC_NSHADOWREG	2 /* number of command "shadow" registers */
 45
 46struct wdc_regs {
 47	/* Our registers */
 48	bus_space_tag_t       cmd_iot;
 49	bus_space_handle_t    cmd_baseioh;
 50	bus_space_handle_t    cmd_iohs[WDC_NREG+WDC_NSHADOWREG];
 51	bus_space_tag_t       ctl_iot;
 52	bus_space_handle_t    ctl_ioh;
 53
 54	/* data32{iot,ioh} are only used for 32-bit data xfers */
 55	bus_space_tag_t       data32iot;
 56	bus_space_handle_t    data32ioh;
 57
 58	/* SATA native registers */
 59	bus_space_tag_t       sata_iot;
 60	bus_space_handle_t    sata_baseioh;
 61	bus_space_handle_t    sata_control;
 62	bus_space_handle_t    sata_status;
 63	bus_space_handle_t    sata_error;
 64
 65};
 66
 67/*
 68 * Per-controller data
 69 */
 70struct wdc_softc {
 71	struct atac_softc sc_atac;	/* generic ATA controller info */
 72
 73	struct wdc_regs *regs;		/* register array (per-channel) */
 74
 75	int           cap;		/* controller capabilities */
 76#define WDC_CAPABILITY_NO_EXTRA_RESETS 0x0100 /* only reset once */
 77#define WDC_CAPABILITY_PREATA	0x0200	/* ctrl can be a pre-ata one */
 78#define WDC_CAPABILITY_WIDEREGS 0x0400  /* Ctrl has wide (16bit) registers  */
 79
 80#if NATA_DMA || NATA_PIOBM
 81	/* if WDC_CAPABILITY_DMA set in 'cap' */
 82	void            *dma_arg;
 83	int            (*dma_init)(void *, int, int, void *, size_t, int);
 84	void           (*dma_start)(void *, int, int);
 85	int            (*dma_finish)(void *, int, int, int);
 86#if NATA_PIOBM
 87	void           (*piobm_start)(void *, int, int, int, int, int);
 88	void           (*piobm_done)(void *, int, int);
 89#endif
 90/* flags passed to dma_init */
 91#define WDC_DMA_READ		0x01
 92#define WDC_DMA_IRQW		0x02
 93#define WDC_DMA_LBA48		0x04
 94#define WDC_DMA_PIOBM_ATA	0x08
 95#define WDC_DMA_PIOBM_ATAPI	0x10
 96#if NATA_PIOBM
 97/* flags passed to piobm_start */
 98#define WDC_PIOBM_XFER_IRQ	0x01
 99#endif
100
101/* values passed to dma_finish */
102#define WDC_DMAEND_END	0	/* check for proper end of a DMA xfer */
103#define WDC_DMAEND_ABRT 1	/* abort a DMA xfer, verbose */
104#define WDC_DMAEND_ABRT_QUIET 2	/* abort a DMA xfer, quiet */
105
106	int		dma_status; /* status returned from dma_finish() */
107#define WDC_DMAST_NOIRQ	0x01	/* missing IRQ */
108#define WDC_DMAST_ERR	0x02	/* DMA error */
109#define WDC_DMAST_UNDER	0x04	/* DMA underrun */
110#endif	/* NATA_DMA || NATA_PIOBM */
111
112	/* Optional callback to select drive. */
113	void		(*select)(struct ata_channel *,int);
114
115	/* Optional callback to ack IRQ. */
116	void		(*irqack)(struct ata_channel *);
117
118	/* Optional callback to perform a bus reset */
119	void		(*reset)(struct ata_channel *, int);
120
121	/* overridden if the backend has a different data transfer method */
122	void	(*datain_pio)(struct ata_channel *, int, void *, size_t);
123	void	(*dataout_pio)(struct ata_channel *, int, void *, size_t);
124};
125
126/* Given an ata_channel, get the wdc_softc. */
127#define	CHAN_TO_WDC(chp)	((struct wdc_softc *)(chp)->ch_atac)
128
129/* Given an ata_channel, get the wdc_regs. */
130#define	CHAN_TO_WDC_REGS(chp)	(&CHAN_TO_WDC(chp)->regs[(chp)->ch_channel])
131
132/*
133 * Public functions which can be called by ATA or ATAPI specific parts,
134 * or bus-specific backends.
135 */
136
137void	wdc_allocate_regs(struct wdc_softc *);
138void	wdc_init_shadow_regs(struct ata_channel *);
139
140int	wdcprobe(struct ata_channel *);
141void	wdcattach(struct ata_channel *);
142int	wdcdetach(device_t, int);
143void	wdc_childdetached(device_t, device_t);
144int	wdcactivate(device_t, enum devact);
145int	wdcintr(void *);
146
147void	wdc_sataprobe(struct ata_channel *);
148void	wdc_drvprobe(struct ata_channel *);
149
150void	wdcrestart(void*);
151
152int	wdcwait(struct ata_channel *, int, int, int, int);
153#define WDCWAIT_OK	0  /* we have what we asked */
154#define WDCWAIT_TOUT	-1 /* timed out */
155#define WDCWAIT_THR	1  /* return, the kernel thread has been awakened */
156
157void	wdcbit_bucket(struct ata_channel *, int);
158
159int	wdc_dmawait(struct ata_channel *, struct ata_xfer *, int);
160void	wdccommand(struct ata_channel *, u_int8_t, u_int8_t, u_int16_t,
161		   u_int8_t, u_int8_t, u_int8_t, u_int8_t);
162void	wdccommandext(struct ata_channel *, u_int8_t, u_int8_t, u_int64_t,
163		      u_int16_t);
164void	wdccommandshort(struct ata_channel *, int, int);
165void	wdctimeout(void *arg);
166void	wdc_reset_drive(struct ata_drive_datas *, int);
167void	wdc_reset_channel(struct ata_channel *, int);
168void	wdc_do_reset(struct ata_channel *, int);
169
170int	wdc_exec_command(struct ata_drive_datas *, struct ata_command*);
171
172/*
173 * ST506 spec says that if READY or SEEKCMPLT go off, then the read or write
174 * command is aborted.
175 */
176#define wdc_wait_for_drq(chp, timeout, flags) \
177		wdcwait((chp), WDCS_DRQ, WDCS_DRQ, (timeout), (flags))
178#define wdc_wait_for_unbusy(chp, timeout, flags) \
179		wdcwait((chp), 0, 0, (timeout), (flags))
180#define wdc_wait_for_ready(chp, timeout, flags) \
181		wdcwait((chp), WDCS_DRDY, WDCS_DRDY, (timeout), (flags))
182
183/* ATA/ATAPI specs says a device can take 31s to reset */
184#define WDC_RESET_WAIT 31000
185
186void	wdc_atapibus_attach(struct atabus_softc *);
187
188#endif /* _DEV_IC_WDCVAR_H_ */