/testbed/ic/wdcvar.h

http://rtems-atapi.googlecode.com/ · C Header · 188 lines · 98 code · 35 blank · 55 comment · 1 complexity · 945143281dfc3d1611af246729d1e334 MD5 · raw file

  1. /* $NetBSD: wdcvar.h,v 1.89 2008/04/28 20:23:51 martin Exp $ */
  2. /*-
  3. * Copyright (c) 1998, 2003, 2004 The NetBSD Foundation, Inc.
  4. * All rights reserved.
  5. *
  6. * This code is derived from software contributed to The NetBSD Foundation
  7. * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer.
  8. *
  9. * Redistribution and use in source and binary forms, with or without
  10. * modification, are permitted provided that the following conditions
  11. * are met:
  12. * 1. Redistributions of source code must retain the above copyright
  13. * notice, this list of conditions and the following disclaimer.
  14. * 2. Redistributions in binary form must reproduce the above copyright
  15. * notice, this list of conditions and the following disclaimer in the
  16. * documentation and/or other materials provided with the distribution.
  17. *
  18. * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
  19. * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  20. * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  21. * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
  22. * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  23. * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  24. * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  25. * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  26. * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  27. * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  28. * POSSIBILITY OF SUCH DAMAGE.
  29. */
  30. #ifndef _DEV_IC_WDCVAR_H_
  31. #define _DEV_IC_WDCVAR_H_
  32. #include "../sys/callout.h"
  33. #include "../atapi/ataconf.h"
  34. #include "wdcreg.h"
  35. #define WAITTIME (10 * hz) /* time to wait for a completion */
  36. /* this is a lot for hard drives, but not for cdroms */
  37. #define WDC_NREG 8 /* number of command registers */
  38. #define WDC_NSHADOWREG 2 /* number of command "shadow" registers */
  39. struct wdc_regs {
  40. /* Our registers */
  41. bus_space_tag_t cmd_iot;
  42. bus_space_handle_t cmd_baseioh;
  43. bus_space_handle_t cmd_iohs[WDC_NREG+WDC_NSHADOWREG];
  44. bus_space_tag_t ctl_iot;
  45. bus_space_handle_t ctl_ioh;
  46. /* data32{iot,ioh} are only used for 32-bit data xfers */
  47. bus_space_tag_t data32iot;
  48. bus_space_handle_t data32ioh;
  49. /* SATA native registers */
  50. bus_space_tag_t sata_iot;
  51. bus_space_handle_t sata_baseioh;
  52. bus_space_handle_t sata_control;
  53. bus_space_handle_t sata_status;
  54. bus_space_handle_t sata_error;
  55. };
  56. /*
  57. * Per-controller data
  58. */
  59. struct wdc_softc {
  60. struct atac_softc sc_atac; /* generic ATA controller info */
  61. struct wdc_regs *regs; /* register array (per-channel) */
  62. int cap; /* controller capabilities */
  63. #define WDC_CAPABILITY_NO_EXTRA_RESETS 0x0100 /* only reset once */
  64. #define WDC_CAPABILITY_PREATA 0x0200 /* ctrl can be a pre-ata one */
  65. #define WDC_CAPABILITY_WIDEREGS 0x0400 /* Ctrl has wide (16bit) registers */
  66. #if NATA_DMA || NATA_PIOBM
  67. /* if WDC_CAPABILITY_DMA set in 'cap' */
  68. void *dma_arg;
  69. int (*dma_init)(void *, int, int, void *, size_t, int);
  70. void (*dma_start)(void *, int, int);
  71. int (*dma_finish)(void *, int, int, int);
  72. #if NATA_PIOBM
  73. void (*piobm_start)(void *, int, int, int, int, int);
  74. void (*piobm_done)(void *, int, int);
  75. #endif
  76. /* flags passed to dma_init */
  77. #define WDC_DMA_READ 0x01
  78. #define WDC_DMA_IRQW 0x02
  79. #define WDC_DMA_LBA48 0x04
  80. #define WDC_DMA_PIOBM_ATA 0x08
  81. #define WDC_DMA_PIOBM_ATAPI 0x10
  82. #if NATA_PIOBM
  83. /* flags passed to piobm_start */
  84. #define WDC_PIOBM_XFER_IRQ 0x01
  85. #endif
  86. /* values passed to dma_finish */
  87. #define WDC_DMAEND_END 0 /* check for proper end of a DMA xfer */
  88. #define WDC_DMAEND_ABRT 1 /* abort a DMA xfer, verbose */
  89. #define WDC_DMAEND_ABRT_QUIET 2 /* abort a DMA xfer, quiet */
  90. int dma_status; /* status returned from dma_finish() */
  91. #define WDC_DMAST_NOIRQ 0x01 /* missing IRQ */
  92. #define WDC_DMAST_ERR 0x02 /* DMA error */
  93. #define WDC_DMAST_UNDER 0x04 /* DMA underrun */
  94. #endif /* NATA_DMA || NATA_PIOBM */
  95. /* Optional callback to select drive. */
  96. void (*select)(struct ata_channel *,int);
  97. /* Optional callback to ack IRQ. */
  98. void (*irqack)(struct ata_channel *);
  99. /* Optional callback to perform a bus reset */
  100. void (*reset)(struct ata_channel *, int);
  101. /* overridden if the backend has a different data transfer method */
  102. void (*datain_pio)(struct ata_channel *, int, void *, size_t);
  103. void (*dataout_pio)(struct ata_channel *, int, void *, size_t);
  104. };
  105. /* Given an ata_channel, get the wdc_softc. */
  106. #define CHAN_TO_WDC(chp) ((struct wdc_softc *)(chp)->ch_atac)
  107. /* Given an ata_channel, get the wdc_regs. */
  108. #define CHAN_TO_WDC_REGS(chp) (&CHAN_TO_WDC(chp)->regs[(chp)->ch_channel])
  109. /*
  110. * Public functions which can be called by ATA or ATAPI specific parts,
  111. * or bus-specific backends.
  112. */
  113. void wdc_allocate_regs(struct wdc_softc *);
  114. void wdc_init_shadow_regs(struct ata_channel *);
  115. int wdcprobe(struct ata_channel *);
  116. void wdcattach(struct ata_channel *);
  117. int wdcdetach(device_t, int);
  118. void wdc_childdetached(device_t, device_t);
  119. int wdcactivate(device_t, enum devact);
  120. int wdcintr(void *);
  121. void wdc_sataprobe(struct ata_channel *);
  122. void wdc_drvprobe(struct ata_channel *);
  123. void wdcrestart(void*);
  124. int wdcwait(struct ata_channel *, int, int, int, int);
  125. #define WDCWAIT_OK 0 /* we have what we asked */
  126. #define WDCWAIT_TOUT -1 /* timed out */
  127. #define WDCWAIT_THR 1 /* return, the kernel thread has been awakened */
  128. void wdcbit_bucket(struct ata_channel *, int);
  129. int wdc_dmawait(struct ata_channel *, struct ata_xfer *, int);
  130. void wdccommand(struct ata_channel *, u_int8_t, u_int8_t, u_int16_t,
  131. u_int8_t, u_int8_t, u_int8_t, u_int8_t);
  132. void wdccommandext(struct ata_channel *, u_int8_t, u_int8_t, u_int64_t,
  133. u_int16_t);
  134. void wdccommandshort(struct ata_channel *, int, int);
  135. void wdctimeout(void *arg);
  136. void wdc_reset_drive(struct ata_drive_datas *, int);
  137. void wdc_reset_channel(struct ata_channel *, int);
  138. void wdc_do_reset(struct ata_channel *, int);
  139. int wdc_exec_command(struct ata_drive_datas *, struct ata_command*);
  140. /*
  141. * ST506 spec says that if READY or SEEKCMPLT go off, then the read or write
  142. * command is aborted.
  143. */
  144. #define wdc_wait_for_drq(chp, timeout, flags) \
  145. wdcwait((chp), WDCS_DRQ, WDCS_DRQ, (timeout), (flags))
  146. #define wdc_wait_for_unbusy(chp, timeout, flags) \
  147. wdcwait((chp), 0, 0, (timeout), (flags))
  148. #define wdc_wait_for_ready(chp, timeout, flags) \
  149. wdcwait((chp), WDCS_DRDY, WDCS_DRDY, (timeout), (flags))
  150. /* ATA/ATAPI specs says a device can take 31s to reset */
  151. #define WDC_RESET_WAIT 31000
  152. void wdc_atapibus_attach(struct atabus_softc *);
  153. #endif /* _DEV_IC_WDCVAR_H_ */