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/atapi/atareg.h

http://rtems-atapi.googlecode.com/
C++ Header | 557 lines | 411 code | 43 blank | 103 comment | 6 complexity | 45e38748ed0fa919509fb25b91e3072a MD5 | raw file
  1/*	$NetBSD: atareg.h,v 1.38 2010/01/25 00:39:51 jakllsch Exp $	*/
  2
  3/*
  4 * Copyright (c) 1998, 2001 Manuel Bouyer.
  5 *
  6 * Redistribution and use in source and binary forms, with or without
  7 * modification, are permitted provided that the following conditions
  8 * are met:
  9 * 1. Redistributions of source code must retain the above copyright
 10 *    notice, this list of conditions and the following disclaimer.
 11 * 2. Redistributions in binary form must reproduce the above copyright
 12 *    notice, this list of conditions and the following disclaimer in the
 13 *    documentation and/or other materials provided with the distribution.
 14 *
 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 25 */
 26
 27/*-
 28 * Copyright (c) 1991 The Regents of the University of California.
 29 * All rights reserved.
 30 *
 31 * This code is derived from software contributed to Berkeley by
 32 * William Jolitz.
 33 *
 34 * Redistribution and use in source and binary forms, with or without
 35 * modification, are permitted provided that the following conditions
 36 * are met:
 37 * 1. Redistributions of source code must retain the above copyright
 38 *    notice, this list of conditions and the following disclaimer.
 39 * 2. Redistributions in binary form must reproduce the above copyright
 40 *    notice, this list of conditions and the following disclaimer in the
 41 *    documentation and/or other materials provided with the distribution.
 42 * 3. Neither the name of the University nor the names of its contributors
 43 *    may be used to endorse or promote products derived from this software
 44 *    without specific prior written permission.
 45 *
 46 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
 47 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 48 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 49 * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
 50 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 51 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 52 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 53 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 54 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 55 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 56 * SUCH DAMAGE.
 57 *
 58 *	@(#)wdreg.h	7.1 (Berkeley) 5/9/91
 59 */
 60
 61#ifndef _DEV_ATA_ATAREG_H_
 62#define	_DEV_ATA_ATAREG_H_
 63
 64/*
 65 * ATA Task File register definitions.
 66 */
 67
 68/* Status bits. */
 69#define	WDCS_BSY		0x80    /* busy */
 70#define	WDCS_DRDY		0x40    /* drive ready */
 71#define	WDCS_DWF		0x20    /* drive write fault */
 72#define	WDCS_DSC		0x10    /* drive seek complete */
 73#define	WDCS_DRQ		0x08    /* data request */
 74#define	WDCS_CORR		0x04    /* corrected data */
 75#define	WDCS_IDX		0x02    /* index */
 76#define	WDCS_ERR		0x01    /* error */
 77#define	WDCS_BITS \
 78"\020\010bsy\007drdy\006dwf\005dsc\004drq\003corr\002idx\001err"
 79
 80/* Error bits. */
 81#define	WDCE_BBK		0x80	/* bad block detected */
 82#define	WDCE_CRC		0x80	/* CRC error (Ultra-DMA only) */
 83#define	WDCE_UNC		0x40	/* uncorrectable data error */
 84#define	WDCE_MC			0x20	/* media changed */
 85#define	WDCE_IDNF		0x10	/* id not found */
 86#define	WDCE_MCR		0x08	/* media change requested */
 87#define	WDCE_ABRT		0x04	/* aborted command */
 88#define	WDCE_TK0NF		0x02	/* track 0 not found */
 89#define	WDCE_AMNF		0x01	/* address mark not found */
 90
 91/* Commands for Disk Controller. */
 92#define	WDCC_NOP		0x00	/* Always fail with "aborted command" */
 93#define	WDCC_RECAL		0x10	/* disk restore code -- resets cntlr */
 94
 95#define	WDCC_READ		0x20	/* disk read code */
 96#define	WDCC_WRITE		0x30	/* disk write code */
 97#define	 WDCC__LONG		 0x02	/* modifier -- access ecc bytes */
 98#define	 WDCC__NORETRY		 0x01	/* modifier -- no retrys */
 99
100#define	WDCC_FORMAT		0x50	/* disk format code */
101#define	WDCC_DIAGNOSE		0x90	/* controller diagnostic */
102#define	WDCC_IDP		0x91	/* initialize drive parameters */
103
104#define	WDCC_SMART		0xb0	/* Self Mon, Analysis, Reporting Tech */
105
106#define	WDCC_READMULTI		0xc4	/* read multiple */
107#define	WDCC_WRITEMULTI		0xc5	/* write multiple */
108#define	WDCC_SETMULTI		0xc6	/* set multiple mode */
109
110#define	WDCC_READDMA		0xc8	/* read with DMA */
111#define	WDCC_WRITEDMA		0xca	/* write with DMA */
112
113#define WDCC_ACKMC		0xdb	/* acknowledge media change */
114#define	WDCC_LOCK		0xde	/* lock drawer */
115#define	WDCC_UNLOCK		0xdf	/* unlock drawer */
116
117#define	WDCC_FLUSHCACHE		0xe7	/* Flush cache */
118#define	WDCC_FLUSHCACHE_EXT	0xea	/* Flush cache ext */
119#define	WDCC_IDENTIFY		0xec	/* read parameters from controller */
120#define	SET_FEATURES		0xef	/* set features */
121
122#define	WDCC_IDLE		0xe3	/* set idle timer & enter idle mode */
123#define	WDCC_IDLE_IMMED		0xe1	/* enter idle mode */
124#define	WDCC_SLEEP		0xe6	/* enter sleep mode */
125#define	WDCC_STANDBY		0xe2	/* set standby timer & enter standby */
126#define	WDCC_STANDBY_IMMED	0xe0	/* enter standby mode */
127#define	WDCC_CHECK_PWR		0xe5	/* check power mode */
128
129#define WDCC_SECURITY_FREEZE	0xf5	/* freeze locking state */
130
131/* Big Drive support */
132#define	WDCC_READ_EXT		0x24	/* read 48-bit addressing */
133#define	WDCC_WRITE_EXT		0x34	/* write 48-bit addressing */
134
135#define	WDCC_READMULTI_EXT	0x29	/* read multiple 48-bit addressing */
136#define	WDCC_WRITEMULTI_EXT	0x39	/* write multiple 48-bit addressing */
137
138#define	WDCC_READDMA_EXT	0x25	/* read 48-bit addressing with DMA */
139#define	WDCC_WRITEDMA_EXT	0x35	/* write 48-bit addressing with DMA */
140
141#if defined(_KERNEL) || defined(_STANDALONE)
142#include "ataconf.h"
143
144/* Convert a 32-bit command to a 48-bit command. */
145static __inline int
146atacmd_to48(int cmd32)
147{
148	switch (cmd32) {
149	case WDCC_READ:
150		return WDCC_READ_EXT;
151	case WDCC_WRITE:
152		return WDCC_WRITE_EXT;
153	case WDCC_READMULTI:
154		return WDCC_READMULTI_EXT;
155	case WDCC_WRITEMULTI:
156		return WDCC_WRITEMULTI_EXT;
157#if NATA_DMA
158	case WDCC_READDMA:
159		return WDCC_READDMA_EXT;
160	case WDCC_WRITEDMA:
161		return WDCC_WRITEDMA_EXT;
162#endif
163	default:
164		return 0;
165		//panic("atacmd_to48: illegal 32-bit command: %d", cmd32); cdcs
166		/* NOTREACHED */
167	}
168}
169#endif /* _KERNEL || _STANDALONE */
170
171/* Native SATA command queueing */
172#define	WDCC_READ_FPDMA_QUEUED	0x60	/* SATA native queued read (48bit) */
173#define	WDCC_WRITE_FPDMA_QUEUED	0x61	/* SATA native queued write (48bit) */
174
175#ifdef _KERNEL
176/* Convert a 32-bit command to a Native SATA Queued command. */
177static __inline int
178atacmd_tostatq(int cmd32)
179{
180	switch (cmd32) {
181	case WDCC_READDMA:
182		return WDCC_READ_FPDMA_QUEUED;
183	case WDCC_WRITEDMA:
184		return WDCC_WRITE_FPDMA_QUEUED;
185	default:
186		return 0;
187		//panic("atacmd_tosataq: illegal 32-bit command: %d", cmd32); cdcs
188		/* NOTREACHED */
189	}
190}
191#endif /* _KERNEL */
192
193/* Subcommands for SET_FEATURES (features register) */
194#define	WDSF_8BIT_PIO_EN	0x01
195#define	WDSF_WRITE_CACHE_EN	0x02
196#define	WDSF_SET_MODE		0x03
197#define	WDSF_REASSIGN_EN	0x04
198#define	WDSF_APM_EN		0x05
199#define	WDSF_RETRY_DS		0x33
200#define	WDSF_SET_CACHE_SGMT	0x54
201#define	WDSF_READAHEAD_DS	0x55
202#define	WDSF_POD_DS		0x66
203#define	WDSF_ECC_DS		0x77
204#define	WDSF_WRITE_CACHE_DS	0x82
205#define	WDSF_REASSIGN_DS	0x84
206#define	WDSF_APM_DS		0x85
207#define	WDSF_ECC_EN		0x88
208#define	WDSF_RETRY_EN		0x99
209#define	WDSF_SET_CURRENT	0x9a
210#define	WDSF_READAHEAD_EN	0xaa
211#define	WDSF_PREFETCH_SET	0xab
212#define	WDSF_POD_EN		0xcc
213
214/* Subcommands for SMART (features register) */
215#define	WDSM_RD_DATA		0xd0
216#define	WDSM_RD_THRESHOLDS	0xd1
217#define	WDSM_ATTR_AUTOSAVE_EN	0xd2
218#define	WDSM_SAVE_ATTR		0xd3
219#define	WDSM_EXEC_OFFL_IMM	0xd4
220#define	WDSM_RD_LOG		0xd5
221#define	WDSM_ENABLE_OPS		0xd8
222#define	WDSM_DISABLE_OPS	0xd9
223#define	WDSM_STATUS		0xda
224
225#define WDSMART_CYL		0xc24f
226
227/* parameters uploaded to device/heads register */
228#define	WDSD_IBM		0xa0	/* forced to 512 byte sector, ecc */
229#define	WDSD_CHS		0x00	/* cylinder/head/sector addressing */
230#define	WDSD_LBA		0x40	/* logical block addressing */
231
232/* Commands for ATAPI devices */
233#define	ATAPI_CHECK_POWER_MODE	0xe5
234#define	ATAPI_EXEC_DRIVE_DIAGS	0x90
235#define	ATAPI_IDLE_IMMEDIATE	0xe1
236#define	ATAPI_NOP		0x00
237#define	ATAPI_PKT_CMD		0xa0
238#define	ATAPI_IDENTIFY_DEVICE	0xa1
239#define	ATAPI_SOFT_RESET	0x08
240#define	ATAPI_SLEEP		0xe6
241#define	ATAPI_STANDBY_IMMEDIATE	0xe0
242
243/* Bytes used by ATAPI_PACKET_COMMAND (feature register) */
244#define	ATAPI_PKT_CMD_FTRE_DMA	0x01
245#define	ATAPI_PKT_CMD_FTRE_OVL	0x02
246
247/* ireason */
248#define	WDCI_CMD		0x01	/* command(1) or data(0) */
249#define	WDCI_IN			0x02	/* transfer to(1) or from(0) the host */
250#define	WDCI_RELEASE		0x04	/* bus released until completion */
251
252#define	PHASE_CMDOUT		(WDCS_DRQ | WDCI_CMD)
253#define	PHASE_DATAIN		(WDCS_DRQ | WDCI_IN)
254#define	PHASE_DATAOUT		(WDCS_DRQ)
255#define	PHASE_COMPLETED		(WDCI_IN | WDCI_CMD)
256#define	PHASE_ABORTED		(0)
257
258/*
259 * Drive parameter structure for ATA/ATAPI.
260 * Bit fields: WDC_* : common to ATA/ATAPI
261 *             ATA_* : ATA only
262 *             ATAPI_* : ATAPI only.
263 */
264struct ataparams {
265    /* drive info */
266    uint16_t	atap_config;		/* 0: general configuration */
267#define WDC_CFG_ATAPI_MASK    	0xc000
268#define WDC_CFG_ATAPI    	0x8000
269#define	ATA_CFG_REMOVABLE	0x0080
270#define	ATA_CFG_FIXED		0x0040
271#define ATAPI_CFG_TYPE_MASK	0x1f00
272#define ATAPI_CFG_TYPE(x) (((x) & ATAPI_CFG_TYPE_MASK) >> 8)
273#define	ATAPI_CFG_REMOV		0x0080
274#define ATAPI_CFG_DRQ_MASK	0x0060
275#define ATAPI_CFG_STD_DRQ	0x0000
276#define ATAPI_CFG_IRQ_DRQ	0x0020
277#define ATAPI_CFG_ACCEL_DRQ	0x0040
278#define ATAPI_CFG_CMD_MASK	0x0003
279#define ATAPI_CFG_CMD_12	0x0000
280#define ATAPI_CFG_CMD_16	0x0001
281/* words 1-9 are ATA only */
282    uint16_t	atap_cylinders;		/* 1: # of non-removable cylinders */
283    uint16_t	__reserved1;
284    uint16_t	atap_heads;		/* 3: # of heads */
285    uint16_t	__retired1[2];		/* 4-5: # of unform. bytes/track */
286    uint16_t	atap_sectors;		/* 6: # of sectors */
287    uint16_t	__retired2[3];
288
289    uint8_t	atap_serial[20];	/* 10-19: serial number */
290    uint16_t	__retired3[2];
291    uint16_t	__obsolete1;
292    uint8_t	atap_revision[8];	/* 23-26: firmware revision */
293    uint8_t	atap_model[40];		/* 27-46: model number */
294    uint16_t	atap_multi;		/* 47: maximum sectors per irq (ATA) */
295    uint16_t	__reserved2;
296    uint16_t	atap_capabilities1;	/* 49: capability flags */
297#define WDC_CAP_IORDY	0x0800
298#define WDC_CAP_IORDY_DSBL 0x0400
299#define	WDC_CAP_LBA	0x0200
300#define	WDC_CAP_DMA	0x0100
301#define ATA_CAP_STBY	0x2000
302#define ATAPI_CAP_INTERL_DMA	0x8000
303#define ATAPI_CAP_CMD_QUEUE	0x4000
304#define	ATAPI_CAP_OVERLP	0X2000
305#define ATAPI_CAP_ATA_RST	0x1000
306    uint16_t	atap_capabilities2;	/* 50: capability flags (ATA) */
307#if BYTE_ORDER == LITTLE_ENDIAN
308    uint8_t	__junk2;
309    uint8_t	atap_oldpiotiming;	/* 51: old PIO timing mode */
310    uint8_t	__junk3;
311    uint8_t	atap_olddmatiming;	/* 52: old DMA timing mode (ATA) */
312#else
313    uint8_t	atap_oldpiotiming;	/* 51: old PIO timing mode */
314    uint8_t	__junk2;
315    uint8_t	atap_olddmatiming;	/* 52: old DMA timing mode (ATA) */
316    uint8_t	__junk3;
317#endif
318    uint16_t	atap_extensions;	/* 53: extensions supported */
319#define WDC_EXT_UDMA_MODES	0x0004
320#define WDC_EXT_MODES		0x0002
321#define WDC_EXT_GEOM		0x0001
322/* words 54-62 are ATA only */
323    uint16_t	atap_curcylinders;	/* 54: current logical cylinders */
324    uint16_t	atap_curheads;		/* 55: current logical heads */
325    uint16_t	atap_cursectors;	/* 56: current logical sectors/tracks */
326    uint16_t	atap_curcapacity[2];	/* 57-58: current capacity */
327    uint16_t	atap_curmulti;		/* 59: current multi-sector setting */
328#define WDC_MULTI_VALID 0x0100
329#define WDC_MULTI_MASK  0x00ff
330    uint16_t	atap_capacity[2];  	/* 60-61: total capacity (LBA only) */
331    uint16_t	__retired4;
332#if BYTE_ORDER == LITTLE_ENDIAN
333    uint8_t	atap_dmamode_supp; 	/* 63: multiword DMA mode supported */
334    uint8_t	atap_dmamode_act; 	/*     multiword DMA mode active */
335    uint8_t	atap_piomode_supp;	/* 64: PIO mode supported */
336    uint8_t	__junk4;
337#else
338    uint8_t	atap_dmamode_act; 	/*     multiword DMA mode active */
339    uint8_t	atap_dmamode_supp; 	/* 63: multiword DMA mode supported */
340    uint8_t	__junk4;
341    uint8_t	atap_piomode_supp;	/* 64: PIO mode supported */
342#endif
343    uint16_t	atap_dmatiming_mimi;	/* 65: minimum DMA cycle time */
344    uint16_t	atap_dmatiming_recom;	/* 66: recommended DMA cycle time */
345    uint16_t	atap_piotiming;		/* 67: mini PIO cycle time without FC */
346    uint16_t	atap_piotiming_iordy;	/* 68: mini PIO cycle time with IORDY FC */
347    uint16_t	__reserved3[2];
348/* words 71-72 are ATAPI only */
349    uint16_t	atap_pkt_br;		/* 71: time (ns) to bus release */
350    uint16_t	atap_pkt_bsyclr;	/* 72: tme to clear BSY after service */
351    uint16_t	__reserved4[2];
352    uint16_t	atap_queuedepth;	/* 75: */
353#define WDC_QUEUE_DEPTH_MASK 0x1F
354    uint16_t	atap_sata_caps;		/* 76: */
355#define SATA_SIGNAL_GEN1	0x02
356#define SATA_SIGNAL_GEN2	0x04
357#define SATA_NATIVE_CMDQ	0x0100
358#define SATA_HOST_PWR_MGMT	0x0200
359#define SATA_PHY_EVNT_CNT	0x0400
360    uint16_t	atap_sata_reserved;	/* 77: */
361    uint16_t	atap_sata_features_supp; /* 78: */
362#define SATA_NONZERO_OFFSETS	0x02
363#define SATA_DMA_SETUP_AUTO	0x04
364#define SATA_DRIVE_PWR_MGMT	0x08
365#define SATA_IN_ORDER_DATA	0x10
366#define SATA_SW_STTNGS_PRS	0x40
367    uint16_t	atap_sata_features_en;	/* 79: */
368    uint16_t	atap_ata_major;  	/* 80: Major version number */
369#define	WDC_VER_ATA1	0x0002
370#define	WDC_VER_ATA2	0x0004
371#define	WDC_VER_ATA3	0x0008
372#define	WDC_VER_ATA4	0x0010
373#define	WDC_VER_ATA5	0x0020
374#define	WDC_VER_ATA6	0x0040
375#define	WDC_VER_ATA7	0x0080
376    uint16_t	atap_ata_minor;		/* 81: Minor version number */
377    uint16_t	atap_cmd_set1;		/* 82: command set supported */
378#define	WDC_CMD1_NOP	0x4000		/*	NOP */
379#define	WDC_CMD1_RB	0x2000		/*	READ BUFFER */
380#define	WDC_CMD1_WB	0x1000		/*	WRITE BUFFER */
381/*			0x0800			Obsolete */
382#define	WDC_CMD1_HPA	0x0400		/*	Host Protected Area */
383#define	WDC_CMD1_DVRST	0x0200		/*	DEVICE RESET */
384#define	WDC_CMD1_SRV	0x0100		/*	SERVICE */
385#define	WDC_CMD1_RLSE	0x0080		/*	release interrupt */
386#define	WDC_CMD1_AHEAD	0x0040		/*	look-ahead */
387#define	WDC_CMD1_CACHE	0x0020		/*	write cache */
388#define	WDC_CMD1_PKT	0x0010		/*	PACKET */
389#define	WDC_CMD1_PM	0x0008		/*	Power Management */
390#define	WDC_CMD1_REMOV	0x0004		/*	Removable Media */
391#define	WDC_CMD1_SEC	0x0002		/*	Security Mode */
392#define	WDC_CMD1_SMART	0x0001		/*	SMART */
393    uint16_t	atap_cmd_set2;		/* 83: command set supported */
394#define	ATA_CMD2_FCE	0x2000		/*	FLUSH CACHE EXT */
395#define	WDC_CMD2_FC	0x1000		/*	FLUSH CACHE */
396#define	WDC_CMD2_DCO	0x0800		/*	Device Configuration Overlay */
397#define	ATA_CMD2_LBA48	0x0400		/*	48-bit Address */
398#define	WDC_CMD2_AAM	0x0200		/*	Automatic Acoustic Management */
399#define	WDC_CMD2_SM	0x0100		/*	SET MAX security extension */
400#define	WDC_CMD2_SFREQ	0x0040		/*	SET FEATURE is required
401						to spin-up after power-up */
402#define	WDC_CMD2_PUIS	0x0020		/*	Power-Up In Standby */
403#define	WDC_CMD2_RMSN	0x0010		/*	Removable Media Status Notify */
404#define	ATA_CMD2_APM	0x0008		/*	Advanced Power Management */
405#define	ATA_CMD2_CFA	0x0004		/*	CFA */
406#define	ATA_CMD2_RWQ	0x0002		/*	READ/WRITE DMA QUEUED */
407#define	WDC_CMD2_DM	0x0001		/*	DOWNLOAD MICROCODE */
408    uint16_t	atap_cmd_ext;		/* 84: command/features supp. ext. */
409#define	ATA_CMDE_TLCONT	0x1000		/*	Time-limited R/W Continuous */
410#define	ATA_CMDE_TL	0x0800		/*	Time-limited R/W */
411#define	ATA_CMDE_URGW	0x0400		/*	URG for WRITE STREAM DMA/PIO */
412#define	ATA_CMDE_URGR	0x0200		/*	URG for READ STREAM DMA/PIO */
413#define	ATA_CMDE_WWN	0x0100		/*	World Wide name */
414#define	ATA_CMDE_WQFE	0x0080		/*	WRITE DMA QUEUED FUA EXT */
415#define	ATA_CMDE_WFE	0x0040		/*	WRITE DMA/MULTIPLE FUA EXT */
416#define	ATA_CMDE_GPL	0x0020		/*	General Purpose Logging */
417#define	ATA_CMDE_STREAM	0x0010		/*	Streaming */
418#define	ATA_CMDE_MCPTC	0x0008		/*	Media Card Pass Through Cmd */
419#define	ATA_CMDE_MS	0x0004		/*	Media serial number */
420#define	ATA_CMDE_SST	0x0002		/*	SMART self-test */
421#define	ATA_CMDE_SEL	0x0001		/*	SMART error logging */
422    uint16_t	atap_cmd1_en;		/* 85: cmd/features enabled */
423/* bits are the same as atap_cmd_set1 */
424    uint16_t	atap_cmd2_en;		/* 86: cmd/features enabled */
425/* bits are the same as atap_cmd_set2 */
426    uint16_t	atap_cmd_def;		/* 87: cmd/features default */
427#if BYTE_ORDER == LITTLE_ENDIAN
428    uint8_t	atap_udmamode_supp; 	/* 88: Ultra-DMA mode supported */
429    uint8_t	atap_udmamode_act; 	/*     Ultra-DMA mode active */
430#else
431    uint8_t	atap_udmamode_act; 	/*     Ultra-DMA mode active */
432    uint8_t	atap_udmamode_supp; 	/* 88: Ultra-DMA mode supported */
433#endif
434/* 89-92 are ATA-only */
435    uint16_t	atap_seu_time;		/* 89: Sec. Erase Unit compl. time */
436    uint16_t	atap_eseu_time;		/* 90: Enhanced SEU compl. time */
437    uint16_t	atap_apm_val;		/* 91: current APM value */
438    uint16_t	__reserved5[8];		/* 92-99: reserved */
439    uint16_t	atap_max_lba[4];	/* 100-103: Max. user LBA addr */
440    uint16_t	__reserved6[2];		/* 104-105: reserved */
441    uint16_t	atap_secsz;		/* 106: physical/logical sector size */
442#define ATA_SECSZ_VALID_MASK 0xc000
443#define ATA_SECSZ_VALID      0x4000
444#define ATA_SECSZ_LPS        0x2000	/* long physical sectors */
445#define ATA_SECSZ_LLS        0x1000	/* long logical sectors */
446#define ATA_SECSZ_LPS_SZMSK  0x000f	/* 2**N logical per physical */
447    uint16_t	atap_iso7779_isd;	/* 107: ISO 7779 inter-seek delay */
448    uint16_t 	atap_wwn[4];		/* 108-111: World Wide Name */
449    uint16_t	__reserved7[5];		/* 112-116 */
450    uint16_t	atap_lls_secsz[2];	/* 117-118: long logical sector size */
451    uint16_t	__reserved8[8];		/* 119-126 */
452    uint16_t	atap_rmsn_supp;		/* 127: remov. media status notif. */
453#define WDC_RMSN_SUPP_MASK 0x0003
454#define WDC_RMSN_SUPP 0x0001
455    uint16_t	atap_sec_st;		/* 128: security status */
456#define WDC_SEC_LEV_MAX	0x0100
457#define WDC_SEC_ESE_SUPP 0x0020
458#define WDC_SEC_EXP	0x0010
459#define WDC_SEC_FROZEN	0x0008
460#define WDC_SEC_LOCKED	0x0004
461#define WDC_SEC_EN	0x0002
462#define WDC_SEC_SUPP	0x0001
463    uint16_t	__reserved9[31];	/* 129-159: vendor specific */
464    uint16_t	atap_cfa_power;		/* 160: CFA powermode */
465#define ATA_CFA_MAX_MASK  0x0fff
466#define ATA_CFA_MODE1_DIS 0x1000	/* CFA Mode 1 Disabled */
467#define ATA_CFA_MODE1_REQ 0x2000	/* CFA Mode 1 Required */
468#define ATA_CFA_WORD160   0x8000	/* Word 160 supported */
469    uint16_t	__reserved10[15];	/* 161-175: reserved for CFA */
470    uint8_t	atap_media_serial[60];	/* 176-205: media serial number */
471    uint16_t	__reserved11[3];	/* 206-208: */
472    uint16_t	atap_logical_align;	/* 209: logical/physical alignment */
473#define ATA_LA_VALID_MASK 0xc000
474#define ATA_LA_VALID      0x4000
475#define ATA_LA_MASK       0x3fff	/* offset of sector LBA 0 in PBA 0 */
476    uint16_t	__reserved12[45];	/* 210-254: */
477    uint16_t	atap_integrity;		/* 255: Integrity word */
478#define WDC_INTEGRITY_MAGIC_MASK 0x00ff
479#define WDC_INTEGRITY_MAGIC      0x00a5
480};
481
482/*
483 * If WDSM_ATTR_ADVISORY, device exceeded intended design life period.
484 * If not WDSM_ATTR_ADVISORY, imminent data loss predicted.
485 */
486#define WDSM_ATTR_ADVISORY	1
487
488/*
489 * If WDSM_ATTR_COLLECTIVE, attribute only updated in off-line testing.
490 * If not WDSM_ATTR_COLLECTIVE, attribute updated also in on-line testing.
491 */
492#define WDSM_ATTR_COLLECTIVE	2
493
494/*
495 * ATA SMART attributes
496 */
497
498struct ata_smart_attr {
499	uint8_t		id;		/* attribute id number */
500	uint16_t	flags;
501	uint8_t		value;		/* attribute value */
502	uint8_t		worst;
503	uint8_t		raw[6];
504	uint8_t		reserved;
505} ;
506
507struct ata_smart_attributes {
508	uint16_t	data_structure_revision;
509	struct ata_smart_attr attributes[30];
510	uint8_t		offline_data_collection_status;
511	uint8_t		self_test_exec_status;
512	uint16_t	total_time_to_complete_off_line;
513	uint8_t		vendor_specific_366;
514	uint8_t		offline_data_collection_capability;
515	uint16_t	smart_capability;
516	uint8_t		errorlog_capability;
517	uint8_t		vendor_specific_371;
518	uint8_t		short_test_completion_time;
519	uint8_t		extend_test_completion_time;
520	uint8_t		reserved_374_385[12];
521	uint8_t		vendor_specific_386_509[125];
522	int8_t		checksum;
523} ;
524
525struct ata_smart_thresh {
526	uint8_t		id;
527	uint8_t		value;
528	uint8_t		reserved[10];
529} ;
530
531struct ata_smart_thresholds {
532	uint16_t	data_structure_revision;
533	struct ata_smart_thresh	thresholds[30];
534	uint8_t		reserved[18];
535	uint8_t		vendor_specific[131];
536	int8_t		checksum;
537} ;
538
539struct ata_smart_selftest {
540	uint8_t		number;
541	uint8_t		status;
542	uint16_t	time_stamp;
543	uint8_t		failure_check_point;
544	uint32_t	lba_first_error;
545	uint8_t		vendor_specific[15];
546} ;
547
548struct ata_smart_selftestlog {
549	uint16_t	data_structure_revision;
550	struct ata_smart_selftest log_entries[21];
551	uint8_t		vendorspecific[2];
552	uint8_t		mostrecenttest;
553	uint8_t		reserved[2];
554	uint8_t		checksum;
555} ;
556
557#endif /* _DEV_ATA_ATAREG_H_ */