PageRenderTime 117ms CodeModel.GetById 13ms app.highlight 93ms RepoModel.GetById 1ms app.codeStats 0ms

/atapi/ata.c

http://rtems-atapi.googlecode.com/
C | 1566 lines | 1114 code | 175 blank | 277 comment | 299 complexity | 2d63d13c75eb79eadf1a5a1cab61293b MD5 | raw file
   1/*	$NetBSD: ata.c,v 1.113 2010/03/28 20:46:18 snj Exp $	*/
   2
   3/*
   4 * Copyright (c) 1998, 2001 Manuel Bouyer.  All rights reserved.
   5 *
   6 * Redistribution and use in source and binary forms, with or without
   7 * modification, are permitted provided that the following conditions
   8 * are met:
   9 * 1. Redistributions of source code must retain the above copyright
  10 *    notice, this list of conditions and the following disclaimer.
  11 * 2. Redistributions in binary form must reproduce the above copyright
  12 *    notice, this list of conditions and the following disclaimer in the
  13 *    documentation and/or other materials provided with the distribution.
  14 *
  15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  25 */
  26
  27
  28
  29//#include <rtems/bsd/sys/cdefs.h>
  30#include <rtems/bsd/sys/queue.h>
  31//__KERNEL_RCSID(0, "$NetBSD: ata.c,v 1.113 2010/03/28 20:46:18 snj Exp $");
  32
  33//#include "opt_ata.h" 
  34
  35#include "../sys/quirk.h"
  36
  37//#include <sys/param.h>
  38//#include <sys/systm.h>
  39#include <sys/kernel.h> /*safe*/
  40#include <sys/malloc.h> /*+-safe*/
  41
  42#include "../sys/device.h"
  43#include "../sys/conf.h"
  44
  45#include <sys/fcntl.h> /*?*/
  46#include <sys/proc.h>  /*dummy*/
  47
  48#include "../sys/pool.h" /*dummy*/
  49#include "../sys/kthread.h"
  50
  51//#include "../sys/errno.h"
  52#include <errno.h>
  53
  54#include "ataio.h"
  55#include "../sys/kmem.h"
  56#include "../sys/simplelock.h"
  57#include "../sys/intr.h"
  58#include "../sys/bus.h"
  59#include "../sys/once.h"
  60
  61#include "ataconf.h"
  62#include "atareg.h"
  63#include "atavar.h"
  64#include "ic/wdcvar.h"	/* for PIOBM */
  65
  66//#include "locators.h"
  67
  68//#include "atapibus.h"
  69//#include "ataraid.h"
  70
  71#if NATARAID > 0
  72#include <dev/ata/ata_raidvar.h>
  73#endif
  74
  75#define DEBUG_FUNCS  0x08
  76#define DEBUG_PROBE  0x10
  77#define DEBUG_DETACH 0x20
  78#define	DEBUG_XFERS  0x40
  79#ifdef ATADEBUG
  80int atadebug_mask = 0;
  81#define ATADEBUG_PRINT(args, level) \
  82	if (atadebug_mask & (level)) \
  83		printf args
  84#else
  85#define ATADEBUG_PRINT(args, level)
  86#endif
  87
  88static struct pool ata_xfer_pool;
  89
  90/*
  91 * A queue of atabus instances, used to ensure the same bus probe order
  92 * for a given hardware configuration at each boot.
  93 */
  94struct atabus_initq_head atabus_initq_head =
  95    TAILQ_HEAD_INITIALIZER(atabus_initq_head);
  96struct simplelock atabus_interlock = SIMPLELOCK_INITIALIZER;
  97
  98/* kernel thread probing devices on a atabus. Only one probing at once */
  99struct lwp *atabus_configlwp;
 100
 101/*****************************************************************************
 102 * ATA bus layer.
 103 *
 104 * ATA controllers attach an atabus instance, which handles probing the bus
 105 * for drives, etc.
 106 *****************************************************************************/
 107
 108dev_type_open(atabusopen);
 109dev_type_close(atabusclose);
 110dev_type_ioctl(atabusioctl);
 111
 112const struct cdevsw atabus_cdevsw = {
 113	atabusopen, atabusclose, noread, nowrite, atabusioctl,
 114	nostop, notty, nopoll, nommap, nokqfilter, D_OTHER
 115};
 116
 117extern struct cfdriver atabus_cd;
 118
 119static void atabus_childdetached(device_t, device_t);
 120static bool atabus_resume(device_t, const pmf_qual_t *);
 121static bool atabus_suspend(device_t, const pmf_qual_t *);
 122static void atabusconfig_thread(void *);
 123
 124/*
 125 * atabusprint:
 126 *
 127 *	Autoconfiguration print routine used by ATA controllers when
 128 *	attaching an atabus instance.
 129 */
 130int
 131atabusprint(void *aux, const char *pnp)
 132{
 133	struct ata_channel *chan = aux;
 134
 135	if (pnp)
 136		aprint_normal("atabus at %s", pnp);
 137	aprint_normal(" channel %d", chan->ch_channel);
 138
 139	return (UNCONF);
 140}
 141
 142/*
 143 * ataprint:
 144 *
 145 *	Autoconfiguration print routine.
 146 */
 147int
 148ataprint(void *aux, const char *pnp)
 149{
 150	struct ata_device *adev = aux;
 151
 152	if (pnp)
 153		aprint_normal("wd at %s", pnp);
 154	aprint_normal(" drive %d", adev->adev_drv_data->drive);
 155
 156	return (UNCONF);
 157}
 158
 159/*
 160 * ata_channel_attach:
 161 *
 162 *	Common parts of attaching an atabus to an ATA controller channel.
 163 */
 164void
 165ata_channel_attach(struct ata_channel *chp)
 166{
 167
 168	if (chp->ch_flags & ATACH_DISABLED)
 169		return;
 170
 171	/* XXX callout_destroy */
 172	callout_init(&chp->ch_callout, 0);
 173
 174	TAILQ_INIT(&chp->ch_queue->queue_xfer);
 175	chp->ch_queue->queue_freeze = 0;
 176	chp->ch_queue->queue_flags = 0;
 177	chp->ch_queue->active_xfer = NULL;
 178
 179	chp->atabus = config_found_ia(chp->ch_atac->atac_dev, "ata", chp,
 180		atabusprint);
 181}
 182
 183static void
 184atabusconfig(struct atabus_softc *atabus_sc)
 185{
 186	struct ata_channel *chp = atabus_sc->sc_chan;
 187	struct atac_softc *atac = chp->ch_atac;
 188	struct atabus_initq *atabus_initq = NULL;
 189	int i, s, error;
 190
 191	/* we are in the atabus's thread context */
 192	s = splbio();
 193	chp->ch_flags |= ATACH_TH_RUN;
 194	splx(s);
 195
 196	/* Probe for the drives. */
 197	/* XXX for SATA devices we will power up all drives at once */
 198	(*atac->atac_probe)(chp);
 199
 200	ATADEBUG_PRINT(("atabusattach: ch_drive_flags 0x%x 0x%x\n",
 201	    chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags),
 202	    DEBUG_PROBE);
 203
 204	/* next operations will occurs in a separate thread */
 205	s = splbio();
 206	chp->ch_flags &= ~ATACH_TH_RUN;
 207	splx(s);
 208
 209	/* Make sure the devices probe in atabus order to avoid jitter. */
 210	simple_lock(&atabus_interlock);
 211	while(1) {
 212		atabus_initq = TAILQ_FIRST(&atabus_initq_head);
 213		if (atabus_initq->atabus_sc == atabus_sc)
 214			break;
 215		ltsleep(&atabus_initq_head, PRIBIO, "ata_initq", 0,
 216		    &atabus_interlock);
 217	}
 218	simple_unlock(&atabus_interlock);
 219
 220	/* If no drives, abort here */
 221	for (i = 0; i < chp->ch_ndrive; i++)
 222		if ((chp->ch_drive[i].drive_flags & DRIVE) != 0)
 223			break;
 224	if (i == chp->ch_ndrive)
 225		goto out;
 226
 227	/* Shortcut in case we've been shutdown */
 228	if (chp->ch_flags & ATACH_SHUTDOWN)
 229		goto out;
 230
 231
 232	if ((error = kthread_create(PRI_NONE, 0, NULL, atabusconfig_thread,
 233	    atabus_sc, &atabus_configlwp,
 234	    "%scnf", device_xname(atac->atac_dev))) != 0)
 235		aprint_error_dev(atac->atac_dev,
 236		    "unable to create config thread: error %d\n", error);
 237	return;
 238
 239 out:
 240	simple_lock(&atabus_interlock);
 241	TAILQ_REMOVE(&atabus_initq_head, atabus_initq, atabus_initq);
 242	simple_unlock(&atabus_interlock);
 243
 244	free(atabus_initq, M_DEVBUF);
 245	wakeup(&atabus_initq_head);
 246
 247	ata_delref(chp);
 248
 249	config_pending_decr();
 250}
 251
 252/*
 253 * atabus_configthread: finish attach of atabus's childrens, in a separate
 254 * kernel thread.
 255 */
 256static void
 257atabusconfig_thread(void *arg)
 258{
 259	struct atabus_softc *atabus_sc = arg;
 260	struct ata_channel *chp = atabus_sc->sc_chan;
 261	struct atac_softc *atac = chp->ch_atac;
 262	int i, s;
 263	struct atabus_initq *atabus_initq = NULL;
 264
 265	simple_lock(&atabus_interlock);
 266	atabus_initq = TAILQ_FIRST(&atabus_initq_head);
 267	simple_unlock(&atabus_interlock);
 268	KASSERT(atabus_initq->atabus_sc == atabus_sc);
 269	/*
 270	 * Attach an ATAPI bus, if needed.
 271	 */
 272	for (i = 0; i < chp->ch_ndrive; i++) {
 273		if (chp->ch_drive[i].drive_flags & DRIVE_ATAPI) {
 274#if NATAPIBUS > 0
 275			(*atac->atac_atapibus_attach)(atabus_sc);
 276#else
 277			/*
 278			 * Fake the autoconfig "not configured" message
 279			 */
 280			aprint_normal("atapibus at %s not configured\n",
 281			    device_xname(atac->atac_dev));
 282			chp->atapibus = NULL;
 283			s = splbio();
 284			for (i = 0; i < chp->ch_ndrive; i++)
 285				chp->ch_drive[i].drive_flags &= ~DRIVE_ATAPI;
 286			splx(s);
 287#endif
 288			break;
 289		}
 290	}
 291
 292	for (i = 0; i < chp->ch_ndrive; i++) {
 293		struct ata_device adev;
 294		if ((chp->ch_drive[i].drive_flags &
 295		    (DRIVE_ATA | DRIVE_OLD)) == 0) {
 296			continue;
 297		}
 298		memset(&adev, 0, sizeof(struct ata_device));
 299		adev.adev_bustype = atac->atac_bustype_ata;
 300		adev.adev_channel = chp->ch_channel;
 301		adev.adev_openings = 1;
 302		adev.adev_drv_data = &chp->ch_drive[i];
 303		chp->ata_drives[i] = config_found_ia(atabus_sc->sc_dev,
 304		    "ata_hl", &adev, ataprint);
 305		if (chp->ata_drives[i] != NULL)
 306			ata_probe_caps(&chp->ch_drive[i]);
 307		else {
 308			s = splbio();
 309			chp->ch_drive[i].drive_flags &=
 310			    ~(DRIVE_ATA | DRIVE_OLD);
 311			splx(s);
 312		}
 313	}
 314
 315	/* now that we know the drives, the controller can set its modes */
 316	if (atac->atac_set_modes) {
 317		(*atac->atac_set_modes)(chp);
 318		ata_print_modes(chp);
 319	}
 320#if NATARAID > 0
 321	if (atac->atac_cap & ATAC_CAP_RAID)
 322		for (i = 0; i < chp->ch_ndrive; i++)
 323			if (chp->ata_drives[i] != NULL)
 324				ata_raid_check_component(chp->ata_drives[i]);
 325#endif /* NATARAID > 0 */
 326
 327	/*
 328	 * reset drive_flags for unattached devices, reset state for attached
 329	 * ones
 330	 */
 331	s = splbio();
 332	for (i = 0; i < chp->ch_ndrive; i++) {
 333		if (chp->ch_drive[i].drv_softc == NULL)
 334			chp->ch_drive[i].drive_flags = 0;
 335		else
 336			chp->ch_drive[i].state = 0;
 337	}
 338	splx(s);
 339
 340	simple_lock(&atabus_interlock);
 341	TAILQ_REMOVE(&atabus_initq_head, atabus_initq, atabus_initq);
 342	simple_unlock(&atabus_interlock);
 343
 344	free(atabus_initq, M_DEVBUF);
 345	wakeup(&atabus_initq_head);
 346
 347	ata_delref(chp);
 348
 349	config_pending_decr();
 350	kthread_exit(0);
 351}
 352
 353/*
 354 * atabus_thread:
 355 *
 356 *	Worker thread for the ATA bus.
 357 */
 358static void
 359atabus_thread(void *arg)
 360{
 361	struct atabus_softc *sc = arg;
 362	struct ata_channel *chp = sc->sc_chan;
 363	struct ata_xfer *xfer;
 364	int i, s;
 365
 366	s = splbio();
 367	chp->ch_flags |= ATACH_TH_RUN;
 368
 369	/*
 370	 * Probe the drives.  Reset all flags to 0 to indicate to controllers
 371	 * that can re-probe that all drives must be probed..
 372	 *
 373	 * Note: ch_ndrive may be changed during the probe.
 374	 */
 375	for (i = 0; i < ATA_MAXDRIVES; i++)
 376		chp->ch_drive[i].drive_flags = 0;
 377	splx(s);
 378
 379	atabusconfig(sc);
 380
 381	s = splbio();
 382	for (;;) {
 383		if ((chp->ch_flags & (ATACH_TH_RESET | ATACH_SHUTDOWN)) == 0 &&
 384		    (chp->ch_queue->active_xfer == NULL ||
 385		     chp->ch_queue->queue_freeze == 0)) {
 386			chp->ch_flags &= ~ATACH_TH_RUN;
 387			//(void) tsleep(&chp->ch_thread, PRIBIO, "atath", 0);
 388			chp->ch_flags |= ATACH_TH_RUN;
 389		}
 390		if (chp->ch_flags & ATACH_SHUTDOWN) {
 391			break;
 392		}
 393		if (chp->ch_flags & ATACH_TH_RESET) {
 394			/*
 395			 * ata_reset_channel() will freeze 2 times, so
 396			 * unfreeze one time. Not a problem as we're at splbio
 397			 */
 398			chp->ch_queue->queue_freeze--;
 399			ata_reset_channel(chp, AT_WAIT | chp->ch_reset_flags);
 400		} else if (chp->ch_queue->active_xfer != NULL &&
 401			   chp->ch_queue->queue_freeze == 1) {
 402			/*
 403			 * Caller has bumped queue_freeze, decrease it.
 404			 */
 405			chp->ch_queue->queue_freeze--;
 406			xfer = chp->ch_queue->active_xfer;
 407			KASSERT(xfer != NULL);
 408			(*xfer->c_start)(xfer->c_chp, xfer);
 409		} else if (chp->ch_queue->queue_freeze > 1)
 410			return;//panic("ata_thread: queue_freeze");
 411	}
 412	splx(s);
 413	chp->ch_thread = NULL;
 414	wakeup(&chp->ch_flags);
 415	kthread_exit(0);
 416}
 417
 418/*
 419 * atabus_match:
 420 *
 421 *	Autoconfiguration match routine.
 422 */
 423static int
 424atabus_match(device_t parent, cfdata_t cf, void *aux)
 425{
 426	struct ata_channel *chp = aux;
 427
 428	if (chp == NULL)
 429		return (0);
 430
 431	if (cf->cf_loc[ATACF_CHANNEL] != chp->ch_channel &&
 432	    cf->cf_loc[ATACF_CHANNEL] != ATACF_CHANNEL_DEFAULT)
 433		return (0);
 434
 435	return (1);
 436}
 437
 438static int
 439atabus_xferpool_init(void)
 440{
 441
 442	pool_init(&ata_xfer_pool, sizeof(struct ata_xfer), 0, 0, 0, "ataspl",
 443	    NULL, IPL_BIO);
 444	return 0;
 445}
 446
 447/*
 448 * atabus_attach:
 449 *
 450 *	Autoconfiguration attach routine.
 451 */
 452static void
 453atabus_attach(device_t parent, device_t self, void *aux)
 454{
 455	struct atabus_softc *sc = device_private(self);
 456	struct ata_channel *chp = aux;
 457	struct atabus_initq *initq;
 458	static ONCE_DECL(poolinit_ctrl);
 459	int error;
 460
 461	sc->sc_chan = chp;
 462
 463	aprint_normal("\n");
 464	aprint_naive("\n");
 465
 466	sc->sc_dev = self;
 467
 468	if (ata_addref(chp))
 469		return;
 470
 471	RUN_ONCE(&poolinit_ctrl, atabus_xferpool_init);
 472
 473	initq = malloc(sizeof(*initq), M_DEVBUF, M_WAITOK);
 474	initq->atabus_sc = sc;
 475	TAILQ_INSERT_TAIL(&atabus_initq_head, initq, atabus_initq);
 476	config_pending_incr();
 477
 478	if ((error = kthread_create(PRI_NONE, 0, NULL, atabus_thread, sc,
 479	    &chp->ch_thread, "%s", device_xname(self))) != 0)
 480		aprint_error_dev(self,
 481		    "unable to create kernel thread: error %d\n", error);
 482
 483	if (!pmf_device_register(self, atabus_suspend, atabus_resume))
 484		aprint_error_dev(self, "couldn't establish power handler\n");
 485}
 486
 487/*
 488 * atabus_detach:
 489 *
 490 *	Autoconfiguration detach routine.
 491 */
 492static int
 493atabus_detach(device_t self, int flags)
 494{
 495	struct atabus_softc *sc = device_private(self);
 496	struct ata_channel *chp = sc->sc_chan;
 497	device_t dev = NULL;
 498	int s, i, error = 0;
 499
 500	/* Shutdown the channel. */
 501	s = splbio();		/* XXX ALSO NEED AN INTERLOCK HERE. */
 502	chp->ch_flags |= ATACH_SHUTDOWN;
 503	splx(s);
 504
 505	wakeup(&chp->ch_thread);
 506
 507	while (chp->ch_thread != NULL)
 508		//(void) tsleep(&chp->ch_flags, PRIBIO, "atadown", 0);
 509
 510
 511	/*
 512	 * Detach atapibus and its children.
 513	 */
 514	if ((dev = chp->atapibus) != NULL) {
 515		ATADEBUG_PRINT(("atabus_detach: %s: detaching %s\n",
 516		    device_xname(self), device_xname(dev)), DEBUG_DETACH);
 517
 518		error = config_detach(dev, flags);
 519		if (error)
 520			goto out;
 521		KASSERT(chp->atapibus == NULL);
 522	}
 523
 524	/*
 525	 * Detach our other children.
 526	 */
 527	for (i = 0; i < chp->ch_ndrive; i++) {
 528		if (chp->ch_drive[i].drive_flags & DRIVE_ATAPI)
 529			continue;
 530		if ((dev = chp->ata_drives[i]) != NULL) {
 531			ATADEBUG_PRINT(("%s.%d: %s: detaching %s\n", __func__,
 532			    __LINE__, device_xname(self), device_xname(dev)),
 533			    DEBUG_DETACH);
 534			KASSERT(chp->ch_drive[i].drv_softc ==
 535			        chp->ata_drives[i]);
 536			error = config_detach(dev, flags);
 537			if (error)
 538				goto out;
 539			KASSERT(chp->ata_drives[i] == NULL);
 540		}
 541	}
 542
 543 out:
 544#ifdef ATADEBUG
 545	if (dev != NULL && error != 0)
 546		ATADEBUG_PRINT(("%s: %s: error %d detaching %s\n", __func__,
 547		    device_xname(self), error, device_xname(dev)),
 548		    DEBUG_DETACH);
 549#endif /* ATADEBUG */
 550
 551	return (error);
 552}
 553
 554void
 555atabus_childdetached(device_t self, device_t child)
 556{
 557	bool found = false;
 558	struct atabus_softc *sc = device_private(self);
 559	struct ata_channel *chp = sc->sc_chan;
 560	int i;
 561
 562	/*
 563	 * atapibus detached.
 564	 */
 565	if (child == chp->atapibus) {
 566		chp->atapibus = NULL;
 567		found = true;
 568	}
 569
 570	/*
 571	 * Detach our other children.
 572	 */
 573	for (i = 0; i < chp->ch_ndrive; i++) {
 574		if (chp->ch_drive[i].drive_flags & DRIVE_ATAPI)
 575			continue;
 576		if (child == chp->ata_drives[i]) {
 577			KASSERT(chp->ata_drives[i] ==
 578			        chp->ch_drive[i].drv_softc);
 579			chp->ata_drives[i] = NULL;
 580			chp->ch_drive[i].drv_softc = NULL;
 581			chp->ch_drive[i].drive_flags = 0;
 582			found = true;
 583		}
 584	}
 585
 586	if (!found)
 587	  return;
 588		/*panic("%s: unknown child %p", device_xname(self),
 589		    (const void *)child);*/
 590}
 591
 592/*CFATTACH_DECL3_NEW(ata_bus, sizeof(struct atabus_softc),
 593    atabus_match, atabus_attach, atabus_detach, NULL, NULL,
 594    atabus_childdetached, DVF_DETACH_SHUTDOWN);*/
 595
 596/*****************************************************************************
 597 * Common ATA bus operations.
 598 *****************************************************************************/
 599
 600/* Get the disk's parameters */
 601int
 602ata_get_params(struct ata_drive_datas *drvp, u_int8_t flags,
 603    struct ataparams *prms)
 604{
 605	struct ata_command ata_c;
 606	struct ata_channel *chp = drvp->chnl_softc;
 607	struct atac_softc *atac = chp->ch_atac;
 608	char *tb;
 609	int i, rv;
 610	u_int16_t *p;
 611
 612	ATADEBUG_PRINT(("%s\n", __func__), DEBUG_FUNCS);
 613
 614	tb = kmem_zalloc(DEV_BSIZE, KM_SLEEP);
 615	memset(prms, 0, sizeof(struct ataparams));
 616	memset(&ata_c, 0, sizeof(struct ata_command));
 617
 618	if (drvp->drive_flags & DRIVE_ATA) {
 619		ata_c.r_command = WDCC_IDENTIFY;
 620		ata_c.r_st_bmask = WDCS_DRDY;
 621		ata_c.r_st_pmask = WDCS_DRQ;
 622		ata_c.timeout = 3000; /* 3s */
 623	} else if (drvp->drive_flags & DRIVE_ATAPI) {
 624		ata_c.r_command = ATAPI_IDENTIFY_DEVICE;
 625		ata_c.r_st_bmask = 0;
 626		ata_c.r_st_pmask = WDCS_DRQ;
 627		ata_c.timeout = 10000; /* 10s */
 628	} else {
 629		ATADEBUG_PRINT(("ata_get_parms: no disks\n"),
 630		    DEBUG_FUNCS|DEBUG_PROBE);
 631		rv = CMD_ERR;
 632		goto out;
 633	}
 634	ata_c.flags = AT_READ | flags;
 635	ata_c.data = tb;
 636	ata_c.bcount = DEV_BSIZE;
 637	if ((*atac->atac_bustype_ata->ata_exec_command)(drvp,
 638						&ata_c) != ATACMD_COMPLETE) {
 639		ATADEBUG_PRINT(("ata_get_parms: wdc_exec_command failed\n"),
 640		    DEBUG_FUNCS|DEBUG_PROBE);
 641		rv = CMD_AGAIN;
 642		goto out;
 643	}
 644	if (ata_c.flags & (AT_ERROR | AT_TIMEOU | AT_DF)) {
 645		ATADEBUG_PRINT(("ata_get_parms: ata_c.flags=0x%x\n",
 646		    ata_c.flags), DEBUG_FUNCS|DEBUG_PROBE);
 647		rv = CMD_ERR;
 648		goto out;
 649	}
 650	/* if we didn't read any data something is wrong */
 651	if ((ata_c.flags & AT_XFDONE) == 0) {
 652		rv = CMD_ERR;
 653		goto out;
 654	}
 655
 656	/* Read in parameter block. */
 657	memcpy(prms, tb, sizeof(struct ataparams));
 658
 659	/*
 660	 * Shuffle string byte order.
 661	 * ATAPI NEC, Mitsumi and Pioneer drives and
 662	 * old ATA TDK CompactFlash cards
 663	 * have different byte order.
 664	 */
 665#if BYTE_ORDER == BIG_ENDIAN
 666# define M(n)	prms->atap_model[(n) ^ 1]
 667#else
 668# define M(n)	prms->atap_model[n]
 669#endif
 670	if (
 671#if BYTE_ORDER == BIG_ENDIAN
 672	    !
 673#endif
 674	    ((drvp->drive_flags & DRIVE_ATAPI) ?
 675	     ((M(0) == 'N' && M(1) == 'E') ||
 676	      (M(0) == 'F' && M(1) == 'X') ||
 677	      (M(0) == 'P' && M(1) == 'i')) :
 678	     ((M(0) == 'T' && M(1) == 'D' && M(2) == 'K')))) {
 679		rv = CMD_OK;
 680		goto out;
 681	     }
 682#undef M
 683	for (i = 0; i < sizeof(prms->atap_model); i += 2) {
 684		p = (u_int16_t *)(prms->atap_model + i);
 685		*p = bswap16(*p);
 686	}
 687	for (i = 0; i < sizeof(prms->atap_serial); i += 2) {
 688		p = (u_int16_t *)(prms->atap_serial + i);
 689		*p = bswap16(*p);
 690	}
 691	for (i = 0; i < sizeof(prms->atap_revision); i += 2) {
 692		p = (u_int16_t *)(prms->atap_revision + i);
 693		*p = bswap16(*p);
 694	}
 695
 696	rv = CMD_OK;
 697 out:
 698	kmem_free(tb, DEV_BSIZE);
 699	return rv;
 700}
 701
 702int
 703ata_set_mode(struct ata_drive_datas *drvp, u_int8_t mode, u_int8_t flags)
 704{
 705	struct ata_command ata_c;
 706	struct ata_channel *chp = drvp->chnl_softc;
 707	struct atac_softc *atac = chp->ch_atac;
 708
 709	ATADEBUG_PRINT(("ata_set_mode=0x%x\n", mode), DEBUG_FUNCS);
 710	memset(&ata_c, 0, sizeof(struct ata_command));
 711
 712	ata_c.r_command = SET_FEATURES;
 713	ata_c.r_st_bmask = 0;
 714	ata_c.r_st_pmask = 0;
 715	ata_c.r_features = WDSF_SET_MODE;
 716	ata_c.r_count = mode;
 717	ata_c.flags = flags;
 718	ata_c.timeout = 1000; /* 1s */
 719	if ((*atac->atac_bustype_ata->ata_exec_command)(drvp,
 720						&ata_c) != ATACMD_COMPLETE)
 721		return CMD_AGAIN;
 722	if (ata_c.flags & (AT_ERROR | AT_TIMEOU | AT_DF)) {
 723		return CMD_ERR;
 724	}
 725	return CMD_OK;
 726}
 727
 728#if NATA_DMA
 729void
 730ata_dmaerr(struct ata_drive_datas *drvp, int flags)
 731{
 732	/*
 733	 * Downgrade decision: if we get NERRS_MAX in NXFER.
 734	 * We start with n_dmaerrs set to NERRS_MAX-1 so that the
 735	 * first error within the first NXFER ops will immediatly trigger
 736	 * a downgrade.
 737	 * If we got an error and n_xfers is bigger than NXFER reset counters.
 738	 */
 739	drvp->n_dmaerrs++;
 740	if (drvp->n_dmaerrs >= NERRS_MAX && drvp->n_xfers <= NXFER) {
 741		ata_downgrade_mode(drvp, flags);
 742		drvp->n_dmaerrs = NERRS_MAX-1;
 743		drvp->n_xfers = 0;
 744		return;
 745	}
 746	if (drvp->n_xfers > NXFER) {
 747		drvp->n_dmaerrs = 1; /* just got an error */
 748		drvp->n_xfers = 1; /* restart counting from this error */
 749	}
 750}
 751#endif	/* NATA_DMA */
 752
 753/*
 754 * freeze the queue and wait for the controller to be idle. Caller has to
 755 * unfreeze/restart the queue
 756 */
 757void
 758ata_queue_idle(struct ata_queue *queue)
 759{
 760	int s = splbio();
 761	queue->queue_freeze++;
 762	while (queue->active_xfer != NULL) {
 763		queue->queue_flags |= QF_IDLE_WAIT;
 764		tsleep(&queue->queue_flags, PRIBIO, "qidl", 0);
 765	}
 766	splx(s);
 767}
 768
 769/*
 770 * Add a command to the queue and start controller.
 771 *
 772 * MUST BE CALLED AT splbio()!
 773 */
 774void
 775ata_exec_xfer(struct ata_channel *chp, struct ata_xfer *xfer)
 776{
 777
 778	ATADEBUG_PRINT(("ata_exec_xfer %p channel %d drive %d\n", xfer,
 779	    chp->ch_channel, xfer->c_drive), DEBUG_XFERS);
 780
 781	/* complete xfer setup */
 782	xfer->c_chp = chp;
 783
 784	/* insert at the end of command list */
 785	TAILQ_INSERT_TAIL(&chp->ch_queue->queue_xfer, xfer, c_xferchain);
 786	ATADEBUG_PRINT(("atastart from ata_exec_xfer, flags 0x%x\n",
 787	    chp->ch_flags), DEBUG_XFERS);
 788	/*
 789	 * if polling and can sleep, wait for the xfer to be at head of queue
 790	 */
 791	if ((xfer->c_flags & (C_POLL | C_WAIT)) ==  (C_POLL | C_WAIT)) {
 792		while (chp->ch_queue->active_xfer != NULL ||
 793		    TAILQ_FIRST(&chp->ch_queue->queue_xfer) != xfer) {
 794			xfer->c_flags |= C_WAITACT;
 795			tsleep(xfer, PRIBIO, "ataact", 0);
 796			xfer->c_flags &= ~C_WAITACT;
 797			if (xfer->c_flags & C_FREE) {
 798				ata_free_xfer(chp, xfer);
 799				return;
 800			}
 801		}
 802	}
 803	atastart(chp);
 804}
 805
 806/*
 807 * Start I/O on a controller, for the given channel.
 808 * The first xfer may be not for our channel if the channel queues
 809 * are shared.
 810 *
 811 * MUST BE CALLED AT splbio()!
 812 */
 813void
 814atastart(struct ata_channel *chp)
 815{
 816	struct atac_softc *atac = chp->ch_atac;
 817	struct ata_xfer *xfer;
 818
 819#ifdef ATA_DEBUG
 820	int spl1, spl2;
 821
 822	spl1 = splbio();
 823	spl2 = splbio();
 824	if (spl2 != spl1) {
 825		printf("atastart: not at splbio()\n");
 826		//panic("atastart");
 827	}
 828	splx(spl2);
 829	splx(spl1);
 830#endif /* ATA_DEBUG */
 831
 832	/* is there a xfer ? */
 833	if ((xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer)) == NULL)
 834		return;
 835
 836	/* adjust chp, in case we have a shared queue */
 837	chp = xfer->c_chp;
 838
 839	if (chp->ch_queue->active_xfer != NULL) {
 840		return; /* channel aleady active */
 841	}
 842	if (__predict_false(chp->ch_queue->queue_freeze > 0)) {
 843		if (chp->ch_queue->queue_flags & QF_IDLE_WAIT) {
 844			chp->ch_queue->queue_flags &= ~QF_IDLE_WAIT;
 845			wakeup(&chp->ch_queue->queue_flags);
 846		}
 847		return; /* queue frozen */
 848	}
 849	/*
 850	 * if someone is waiting for the command to be active, wake it up
 851	 * and let it process the command
 852	 */
 853	if (xfer->c_flags & C_WAITACT) {
 854		ATADEBUG_PRINT(("atastart: xfer %p channel %d drive %d "
 855		    "wait active\n", xfer, chp->ch_channel, xfer->c_drive),
 856		    DEBUG_XFERS);
 857		wakeup(xfer);
 858		return;
 859	}
 860#ifdef DIAGNOSTIC
 861	if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0)
 862		//panic("atastart: channel waiting for irq");
 863#endif
 864	if (atac->atac_claim_hw)
 865		if (!(*atac->atac_claim_hw)(chp, 0))
 866			return;
 867
 868	ATADEBUG_PRINT(("atastart: xfer %p channel %d drive %d\n", xfer,
 869	    chp->ch_channel, xfer->c_drive), DEBUG_XFERS);
 870	if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_RESET) {
 871		chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_RESET;
 872		chp->ch_drive[xfer->c_drive].state = 0;
 873	}
 874	chp->ch_queue->active_xfer = xfer;
 875	TAILQ_REMOVE(&chp->ch_queue->queue_xfer, xfer, c_xferchain);
 876
 877	if (atac->atac_cap & ATAC_CAP_NOIRQ)
 878		KASSERT(xfer->c_flags & C_POLL);
 879
 880	xfer->c_start(chp, xfer);
 881}
 882
 883struct ata_xfer *
 884ata_get_xfer(int flags)
 885{
 886	struct ata_xfer *xfer;
 887	int s;
 888
 889	s = splbio();
 890	xfer = pool_get(&ata_xfer_pool,
 891	    ((flags & ATAXF_NOSLEEP) != 0 ? PR_NOWAIT : PR_WAITOK));
 892	splx(s);
 893	if (xfer != NULL) {
 894		memset(xfer, 0, sizeof(struct ata_xfer));
 895	}
 896	return xfer;
 897}
 898
 899void
 900ata_free_xfer(struct ata_channel *chp, struct ata_xfer *xfer)
 901{
 902	struct atac_softc *atac = chp->ch_atac;
 903	int s;
 904
 905	if (xfer->c_flags & C_WAITACT) {
 906		/* Someone is waiting for this xfer, so we can't free now */
 907		xfer->c_flags |= C_FREE;
 908		wakeup(xfer);
 909		return;
 910	}
 911
 912#if NATA_PIOBM		/* XXX wdc dependent code */
 913	if (xfer->c_flags & C_PIOBM) {
 914		struct wdc_softc *wdc = CHAN_TO_WDC(chp);
 915
 916		/* finish the busmastering PIO */
 917		(*wdc->piobm_done)(wdc->dma_arg,
 918		    chp->ch_channel, xfer->c_drive);
 919		chp->ch_flags &= ~(ATACH_DMA_WAIT | ATACH_PIOBM_WAIT | ATACH_IRQ_WAIT);
 920	}
 921#endif
 922
 923	if (atac->atac_free_hw)
 924		(*atac->atac_free_hw)(chp);
 925	s = splbio();
 926	pool_put(&ata_xfer_pool, xfer);
 927	splx(s);
 928}
 929
 930/*
 931 * Kill off all pending xfers for a ata_channel.
 932 *
 933 * Must be called at splbio().
 934 */
 935void
 936ata_kill_pending(struct ata_drive_datas *drvp)
 937{
 938	struct ata_channel *chp = drvp->chnl_softc;
 939	struct ata_xfer *xfer, *next_xfer;
 940	int s = splbio();
 941
 942	for (xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer);
 943	    xfer != NULL; xfer = next_xfer) {
 944		next_xfer = TAILQ_NEXT(xfer, c_xferchain);
 945		if (xfer->c_chp != chp || xfer->c_drive != drvp->drive)
 946			continue;
 947		TAILQ_REMOVE(&chp->ch_queue->queue_xfer, xfer, c_xferchain);
 948		(*xfer->c_kill_xfer)(chp, xfer, KILL_GONE);
 949	}
 950
 951	while ((xfer = chp->ch_queue->active_xfer) != NULL) {
 952		if (xfer->c_chp == chp && xfer->c_drive == drvp->drive) {
 953			drvp->drive_flags |= DRIVE_WAITDRAIN;
 954			//(void) tsleep(&chp->ch_queue->active_xfer,PRIBIO, "atdrn", 0);
 955		} else {
 956			/* no more xfer for us */
 957			break;
 958		}
 959	}
 960	splx(s);
 961}
 962
 963/*
 964 * ata_reset_channel:
 965 *
 966 *	Reset and ATA channel.
 967 *
 968 *	MUST BE CALLED AT splbio()!
 969 */
 970void
 971ata_reset_channel(struct ata_channel *chp, int flags)
 972{
 973	struct atac_softc *atac = chp->ch_atac;
 974	int drive;
 975
 976#ifdef ATA_DEBUG
 977	int spl1, spl2;
 978
 979	spl1 = splbio();
 980	spl2 = splbio();
 981	if (spl2 != spl1) {
 982		printf("ata_reset_channel: not at splbio()\n");
 983		//panic("ata_reset_channel");
 984	}
 985	splx(spl2);
 986	splx(spl1);
 987#endif /* ATA_DEBUG */
 988
 989	chp->ch_queue->queue_freeze++;
 990
 991	/*
 992	 * If we can poll or wait it's OK, otherwise wake up the
 993	 * kernel thread to do it for us.
 994	 */
 995	ATADEBUG_PRINT(("ata_reset_channel flags 0x%x ch_flags 0x%x\n",
 996	    flags, chp->ch_flags), DEBUG_FUNCS | DEBUG_XFERS);
 997	if ((flags & (AT_POLL | AT_WAIT)) == 0) {
 998		if (chp->ch_flags & ATACH_TH_RESET) {
 999			/* No need to schedule a reset more than one time. */
1000			chp->ch_queue->queue_freeze--;
1001			return;
1002		}
1003		chp->ch_flags |= ATACH_TH_RESET;
1004		chp->ch_reset_flags = flags & (AT_RST_EMERG | AT_RST_NOCMD);
1005		wakeup(&chp->ch_thread);
1006		return;
1007	}
1008
1009	(*atac->atac_bustype_ata->ata_reset_channel)(chp, flags);
1010
1011	for (drive = 0; drive < chp->ch_ndrive; drive++)
1012		chp->ch_drive[drive].state = 0;
1013
1014	chp->ch_flags &= ~ATACH_TH_RESET;
1015	if ((flags & AT_RST_EMERG) == 0)  {
1016		chp->ch_queue->queue_freeze--;
1017		atastart(chp);
1018	} else {
1019		/* make sure that we can use polled commands */
1020		TAILQ_INIT(&chp->ch_queue->queue_xfer);
1021		chp->ch_queue->queue_freeze = 0;
1022		chp->ch_queue->active_xfer = NULL;
1023	}
1024}
1025
1026int
1027ata_addref(struct ata_channel *chp)
1028{
1029	struct atac_softc *atac = chp->ch_atac;
1030	struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic;
1031	int s, error = 0;
1032
1033	s = splbio();
1034	if (adapt->adapt_refcnt++ == 0 &&
1035	    adapt->adapt_enable != NULL) {
1036		error = (*adapt->adapt_enable)(atac->atac_dev, 1);
1037		if (error)
1038			adapt->adapt_refcnt--;
1039	}
1040	splx(s);
1041	return (error);
1042}
1043
1044void
1045ata_delref(struct ata_channel *chp)
1046{
1047	struct atac_softc *atac = chp->ch_atac;
1048	struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic;
1049	int s;
1050
1051	s = splbio();
1052	if (adapt->adapt_refcnt-- == 1 &&
1053	    adapt->adapt_enable != NULL)
1054		(void) (*adapt->adapt_enable)(atac->atac_dev, 0);
1055	splx(s);
1056}
1057
1058void
1059ata_print_modes(struct ata_channel *chp)
1060{
1061	struct atac_softc *atac = chp->ch_atac;
1062	int drive;
1063	struct ata_drive_datas *drvp;
1064
1065	for (drive = 0; drive < chp->ch_ndrive; drive++) {
1066		drvp = &chp->ch_drive[drive];
1067		if ((drvp->drive_flags & DRIVE) == 0 || drvp->drv_softc == NULL)
1068			continue;
1069		aprint_verbose("%s(%s:%d:%d): using PIO mode %d",
1070			device_xname(drvp->drv_softc),
1071			device_xname(atac->atac_dev),
1072			chp->ch_channel, drvp->drive, drvp->PIO_mode);
1073#if NATA_DMA
1074		if (drvp->drive_flags & DRIVE_DMA)
1075			aprint_verbose(", DMA mode %d", drvp->DMA_mode);
1076#if NATA_UDMA
1077		if (drvp->drive_flags & DRIVE_UDMA) {
1078			aprint_verbose(", Ultra-DMA mode %d", drvp->UDMA_mode);
1079			if (drvp->UDMA_mode == 2)
1080				aprint_verbose(" (Ultra/33)");
1081			else if (drvp->UDMA_mode == 4)
1082				aprint_verbose(" (Ultra/66)");
1083			else if (drvp->UDMA_mode == 5)
1084				aprint_verbose(" (Ultra/100)");
1085			else if (drvp->UDMA_mode == 6)
1086				aprint_verbose(" (Ultra/133)");
1087		}
1088#endif	/* NATA_UDMA */
1089#endif	/* NATA_DMA */
1090#if NATA_DMA || NATA_PIOBM
1091		if (0
1092#if NATA_DMA
1093		    || (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA))
1094#endif
1095#if NATA_PIOBM
1096		    /* PIOBM capable controllers use DMA for PIO commands */
1097		    || (atac->atac_cap & ATAC_CAP_PIOBM)
1098#endif
1099		    )
1100			aprint_verbose(" (using DMA)");
1101#endif	/* NATA_DMA || NATA_PIOBM */
1102		aprint_verbose("\n");
1103	}
1104}
1105
1106#if NATA_DMA
1107/*
1108 * downgrade the transfer mode of a drive after an error. return 1 if
1109 * downgrade was possible, 0 otherwise.
1110 *
1111 * MUST BE CALLED AT splbio()!
1112 */
1113int
1114ata_downgrade_mode(struct ata_drive_datas *drvp, int flags)
1115{
1116	struct ata_channel *chp = drvp->chnl_softc;
1117	struct atac_softc *atac = chp->ch_atac;
1118	device_t drv_dev = drvp->drv_softc;
1119	int cf_flags = device_cfdata(drv_dev)->cf_flags;
1120
1121	/* if drive or controller don't know its mode, we can't do much */
1122	if ((drvp->drive_flags & DRIVE_MODE) == 0 ||
1123	    (atac->atac_set_modes == NULL))
1124		return 0;
1125	/* current drive mode was set by a config flag, let it this way */
1126	if ((cf_flags & ATA_CONFIG_PIO_SET) ||
1127	    (cf_flags & ATA_CONFIG_DMA_SET) ||
1128	    (cf_flags & ATA_CONFIG_UDMA_SET))
1129		return 0;
1130
1131#if NATA_UDMA
1132	/*
1133	 * If we were using Ultra-DMA mode, downgrade to the next lower mode.
1134	 */
1135	if ((drvp->drive_flags & DRIVE_UDMA) && drvp->UDMA_mode >= 2) {
1136		drvp->UDMA_mode--;
1137		aprint_error_dev(drv_dev,
1138		    "transfer error, downgrading to Ultra-DMA mode %d\n",
1139		    drvp->UDMA_mode);
1140	}
1141#endif
1142
1143	/*
1144	 * If we were using ultra-DMA, don't downgrade to multiword DMA.
1145	 */
1146	else if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) {
1147		drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA);
1148		drvp->PIO_mode = drvp->PIO_cap;
1149		aprint_error_dev(drv_dev,
1150		    "transfer error, downgrading to PIO mode %d\n",
1151		    drvp->PIO_mode);
1152	} else /* already using PIO, can't downgrade */
1153		return 0;
1154
1155	(*atac->atac_set_modes)(chp);
1156	ata_print_modes(chp);
1157	/* reset the channel, which will schedule all drives for setup */
1158	ata_reset_channel(chp, flags | AT_RST_NOCMD);
1159	return 1;
1160}
1161#endif	/* NATA_DMA */
1162
1163/*
1164 * Probe drive's capabilities, for use by the controller later
1165 * Assumes drvp points to an existing drive.
1166 */
1167void
1168ata_probe_caps(struct ata_drive_datas *drvp)
1169{
1170	struct ataparams params, params2;
1171	struct ata_channel *chp = drvp->chnl_softc;
1172	struct atac_softc *atac = chp->ch_atac;
1173	device_t drv_dev = drvp->drv_softc;
1174	int i, printed, s;
1175	const char *sep = "";
1176	int cf_flags;
1177
1178	if (ata_get_params(drvp, AT_WAIT, &params) != CMD_OK) {
1179		/* IDENTIFY failed. Can't tell more about the device */
1180		return;
1181	}
1182	if ((atac->atac_cap & (ATAC_CAP_DATA16 | ATAC_CAP_DATA32)) ==
1183	    (ATAC_CAP_DATA16 | ATAC_CAP_DATA32)) {
1184		/*
1185		 * Controller claims 16 and 32 bit transfers.
1186		 * Re-do an IDENTIFY with 32-bit transfers,
1187		 * and compare results.
1188		 */
1189		s = splbio();
1190		drvp->drive_flags |= DRIVE_CAP32;
1191		splx(s);
1192		ata_get_params(drvp, AT_WAIT, &params2);
1193		if (memcmp(&params, &params2, sizeof(struct ataparams)) != 0) {
1194			/* Not good. fall back to 16bits */
1195			s = splbio();
1196			drvp->drive_flags &= ~DRIVE_CAP32;
1197			splx(s);
1198		} else {
1199			aprint_verbose_dev(drv_dev, "32-bit data port\n");
1200		}
1201	}
1202#if 0 /* Some ultra-DMA drives claims to only support ATA-3. sigh */
1203	if (params.atap_ata_major > 0x01 &&
1204	    params.atap_ata_major != 0xffff) {
1205		for (i = 14; i > 0; i--) {
1206			if (params.atap_ata_major & (1 << i)) {
1207				aprint_verbose_dev(drv_dev,
1208				    "ATA version %d\n", i);
1209				drvp->ata_vers = i;
1210				break;
1211			}
1212		}
1213	}
1214#endif
1215
1216	/* An ATAPI device is at last PIO mode 3 */
1217	if (drvp->drive_flags & DRIVE_ATAPI)
1218		drvp->PIO_mode = 3;
1219
1220	/*
1221	 * It's not in the specs, but it seems that some drive
1222	 * returns 0xffff in atap_extensions when this field is invalid
1223	 */
1224	if (params.atap_extensions != 0xffff &&
1225	    (params.atap_extensions & WDC_EXT_MODES)) {
1226		printed = 0;
1227		/*
1228		 * XXX some drives report something wrong here (they claim to
1229		 * support PIO mode 8 !). As mode is coded on 3 bits in
1230		 * SET FEATURE, limit it to 7 (so limit i to 4).
1231		 * If higher mode than 7 is found, abort.
1232		 */
1233		for (i = 7; i >= 0; i--) {
1234			if ((params.atap_piomode_supp & (1 << i)) == 0)
1235				continue;
1236			if (i > 4)
1237				return;
1238			/*
1239			 * See if mode is accepted.
1240			 * If the controller can't set its PIO mode,
1241			 * assume the defaults are good, so don't try
1242			 * to set it
1243			 */
1244			if (atac->atac_set_modes)
1245				/*
1246				 * It's OK to pool here, it's fast enough
1247				 * to not bother waiting for interrupt
1248				 */
1249				if (ata_set_mode(drvp, 0x08 | (i + 3),
1250				   AT_WAIT) != CMD_OK)
1251					continue;
1252			if (!printed) {
1253				aprint_verbose_dev(drv_dev,
1254				    "drive supports PIO mode %d", i + 3);
1255				sep = ",";
1256				printed = 1;
1257			}
1258			/*
1259			 * If controller's driver can't set its PIO mode,
1260			 * get the highter one for the drive.
1261			 */
1262			if (atac->atac_set_modes == NULL ||
1263			    atac->atac_pio_cap >= i + 3) {
1264				drvp->PIO_mode = i + 3;
1265				drvp->PIO_cap = i + 3;
1266				break;
1267			}
1268		}
1269		if (!printed) {
1270			/*
1271			 * We didn't find a valid PIO mode.
1272			 * Assume the values returned for DMA are buggy too
1273			 */
1274			return;
1275		}
1276		s = splbio();
1277		drvp->drive_flags |= DRIVE_MODE;
1278		splx(s);
1279		printed = 0;
1280		for (i = 7; i >= 0; i--) {
1281			if ((params.atap_dmamode_supp & (1 << i)) == 0)
1282				continue;
1283#if NATA_DMA
1284			if ((atac->atac_cap & ATAC_CAP_DMA) &&
1285			    atac->atac_set_modes != NULL)
1286				if (ata_set_mode(drvp, 0x20 | i, AT_WAIT)
1287				    != CMD_OK)
1288					continue;
1289#endif
1290			if (!printed) {
1291				aprint_verbose("%s DMA mode %d", sep, i);
1292				sep = ",";
1293				printed = 1;
1294			}
1295#if NATA_DMA
1296			if (atac->atac_cap & ATAC_CAP_DMA) {
1297				if (atac->atac_set_modes != NULL &&
1298				    atac->atac_dma_cap < i)
1299					continue;
1300				drvp->DMA_mode = i;
1301				drvp->DMA_cap = i;
1302				s = splbio();
1303				drvp->drive_flags |= DRIVE_DMA;
1304				splx(s);
1305			}
1306#endif
1307			break;
1308		}
1309		if (params.atap_extensions & WDC_EXT_UDMA_MODES) {
1310			printed = 0;
1311			for (i = 7; i >= 0; i--) {
1312				if ((params.atap_udmamode_supp & (1 << i))
1313				    == 0)
1314					continue;
1315#if NATA_UDMA
1316				if (atac->atac_set_modes != NULL &&
1317				    (atac->atac_cap & ATAC_CAP_UDMA))
1318					if (ata_set_mode(drvp, 0x40 | i,
1319					    AT_WAIT) != CMD_OK)
1320						continue;
1321#endif
1322				if (!printed) {
1323					aprint_verbose("%s Ultra-DMA mode %d",
1324					    sep, i);
1325					if (i == 2)
1326						aprint_verbose(" (Ultra/33)");
1327					else if (i == 4)
1328						aprint_verbose(" (Ultra/66)");
1329					else if (i == 5)
1330						aprint_verbose(" (Ultra/100)");
1331					else if (i == 6)
1332						aprint_verbose(" (Ultra/133)");
1333					sep = ",";
1334					printed = 1;
1335				}
1336#if NATA_UDMA
1337				if (atac->atac_cap & ATAC_CAP_UDMA) {
1338					if (atac->atac_set_modes != NULL &&
1339					    atac->atac_udma_cap < i)
1340						continue;
1341					drvp->UDMA_mode = i;
1342					drvp->UDMA_cap = i;
1343					s = splbio();
1344					drvp->drive_flags |= DRIVE_UDMA;
1345					splx(s);
1346				}
1347#endif
1348				break;
1349			}
1350		}
1351		aprint_verbose("\n");
1352	}
1353
1354	s = splbio();
1355	drvp->drive_flags &= ~DRIVE_NOSTREAM;
1356	if (drvp->drive_flags & DRIVE_ATAPI) {
1357		if (atac->atac_cap & ATAC_CAP_ATAPI_NOSTREAM)
1358			drvp->drive_flags |= DRIVE_NOSTREAM;
1359	} else {
1360		if (atac->atac_cap & ATAC_CAP_ATA_NOSTREAM)
1361			drvp->drive_flags |= DRIVE_NOSTREAM;
1362	}
1363	splx(s);
1364
1365	/* Try to guess ATA version here, if it didn't get reported */
1366	if (drvp->ata_vers == 0) {
1367#if NATA_UDMA
1368		if (drvp->drive_flags & DRIVE_UDMA)
1369			drvp->ata_vers = 4; /* should be at last ATA-4 */
1370		else
1371#endif
1372		if (drvp->PIO_cap > 2)
1373			drvp->ata_vers = 2; /* should be at last ATA-2 */
1374	}
1375	cf_flags = device_cfdata(drv_dev)->cf_flags;
1376	if (cf_flags & ATA_CONFIG_PIO_SET) {
1377		s = splbio();
1378		drvp->PIO_mode =
1379		    (cf_flags & ATA_CONFIG_PIO_MODES) >> ATA_CONFIG_PIO_OFF;
1380		drvp->drive_flags |= DRIVE_MODE;
1381		splx(s);
1382	}
1383#if NATA_DMA
1384	if ((atac->atac_cap & ATAC_CAP_DMA) == 0) {
1385		/* don't care about DMA modes */
1386		return;
1387	}
1388	if (cf_flags & ATA_CONFIG_DMA_SET) {
1389		s = splbio();
1390		if ((cf_flags & ATA_CONFIG_DMA_MODES) ==
1391		    ATA_CONFIG_DMA_DISABLE) {
1392			drvp->drive_flags &= ~DRIVE_DMA;
1393		} else {
1394			drvp->DMA_mode = (cf_flags & ATA_CONFIG_DMA_MODES) >>
1395			    ATA_CONFIG_DMA_OFF;
1396			drvp->drive_flags |= DRIVE_DMA | DRIVE_MODE;
1397		}
1398		splx(s);
1399	}
1400#if NATA_UDMA
1401	if ((atac->atac_cap & ATAC_CAP_UDMA) == 0) {
1402		/* don't care about UDMA modes */
1403		return;
1404	}
1405	if (cf_flags & ATA_CONFIG_UDMA_SET) {
1406		s = splbio();
1407		if ((cf_flags & ATA_CONFIG_UDMA_MODES) ==
1408		    ATA_CONFIG_UDMA_DISABLE) {
1409			drvp->drive_flags &= ~DRIVE_UDMA;
1410		} else {
1411			drvp->UDMA_mode = (cf_flags & ATA_CONFIG_UDMA_MODES) >>
1412			    ATA_CONFIG_UDMA_OFF;
1413			drvp->drive_flags |= DRIVE_UDMA | DRIVE_MODE;
1414		}
1415		splx(s);
1416	}
1417#endif	/* NATA_UDMA */
1418#endif	/* NATA_DMA */
1419}
1420
1421/* management of the /dev/atabus* devices */
1422int
1423atabusopen(dev_t dev, int flag, int fmt, struct lwp *l)
1424{
1425	struct atabus_softc *sc;
1426	int error;
1427
1428	sc = device_lookup_private(&atabus_cd, minor(dev));
1429	if (sc == NULL)
1430		return (ENXIO);
1431
1432	if (sc->sc_flags & ATABUSCF_OPEN)
1433		return (EBUSY);
1434
1435	if ((error = ata_addref(sc->sc_chan)) != 0)
1436		return (error);
1437
1438	sc->sc_flags |= ATABUSCF_OPEN;
1439
1440	return (0);
1441}
1442
1443
1444int
1445atabusclose(dev_t dev, int flag, int fmt, struct lwp *l)
1446{
1447	struct atabus_softc *sc =
1448	    device_lookup_private(&atabus_cd, minor(dev));
1449
1450	ata_delref(sc->sc_chan);
1451
1452	sc->sc_flags &= ~ATABUSCF_OPEN;
1453
1454	return (0);
1455}
1456
1457int
1458atabusioctl(dev_t dev, u_long cmd, void *addr, int flag, struct lwp *l)
1459{
1460	struct atabus_softc *sc =
1461	    device_lookup_private(&atabus_cd, minor(dev));
1462	struct ata_channel *chp = sc->sc_chan;
1463	int min_drive, max_drive, drive;
1464	int error;
1465	int s;
1466
1467	/*
1468	 * Enforce write permission for ioctls that change the
1469	 * state of the bus.  Host adapter specific ioctls must
1470	 * be checked by the adapter driver.
1471	 */
1472	switch (cmd) {
1473	case ATABUSIOSCAN:
1474	case ATABUSIODETACH:
1475	case ATABUSIORESET:
1476		if ((flag & FWRITE) == 0)
1477			return (EBADF);
1478	}
1479
1480	switch (cmd) {
1481	case ATABUSIORESET:
1482		s = splbio();
1483		ata_reset_channel(sc->sc_chan, AT_WAIT | AT_POLL);
1484		splx(s);
1485		return 0;
1486	case ATABUSIOSCAN:
1487	{
1488#if 0
1489		struct atabusioscan_args *a=
1490		    (struct atabusioscan_args *)addr;
1491#endif
1492		if ((chp->ch_drive[0].drive_flags & DRIVE_OLD) ||
1493		    (chp->ch_drive[1].drive_flags & DRIVE_OLD))
1494			return (EOPNOTSUPP);
1495		return (EOPNOTSUPP);
1496	}
1497	case ATABUSIODETACH:
1498	{
1499		struct atabusioscan_args *a=
1500		    (struct atabusioscan_args *)addr;
1501		if ((chp->ch_drive[0].drive_flags & DRIVE_OLD) ||
1502		    (chp->ch_drive[1].drive_flags & DRIVE_OLD))
1503			return (EOPNOTSUPP);
1504		switch (a->at_dev) {
1505		case -1:
1506			min_drive = 0;
1507			max_drive = 1;
1508			break;
1509		case 0:
1510		case 1:
1511			min_drive = max_drive = a->at_dev;
1512			break;
1513		default:
1514			return (EINVAL);
1515		}
1516		for (drive = min_drive; drive <= max_drive; drive++) {
1517			if (chp->ch_drive[drive].drv_softc != NULL) {
1518				error = config_detach(
1519				    chp->ch_drive[drive].drv_softc, 0);
1520				if (error)
1521					return (error);
1522				KASSERT(chp->ch_drive[drive].drv_softc == NULL);
1523			}
1524		}
1525		return 0;
1526	}
1527	default:
1528		return ENOTTY;
1529	}
1530}
1531
1532static bool
1533atabus_suspend(device_t dv, const pmf_qual_t *qual)
1534{
1535	struct atabus_softc *sc = device_private(dv);
1536	struct ata_channel *chp = sc->sc_chan;
1537
1538	ata_queue_idle(chp->ch_queue);
1539
1540	return true;
1541}
1542
1543static bool
1544atabus_resume(device_t dv, const pmf_qual_t *qual)
1545{
1546	struct atabus_softc *sc = device_private(dv);
1547	struct ata_channel *chp = sc->sc_chan;
1548	int s;
1549
1550	/*
1551	 * XXX joerg: with wdc, the first channel unfreezes the controler.
1552	 * Move this the reset and queue idling into wdc.
1553	 */
1554	s = splbio();
1555	if (chp->ch_queue->queue_freeze == 0) {
1556		splx(s);
1557		return true;
1558	}
1559	KASSERT(chp->ch_queue->queue_freeze > 0);
1560	/* unfreeze the queue and reset drives */
1561	chp->ch_queue->queue_freeze--;
1562	ata_reset_channel(chp, AT_WAIT);
1563	splx(s);
1564
1565	return true;
1566}