/atapi/ata.c

http://rtems-atapi.googlecode.com/ · C · 1566 lines · 1114 code · 175 blank · 277 comment · 300 complexity · 2d63d13c75eb79eadf1a5a1cab61293b MD5 · raw file

  1. /* $NetBSD: ata.c,v 1.113 2010/03/28 20:46:18 snj Exp $ */
  2. /*
  3. * Copyright (c) 1998, 2001 Manuel Bouyer. All rights reserved.
  4. *
  5. * Redistribution and use in source and binary forms, with or without
  6. * modification, are permitted provided that the following conditions
  7. * are met:
  8. * 1. Redistributions of source code must retain the above copyright
  9. * notice, this list of conditions and the following disclaimer.
  10. * 2. Redistributions in binary form must reproduce the above copyright
  11. * notice, this list of conditions and the following disclaimer in the
  12. * documentation and/or other materials provided with the distribution.
  13. *
  14. * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  15. * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  16. * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  17. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  18. * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  19. * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  20. * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  21. * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  22. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  23. * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  24. */
  25. //#include <rtems/bsd/sys/cdefs.h>
  26. #include <rtems/bsd/sys/queue.h>
  27. //__KERNEL_RCSID(0, "$NetBSD: ata.c,v 1.113 2010/03/28 20:46:18 snj Exp $");
  28. //#include "opt_ata.h"
  29. #include "../sys/quirk.h"
  30. //#include <sys/param.h>
  31. //#include <sys/systm.h>
  32. #include <sys/kernel.h> /*safe*/
  33. #include <sys/malloc.h> /*+-safe*/
  34. #include "../sys/device.h"
  35. #include "../sys/conf.h"
  36. #include <sys/fcntl.h> /*?*/
  37. #include <sys/proc.h> /*dummy*/
  38. #include "../sys/pool.h" /*dummy*/
  39. #include "../sys/kthread.h"
  40. //#include "../sys/errno.h"
  41. #include <errno.h>
  42. #include "ataio.h"
  43. #include "../sys/kmem.h"
  44. #include "../sys/simplelock.h"
  45. #include "../sys/intr.h"
  46. #include "../sys/bus.h"
  47. #include "../sys/once.h"
  48. #include "ataconf.h"
  49. #include "atareg.h"
  50. #include "atavar.h"
  51. #include "ic/wdcvar.h" /* for PIOBM */
  52. //#include "locators.h"
  53. //#include "atapibus.h"
  54. //#include "ataraid.h"
  55. #if NATARAID > 0
  56. #include <dev/ata/ata_raidvar.h>
  57. #endif
  58. #define DEBUG_FUNCS 0x08
  59. #define DEBUG_PROBE 0x10
  60. #define DEBUG_DETACH 0x20
  61. #define DEBUG_XFERS 0x40
  62. #ifdef ATADEBUG
  63. int atadebug_mask = 0;
  64. #define ATADEBUG_PRINT(args, level) \
  65. if (atadebug_mask & (level)) \
  66. printf args
  67. #else
  68. #define ATADEBUG_PRINT(args, level)
  69. #endif
  70. static struct pool ata_xfer_pool;
  71. /*
  72. * A queue of atabus instances, used to ensure the same bus probe order
  73. * for a given hardware configuration at each boot.
  74. */
  75. struct atabus_initq_head atabus_initq_head =
  76. TAILQ_HEAD_INITIALIZER(atabus_initq_head);
  77. struct simplelock atabus_interlock = SIMPLELOCK_INITIALIZER;
  78. /* kernel thread probing devices on a atabus. Only one probing at once */
  79. struct lwp *atabus_configlwp;
  80. /*****************************************************************************
  81. * ATA bus layer.
  82. *
  83. * ATA controllers attach an atabus instance, which handles probing the bus
  84. * for drives, etc.
  85. *****************************************************************************/
  86. dev_type_open(atabusopen);
  87. dev_type_close(atabusclose);
  88. dev_type_ioctl(atabusioctl);
  89. const struct cdevsw atabus_cdevsw = {
  90. atabusopen, atabusclose, noread, nowrite, atabusioctl,
  91. nostop, notty, nopoll, nommap, nokqfilter, D_OTHER
  92. };
  93. extern struct cfdriver atabus_cd;
  94. static void atabus_childdetached(device_t, device_t);
  95. static bool atabus_resume(device_t, const pmf_qual_t *);
  96. static bool atabus_suspend(device_t, const pmf_qual_t *);
  97. static void atabusconfig_thread(void *);
  98. /*
  99. * atabusprint:
  100. *
  101. * Autoconfiguration print routine used by ATA controllers when
  102. * attaching an atabus instance.
  103. */
  104. int
  105. atabusprint(void *aux, const char *pnp)
  106. {
  107. struct ata_channel *chan = aux;
  108. if (pnp)
  109. aprint_normal("atabus at %s", pnp);
  110. aprint_normal(" channel %d", chan->ch_channel);
  111. return (UNCONF);
  112. }
  113. /*
  114. * ataprint:
  115. *
  116. * Autoconfiguration print routine.
  117. */
  118. int
  119. ataprint(void *aux, const char *pnp)
  120. {
  121. struct ata_device *adev = aux;
  122. if (pnp)
  123. aprint_normal("wd at %s", pnp);
  124. aprint_normal(" drive %d", adev->adev_drv_data->drive);
  125. return (UNCONF);
  126. }
  127. /*
  128. * ata_channel_attach:
  129. *
  130. * Common parts of attaching an atabus to an ATA controller channel.
  131. */
  132. void
  133. ata_channel_attach(struct ata_channel *chp)
  134. {
  135. if (chp->ch_flags & ATACH_DISABLED)
  136. return;
  137. /* XXX callout_destroy */
  138. callout_init(&chp->ch_callout, 0);
  139. TAILQ_INIT(&chp->ch_queue->queue_xfer);
  140. chp->ch_queue->queue_freeze = 0;
  141. chp->ch_queue->queue_flags = 0;
  142. chp->ch_queue->active_xfer = NULL;
  143. chp->atabus = config_found_ia(chp->ch_atac->atac_dev, "ata", chp,
  144. atabusprint);
  145. }
  146. static void
  147. atabusconfig(struct atabus_softc *atabus_sc)
  148. {
  149. struct ata_channel *chp = atabus_sc->sc_chan;
  150. struct atac_softc *atac = chp->ch_atac;
  151. struct atabus_initq *atabus_initq = NULL;
  152. int i, s, error;
  153. /* we are in the atabus's thread context */
  154. s = splbio();
  155. chp->ch_flags |= ATACH_TH_RUN;
  156. splx(s);
  157. /* Probe for the drives. */
  158. /* XXX for SATA devices we will power up all drives at once */
  159. (*atac->atac_probe)(chp);
  160. ATADEBUG_PRINT(("atabusattach: ch_drive_flags 0x%x 0x%x\n",
  161. chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags),
  162. DEBUG_PROBE);
  163. /* next operations will occurs in a separate thread */
  164. s = splbio();
  165. chp->ch_flags &= ~ATACH_TH_RUN;
  166. splx(s);
  167. /* Make sure the devices probe in atabus order to avoid jitter. */
  168. simple_lock(&atabus_interlock);
  169. while(1) {
  170. atabus_initq = TAILQ_FIRST(&atabus_initq_head);
  171. if (atabus_initq->atabus_sc == atabus_sc)
  172. break;
  173. ltsleep(&atabus_initq_head, PRIBIO, "ata_initq", 0,
  174. &atabus_interlock);
  175. }
  176. simple_unlock(&atabus_interlock);
  177. /* If no drives, abort here */
  178. for (i = 0; i < chp->ch_ndrive; i++)
  179. if ((chp->ch_drive[i].drive_flags & DRIVE) != 0)
  180. break;
  181. if (i == chp->ch_ndrive)
  182. goto out;
  183. /* Shortcut in case we've been shutdown */
  184. if (chp->ch_flags & ATACH_SHUTDOWN)
  185. goto out;
  186. if ((error = kthread_create(PRI_NONE, 0, NULL, atabusconfig_thread,
  187. atabus_sc, &atabus_configlwp,
  188. "%scnf", device_xname(atac->atac_dev))) != 0)
  189. aprint_error_dev(atac->atac_dev,
  190. "unable to create config thread: error %d\n", error);
  191. return;
  192. out:
  193. simple_lock(&atabus_interlock);
  194. TAILQ_REMOVE(&atabus_initq_head, atabus_initq, atabus_initq);
  195. simple_unlock(&atabus_interlock);
  196. free(atabus_initq, M_DEVBUF);
  197. wakeup(&atabus_initq_head);
  198. ata_delref(chp);
  199. config_pending_decr();
  200. }
  201. /*
  202. * atabus_configthread: finish attach of atabus's childrens, in a separate
  203. * kernel thread.
  204. */
  205. static void
  206. atabusconfig_thread(void *arg)
  207. {
  208. struct atabus_softc *atabus_sc = arg;
  209. struct ata_channel *chp = atabus_sc->sc_chan;
  210. struct atac_softc *atac = chp->ch_atac;
  211. int i, s;
  212. struct atabus_initq *atabus_initq = NULL;
  213. simple_lock(&atabus_interlock);
  214. atabus_initq = TAILQ_FIRST(&atabus_initq_head);
  215. simple_unlock(&atabus_interlock);
  216. KASSERT(atabus_initq->atabus_sc == atabus_sc);
  217. /*
  218. * Attach an ATAPI bus, if needed.
  219. */
  220. for (i = 0; i < chp->ch_ndrive; i++) {
  221. if (chp->ch_drive[i].drive_flags & DRIVE_ATAPI) {
  222. #if NATAPIBUS > 0
  223. (*atac->atac_atapibus_attach)(atabus_sc);
  224. #else
  225. /*
  226. * Fake the autoconfig "not configured" message
  227. */
  228. aprint_normal("atapibus at %s not configured\n",
  229. device_xname(atac->atac_dev));
  230. chp->atapibus = NULL;
  231. s = splbio();
  232. for (i = 0; i < chp->ch_ndrive; i++)
  233. chp->ch_drive[i].drive_flags &= ~DRIVE_ATAPI;
  234. splx(s);
  235. #endif
  236. break;
  237. }
  238. }
  239. for (i = 0; i < chp->ch_ndrive; i++) {
  240. struct ata_device adev;
  241. if ((chp->ch_drive[i].drive_flags &
  242. (DRIVE_ATA | DRIVE_OLD)) == 0) {
  243. continue;
  244. }
  245. memset(&adev, 0, sizeof(struct ata_device));
  246. adev.adev_bustype = atac->atac_bustype_ata;
  247. adev.adev_channel = chp->ch_channel;
  248. adev.adev_openings = 1;
  249. adev.adev_drv_data = &chp->ch_drive[i];
  250. chp->ata_drives[i] = config_found_ia(atabus_sc->sc_dev,
  251. "ata_hl", &adev, ataprint);
  252. if (chp->ata_drives[i] != NULL)
  253. ata_probe_caps(&chp->ch_drive[i]);
  254. else {
  255. s = splbio();
  256. chp->ch_drive[i].drive_flags &=
  257. ~(DRIVE_ATA | DRIVE_OLD);
  258. splx(s);
  259. }
  260. }
  261. /* now that we know the drives, the controller can set its modes */
  262. if (atac->atac_set_modes) {
  263. (*atac->atac_set_modes)(chp);
  264. ata_print_modes(chp);
  265. }
  266. #if NATARAID > 0
  267. if (atac->atac_cap & ATAC_CAP_RAID)
  268. for (i = 0; i < chp->ch_ndrive; i++)
  269. if (chp->ata_drives[i] != NULL)
  270. ata_raid_check_component(chp->ata_drives[i]);
  271. #endif /* NATARAID > 0 */
  272. /*
  273. * reset drive_flags for unattached devices, reset state for attached
  274. * ones
  275. */
  276. s = splbio();
  277. for (i = 0; i < chp->ch_ndrive; i++) {
  278. if (chp->ch_drive[i].drv_softc == NULL)
  279. chp->ch_drive[i].drive_flags = 0;
  280. else
  281. chp->ch_drive[i].state = 0;
  282. }
  283. splx(s);
  284. simple_lock(&atabus_interlock);
  285. TAILQ_REMOVE(&atabus_initq_head, atabus_initq, atabus_initq);
  286. simple_unlock(&atabus_interlock);
  287. free(atabus_initq, M_DEVBUF);
  288. wakeup(&atabus_initq_head);
  289. ata_delref(chp);
  290. config_pending_decr();
  291. kthread_exit(0);
  292. }
  293. /*
  294. * atabus_thread:
  295. *
  296. * Worker thread for the ATA bus.
  297. */
  298. static void
  299. atabus_thread(void *arg)
  300. {
  301. struct atabus_softc *sc = arg;
  302. struct ata_channel *chp = sc->sc_chan;
  303. struct ata_xfer *xfer;
  304. int i, s;
  305. s = splbio();
  306. chp->ch_flags |= ATACH_TH_RUN;
  307. /*
  308. * Probe the drives. Reset all flags to 0 to indicate to controllers
  309. * that can re-probe that all drives must be probed..
  310. *
  311. * Note: ch_ndrive may be changed during the probe.
  312. */
  313. for (i = 0; i < ATA_MAXDRIVES; i++)
  314. chp->ch_drive[i].drive_flags = 0;
  315. splx(s);
  316. atabusconfig(sc);
  317. s = splbio();
  318. for (;;) {
  319. if ((chp->ch_flags & (ATACH_TH_RESET | ATACH_SHUTDOWN)) == 0 &&
  320. (chp->ch_queue->active_xfer == NULL ||
  321. chp->ch_queue->queue_freeze == 0)) {
  322. chp->ch_flags &= ~ATACH_TH_RUN;
  323. //(void) tsleep(&chp->ch_thread, PRIBIO, "atath", 0);
  324. chp->ch_flags |= ATACH_TH_RUN;
  325. }
  326. if (chp->ch_flags & ATACH_SHUTDOWN) {
  327. break;
  328. }
  329. if (chp->ch_flags & ATACH_TH_RESET) {
  330. /*
  331. * ata_reset_channel() will freeze 2 times, so
  332. * unfreeze one time. Not a problem as we're at splbio
  333. */
  334. chp->ch_queue->queue_freeze--;
  335. ata_reset_channel(chp, AT_WAIT | chp->ch_reset_flags);
  336. } else if (chp->ch_queue->active_xfer != NULL &&
  337. chp->ch_queue->queue_freeze == 1) {
  338. /*
  339. * Caller has bumped queue_freeze, decrease it.
  340. */
  341. chp->ch_queue->queue_freeze--;
  342. xfer = chp->ch_queue->active_xfer;
  343. KASSERT(xfer != NULL);
  344. (*xfer->c_start)(xfer->c_chp, xfer);
  345. } else if (chp->ch_queue->queue_freeze > 1)
  346. return;//panic("ata_thread: queue_freeze");
  347. }
  348. splx(s);
  349. chp->ch_thread = NULL;
  350. wakeup(&chp->ch_flags);
  351. kthread_exit(0);
  352. }
  353. /*
  354. * atabus_match:
  355. *
  356. * Autoconfiguration match routine.
  357. */
  358. static int
  359. atabus_match(device_t parent, cfdata_t cf, void *aux)
  360. {
  361. struct ata_channel *chp = aux;
  362. if (chp == NULL)
  363. return (0);
  364. if (cf->cf_loc[ATACF_CHANNEL] != chp->ch_channel &&
  365. cf->cf_loc[ATACF_CHANNEL] != ATACF_CHANNEL_DEFAULT)
  366. return (0);
  367. return (1);
  368. }
  369. static int
  370. atabus_xferpool_init(void)
  371. {
  372. pool_init(&ata_xfer_pool, sizeof(struct ata_xfer), 0, 0, 0, "ataspl",
  373. NULL, IPL_BIO);
  374. return 0;
  375. }
  376. /*
  377. * atabus_attach:
  378. *
  379. * Autoconfiguration attach routine.
  380. */
  381. static void
  382. atabus_attach(device_t parent, device_t self, void *aux)
  383. {
  384. struct atabus_softc *sc = device_private(self);
  385. struct ata_channel *chp = aux;
  386. struct atabus_initq *initq;
  387. static ONCE_DECL(poolinit_ctrl);
  388. int error;
  389. sc->sc_chan = chp;
  390. aprint_normal("\n");
  391. aprint_naive("\n");
  392. sc->sc_dev = self;
  393. if (ata_addref(chp))
  394. return;
  395. RUN_ONCE(&poolinit_ctrl, atabus_xferpool_init);
  396. initq = malloc(sizeof(*initq), M_DEVBUF, M_WAITOK);
  397. initq->atabus_sc = sc;
  398. TAILQ_INSERT_TAIL(&atabus_initq_head, initq, atabus_initq);
  399. config_pending_incr();
  400. if ((error = kthread_create(PRI_NONE, 0, NULL, atabus_thread, sc,
  401. &chp->ch_thread, "%s", device_xname(self))) != 0)
  402. aprint_error_dev(self,
  403. "unable to create kernel thread: error %d\n", error);
  404. if (!pmf_device_register(self, atabus_suspend, atabus_resume))
  405. aprint_error_dev(self, "couldn't establish power handler\n");
  406. }
  407. /*
  408. * atabus_detach:
  409. *
  410. * Autoconfiguration detach routine.
  411. */
  412. static int
  413. atabus_detach(device_t self, int flags)
  414. {
  415. struct atabus_softc *sc = device_private(self);
  416. struct ata_channel *chp = sc->sc_chan;
  417. device_t dev = NULL;
  418. int s, i, error = 0;
  419. /* Shutdown the channel. */
  420. s = splbio(); /* XXX ALSO NEED AN INTERLOCK HERE. */
  421. chp->ch_flags |= ATACH_SHUTDOWN;
  422. splx(s);
  423. wakeup(&chp->ch_thread);
  424. while (chp->ch_thread != NULL)
  425. //(void) tsleep(&chp->ch_flags, PRIBIO, "atadown", 0);
  426. /*
  427. * Detach atapibus and its children.
  428. */
  429. if ((dev = chp->atapibus) != NULL) {
  430. ATADEBUG_PRINT(("atabus_detach: %s: detaching %s\n",
  431. device_xname(self), device_xname(dev)), DEBUG_DETACH);
  432. error = config_detach(dev, flags);
  433. if (error)
  434. goto out;
  435. KASSERT(chp->atapibus == NULL);
  436. }
  437. /*
  438. * Detach our other children.
  439. */
  440. for (i = 0; i < chp->ch_ndrive; i++) {
  441. if (chp->ch_drive[i].drive_flags & DRIVE_ATAPI)
  442. continue;
  443. if ((dev = chp->ata_drives[i]) != NULL) {
  444. ATADEBUG_PRINT(("%s.%d: %s: detaching %s\n", __func__,
  445. __LINE__, device_xname(self), device_xname(dev)),
  446. DEBUG_DETACH);
  447. KASSERT(chp->ch_drive[i].drv_softc ==
  448. chp->ata_drives[i]);
  449. error = config_detach(dev, flags);
  450. if (error)
  451. goto out;
  452. KASSERT(chp->ata_drives[i] == NULL);
  453. }
  454. }
  455. out:
  456. #ifdef ATADEBUG
  457. if (dev != NULL && error != 0)
  458. ATADEBUG_PRINT(("%s: %s: error %d detaching %s\n", __func__,
  459. device_xname(self), error, device_xname(dev)),
  460. DEBUG_DETACH);
  461. #endif /* ATADEBUG */
  462. return (error);
  463. }
  464. void
  465. atabus_childdetached(device_t self, device_t child)
  466. {
  467. bool found = false;
  468. struct atabus_softc *sc = device_private(self);
  469. struct ata_channel *chp = sc->sc_chan;
  470. int i;
  471. /*
  472. * atapibus detached.
  473. */
  474. if (child == chp->atapibus) {
  475. chp->atapibus = NULL;
  476. found = true;
  477. }
  478. /*
  479. * Detach our other children.
  480. */
  481. for (i = 0; i < chp->ch_ndrive; i++) {
  482. if (chp->ch_drive[i].drive_flags & DRIVE_ATAPI)
  483. continue;
  484. if (child == chp->ata_drives[i]) {
  485. KASSERT(chp->ata_drives[i] ==
  486. chp->ch_drive[i].drv_softc);
  487. chp->ata_drives[i] = NULL;
  488. chp->ch_drive[i].drv_softc = NULL;
  489. chp->ch_drive[i].drive_flags = 0;
  490. found = true;
  491. }
  492. }
  493. if (!found)
  494. return;
  495. /*panic("%s: unknown child %p", device_xname(self),
  496. (const void *)child);*/
  497. }
  498. /*CFATTACH_DECL3_NEW(ata_bus, sizeof(struct atabus_softc),
  499. atabus_match, atabus_attach, atabus_detach, NULL, NULL,
  500. atabus_childdetached, DVF_DETACH_SHUTDOWN);*/
  501. /*****************************************************************************
  502. * Common ATA bus operations.
  503. *****************************************************************************/
  504. /* Get the disk's parameters */
  505. int
  506. ata_get_params(struct ata_drive_datas *drvp, u_int8_t flags,
  507. struct ataparams *prms)
  508. {
  509. struct ata_command ata_c;
  510. struct ata_channel *chp = drvp->chnl_softc;
  511. struct atac_softc *atac = chp->ch_atac;
  512. char *tb;
  513. int i, rv;
  514. u_int16_t *p;
  515. ATADEBUG_PRINT(("%s\n", __func__), DEBUG_FUNCS);
  516. tb = kmem_zalloc(DEV_BSIZE, KM_SLEEP);
  517. memset(prms, 0, sizeof(struct ataparams));
  518. memset(&ata_c, 0, sizeof(struct ata_command));
  519. if (drvp->drive_flags & DRIVE_ATA) {
  520. ata_c.r_command = WDCC_IDENTIFY;
  521. ata_c.r_st_bmask = WDCS_DRDY;
  522. ata_c.r_st_pmask = WDCS_DRQ;
  523. ata_c.timeout = 3000; /* 3s */
  524. } else if (drvp->drive_flags & DRIVE_ATAPI) {
  525. ata_c.r_command = ATAPI_IDENTIFY_DEVICE;
  526. ata_c.r_st_bmask = 0;
  527. ata_c.r_st_pmask = WDCS_DRQ;
  528. ata_c.timeout = 10000; /* 10s */
  529. } else {
  530. ATADEBUG_PRINT(("ata_get_parms: no disks\n"),
  531. DEBUG_FUNCS|DEBUG_PROBE);
  532. rv = CMD_ERR;
  533. goto out;
  534. }
  535. ata_c.flags = AT_READ | flags;
  536. ata_c.data = tb;
  537. ata_c.bcount = DEV_BSIZE;
  538. if ((*atac->atac_bustype_ata->ata_exec_command)(drvp,
  539. &ata_c) != ATACMD_COMPLETE) {
  540. ATADEBUG_PRINT(("ata_get_parms: wdc_exec_command failed\n"),
  541. DEBUG_FUNCS|DEBUG_PROBE);
  542. rv = CMD_AGAIN;
  543. goto out;
  544. }
  545. if (ata_c.flags & (AT_ERROR | AT_TIMEOU | AT_DF)) {
  546. ATADEBUG_PRINT(("ata_get_parms: ata_c.flags=0x%x\n",
  547. ata_c.flags), DEBUG_FUNCS|DEBUG_PROBE);
  548. rv = CMD_ERR;
  549. goto out;
  550. }
  551. /* if we didn't read any data something is wrong */
  552. if ((ata_c.flags & AT_XFDONE) == 0) {
  553. rv = CMD_ERR;
  554. goto out;
  555. }
  556. /* Read in parameter block. */
  557. memcpy(prms, tb, sizeof(struct ataparams));
  558. /*
  559. * Shuffle string byte order.
  560. * ATAPI NEC, Mitsumi and Pioneer drives and
  561. * old ATA TDK CompactFlash cards
  562. * have different byte order.
  563. */
  564. #if BYTE_ORDER == BIG_ENDIAN
  565. # define M(n) prms->atap_model[(n) ^ 1]
  566. #else
  567. # define M(n) prms->atap_model[n]
  568. #endif
  569. if (
  570. #if BYTE_ORDER == BIG_ENDIAN
  571. !
  572. #endif
  573. ((drvp->drive_flags & DRIVE_ATAPI) ?
  574. ((M(0) == 'N' && M(1) == 'E') ||
  575. (M(0) == 'F' && M(1) == 'X') ||
  576. (M(0) == 'P' && M(1) == 'i')) :
  577. ((M(0) == 'T' && M(1) == 'D' && M(2) == 'K')))) {
  578. rv = CMD_OK;
  579. goto out;
  580. }
  581. #undef M
  582. for (i = 0; i < sizeof(prms->atap_model); i += 2) {
  583. p = (u_int16_t *)(prms->atap_model + i);
  584. *p = bswap16(*p);
  585. }
  586. for (i = 0; i < sizeof(prms->atap_serial); i += 2) {
  587. p = (u_int16_t *)(prms->atap_serial + i);
  588. *p = bswap16(*p);
  589. }
  590. for (i = 0; i < sizeof(prms->atap_revision); i += 2) {
  591. p = (u_int16_t *)(prms->atap_revision + i);
  592. *p = bswap16(*p);
  593. }
  594. rv = CMD_OK;
  595. out:
  596. kmem_free(tb, DEV_BSIZE);
  597. return rv;
  598. }
  599. int
  600. ata_set_mode(struct ata_drive_datas *drvp, u_int8_t mode, u_int8_t flags)
  601. {
  602. struct ata_command ata_c;
  603. struct ata_channel *chp = drvp->chnl_softc;
  604. struct atac_softc *atac = chp->ch_atac;
  605. ATADEBUG_PRINT(("ata_set_mode=0x%x\n", mode), DEBUG_FUNCS);
  606. memset(&ata_c, 0, sizeof(struct ata_command));
  607. ata_c.r_command = SET_FEATURES;
  608. ata_c.r_st_bmask = 0;
  609. ata_c.r_st_pmask = 0;
  610. ata_c.r_features = WDSF_SET_MODE;
  611. ata_c.r_count = mode;
  612. ata_c.flags = flags;
  613. ata_c.timeout = 1000; /* 1s */
  614. if ((*atac->atac_bustype_ata->ata_exec_command)(drvp,
  615. &ata_c) != ATACMD_COMPLETE)
  616. return CMD_AGAIN;
  617. if (ata_c.flags & (AT_ERROR | AT_TIMEOU | AT_DF)) {
  618. return CMD_ERR;
  619. }
  620. return CMD_OK;
  621. }
  622. #if NATA_DMA
  623. void
  624. ata_dmaerr(struct ata_drive_datas *drvp, int flags)
  625. {
  626. /*
  627. * Downgrade decision: if we get NERRS_MAX in NXFER.
  628. * We start with n_dmaerrs set to NERRS_MAX-1 so that the
  629. * first error within the first NXFER ops will immediatly trigger
  630. * a downgrade.
  631. * If we got an error and n_xfers is bigger than NXFER reset counters.
  632. */
  633. drvp->n_dmaerrs++;
  634. if (drvp->n_dmaerrs >= NERRS_MAX && drvp->n_xfers <= NXFER) {
  635. ata_downgrade_mode(drvp, flags);
  636. drvp->n_dmaerrs = NERRS_MAX-1;
  637. drvp->n_xfers = 0;
  638. return;
  639. }
  640. if (drvp->n_xfers > NXFER) {
  641. drvp->n_dmaerrs = 1; /* just got an error */
  642. drvp->n_xfers = 1; /* restart counting from this error */
  643. }
  644. }
  645. #endif /* NATA_DMA */
  646. /*
  647. * freeze the queue and wait for the controller to be idle. Caller has to
  648. * unfreeze/restart the queue
  649. */
  650. void
  651. ata_queue_idle(struct ata_queue *queue)
  652. {
  653. int s = splbio();
  654. queue->queue_freeze++;
  655. while (queue->active_xfer != NULL) {
  656. queue->queue_flags |= QF_IDLE_WAIT;
  657. tsleep(&queue->queue_flags, PRIBIO, "qidl", 0);
  658. }
  659. splx(s);
  660. }
  661. /*
  662. * Add a command to the queue and start controller.
  663. *
  664. * MUST BE CALLED AT splbio()!
  665. */
  666. void
  667. ata_exec_xfer(struct ata_channel *chp, struct ata_xfer *xfer)
  668. {
  669. ATADEBUG_PRINT(("ata_exec_xfer %p channel %d drive %d\n", xfer,
  670. chp->ch_channel, xfer->c_drive), DEBUG_XFERS);
  671. /* complete xfer setup */
  672. xfer->c_chp = chp;
  673. /* insert at the end of command list */
  674. TAILQ_INSERT_TAIL(&chp->ch_queue->queue_xfer, xfer, c_xferchain);
  675. ATADEBUG_PRINT(("atastart from ata_exec_xfer, flags 0x%x\n",
  676. chp->ch_flags), DEBUG_XFERS);
  677. /*
  678. * if polling and can sleep, wait for the xfer to be at head of queue
  679. */
  680. if ((xfer->c_flags & (C_POLL | C_WAIT)) == (C_POLL | C_WAIT)) {
  681. while (chp->ch_queue->active_xfer != NULL ||
  682. TAILQ_FIRST(&chp->ch_queue->queue_xfer) != xfer) {
  683. xfer->c_flags |= C_WAITACT;
  684. tsleep(xfer, PRIBIO, "ataact", 0);
  685. xfer->c_flags &= ~C_WAITACT;
  686. if (xfer->c_flags & C_FREE) {
  687. ata_free_xfer(chp, xfer);
  688. return;
  689. }
  690. }
  691. }
  692. atastart(chp);
  693. }
  694. /*
  695. * Start I/O on a controller, for the given channel.
  696. * The first xfer may be not for our channel if the channel queues
  697. * are shared.
  698. *
  699. * MUST BE CALLED AT splbio()!
  700. */
  701. void
  702. atastart(struct ata_channel *chp)
  703. {
  704. struct atac_softc *atac = chp->ch_atac;
  705. struct ata_xfer *xfer;
  706. #ifdef ATA_DEBUG
  707. int spl1, spl2;
  708. spl1 = splbio();
  709. spl2 = splbio();
  710. if (spl2 != spl1) {
  711. printf("atastart: not at splbio()\n");
  712. //panic("atastart");
  713. }
  714. splx(spl2);
  715. splx(spl1);
  716. #endif /* ATA_DEBUG */
  717. /* is there a xfer ? */
  718. if ((xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer)) == NULL)
  719. return;
  720. /* adjust chp, in case we have a shared queue */
  721. chp = xfer->c_chp;
  722. if (chp->ch_queue->active_xfer != NULL) {
  723. return; /* channel aleady active */
  724. }
  725. if (__predict_false(chp->ch_queue->queue_freeze > 0)) {
  726. if (chp->ch_queue->queue_flags & QF_IDLE_WAIT) {
  727. chp->ch_queue->queue_flags &= ~QF_IDLE_WAIT;
  728. wakeup(&chp->ch_queue->queue_flags);
  729. }
  730. return; /* queue frozen */
  731. }
  732. /*
  733. * if someone is waiting for the command to be active, wake it up
  734. * and let it process the command
  735. */
  736. if (xfer->c_flags & C_WAITACT) {
  737. ATADEBUG_PRINT(("atastart: xfer %p channel %d drive %d "
  738. "wait active\n", xfer, chp->ch_channel, xfer->c_drive),
  739. DEBUG_XFERS);
  740. wakeup(xfer);
  741. return;
  742. }
  743. #ifdef DIAGNOSTIC
  744. if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0)
  745. //panic("atastart: channel waiting for irq");
  746. #endif
  747. if (atac->atac_claim_hw)
  748. if (!(*atac->atac_claim_hw)(chp, 0))
  749. return;
  750. ATADEBUG_PRINT(("atastart: xfer %p channel %d drive %d\n", xfer,
  751. chp->ch_channel, xfer->c_drive), DEBUG_XFERS);
  752. if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_RESET) {
  753. chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_RESET;
  754. chp->ch_drive[xfer->c_drive].state = 0;
  755. }
  756. chp->ch_queue->active_xfer = xfer;
  757. TAILQ_REMOVE(&chp->ch_queue->queue_xfer, xfer, c_xferchain);
  758. if (atac->atac_cap & ATAC_CAP_NOIRQ)
  759. KASSERT(xfer->c_flags & C_POLL);
  760. xfer->c_start(chp, xfer);
  761. }
  762. struct ata_xfer *
  763. ata_get_xfer(int flags)
  764. {
  765. struct ata_xfer *xfer;
  766. int s;
  767. s = splbio();
  768. xfer = pool_get(&ata_xfer_pool,
  769. ((flags & ATAXF_NOSLEEP) != 0 ? PR_NOWAIT : PR_WAITOK));
  770. splx(s);
  771. if (xfer != NULL) {
  772. memset(xfer, 0, sizeof(struct ata_xfer));
  773. }
  774. return xfer;
  775. }
  776. void
  777. ata_free_xfer(struct ata_channel *chp, struct ata_xfer *xfer)
  778. {
  779. struct atac_softc *atac = chp->ch_atac;
  780. int s;
  781. if (xfer->c_flags & C_WAITACT) {
  782. /* Someone is waiting for this xfer, so we can't free now */
  783. xfer->c_flags |= C_FREE;
  784. wakeup(xfer);
  785. return;
  786. }
  787. #if NATA_PIOBM /* XXX wdc dependent code */
  788. if (xfer->c_flags & C_PIOBM) {
  789. struct wdc_softc *wdc = CHAN_TO_WDC(chp);
  790. /* finish the busmastering PIO */
  791. (*wdc->piobm_done)(wdc->dma_arg,
  792. chp->ch_channel, xfer->c_drive);
  793. chp->ch_flags &= ~(ATACH_DMA_WAIT | ATACH_PIOBM_WAIT | ATACH_IRQ_WAIT);
  794. }
  795. #endif
  796. if (atac->atac_free_hw)
  797. (*atac->atac_free_hw)(chp);
  798. s = splbio();
  799. pool_put(&ata_xfer_pool, xfer);
  800. splx(s);
  801. }
  802. /*
  803. * Kill off all pending xfers for a ata_channel.
  804. *
  805. * Must be called at splbio().
  806. */
  807. void
  808. ata_kill_pending(struct ata_drive_datas *drvp)
  809. {
  810. struct ata_channel *chp = drvp->chnl_softc;
  811. struct ata_xfer *xfer, *next_xfer;
  812. int s = splbio();
  813. for (xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer);
  814. xfer != NULL; xfer = next_xfer) {
  815. next_xfer = TAILQ_NEXT(xfer, c_xferchain);
  816. if (xfer->c_chp != chp || xfer->c_drive != drvp->drive)
  817. continue;
  818. TAILQ_REMOVE(&chp->ch_queue->queue_xfer, xfer, c_xferchain);
  819. (*xfer->c_kill_xfer)(chp, xfer, KILL_GONE);
  820. }
  821. while ((xfer = chp->ch_queue->active_xfer) != NULL) {
  822. if (xfer->c_chp == chp && xfer->c_drive == drvp->drive) {
  823. drvp->drive_flags |= DRIVE_WAITDRAIN;
  824. //(void) tsleep(&chp->ch_queue->active_xfer,PRIBIO, "atdrn", 0);
  825. } else {
  826. /* no more xfer for us */
  827. break;
  828. }
  829. }
  830. splx(s);
  831. }
  832. /*
  833. * ata_reset_channel:
  834. *
  835. * Reset and ATA channel.
  836. *
  837. * MUST BE CALLED AT splbio()!
  838. */
  839. void
  840. ata_reset_channel(struct ata_channel *chp, int flags)
  841. {
  842. struct atac_softc *atac = chp->ch_atac;
  843. int drive;
  844. #ifdef ATA_DEBUG
  845. int spl1, spl2;
  846. spl1 = splbio();
  847. spl2 = splbio();
  848. if (spl2 != spl1) {
  849. printf("ata_reset_channel: not at splbio()\n");
  850. //panic("ata_reset_channel");
  851. }
  852. splx(spl2);
  853. splx(spl1);
  854. #endif /* ATA_DEBUG */
  855. chp->ch_queue->queue_freeze++;
  856. /*
  857. * If we can poll or wait it's OK, otherwise wake up the
  858. * kernel thread to do it for us.
  859. */
  860. ATADEBUG_PRINT(("ata_reset_channel flags 0x%x ch_flags 0x%x\n",
  861. flags, chp->ch_flags), DEBUG_FUNCS | DEBUG_XFERS);
  862. if ((flags & (AT_POLL | AT_WAIT)) == 0) {
  863. if (chp->ch_flags & ATACH_TH_RESET) {
  864. /* No need to schedule a reset more than one time. */
  865. chp->ch_queue->queue_freeze--;
  866. return;
  867. }
  868. chp->ch_flags |= ATACH_TH_RESET;
  869. chp->ch_reset_flags = flags & (AT_RST_EMERG | AT_RST_NOCMD);
  870. wakeup(&chp->ch_thread);
  871. return;
  872. }
  873. (*atac->atac_bustype_ata->ata_reset_channel)(chp, flags);
  874. for (drive = 0; drive < chp->ch_ndrive; drive++)
  875. chp->ch_drive[drive].state = 0;
  876. chp->ch_flags &= ~ATACH_TH_RESET;
  877. if ((flags & AT_RST_EMERG) == 0) {
  878. chp->ch_queue->queue_freeze--;
  879. atastart(chp);
  880. } else {
  881. /* make sure that we can use polled commands */
  882. TAILQ_INIT(&chp->ch_queue->queue_xfer);
  883. chp->ch_queue->queue_freeze = 0;
  884. chp->ch_queue->active_xfer = NULL;
  885. }
  886. }
  887. int
  888. ata_addref(struct ata_channel *chp)
  889. {
  890. struct atac_softc *atac = chp->ch_atac;
  891. struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic;
  892. int s, error = 0;
  893. s = splbio();
  894. if (adapt->adapt_refcnt++ == 0 &&
  895. adapt->adapt_enable != NULL) {
  896. error = (*adapt->adapt_enable)(atac->atac_dev, 1);
  897. if (error)
  898. adapt->adapt_refcnt--;
  899. }
  900. splx(s);
  901. return (error);
  902. }
  903. void
  904. ata_delref(struct ata_channel *chp)
  905. {
  906. struct atac_softc *atac = chp->ch_atac;
  907. struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic;
  908. int s;
  909. s = splbio();
  910. if (adapt->adapt_refcnt-- == 1 &&
  911. adapt->adapt_enable != NULL)
  912. (void) (*adapt->adapt_enable)(atac->atac_dev, 0);
  913. splx(s);
  914. }
  915. void
  916. ata_print_modes(struct ata_channel *chp)
  917. {
  918. struct atac_softc *atac = chp->ch_atac;
  919. int drive;
  920. struct ata_drive_datas *drvp;
  921. for (drive = 0; drive < chp->ch_ndrive; drive++) {
  922. drvp = &chp->ch_drive[drive];
  923. if ((drvp->drive_flags & DRIVE) == 0 || drvp->drv_softc == NULL)
  924. continue;
  925. aprint_verbose("%s(%s:%d:%d): using PIO mode %d",
  926. device_xname(drvp->drv_softc),
  927. device_xname(atac->atac_dev),
  928. chp->ch_channel, drvp->drive, drvp->PIO_mode);
  929. #if NATA_DMA
  930. if (drvp->drive_flags & DRIVE_DMA)
  931. aprint_verbose(", DMA mode %d", drvp->DMA_mode);
  932. #if NATA_UDMA
  933. if (drvp->drive_flags & DRIVE_UDMA) {
  934. aprint_verbose(", Ultra-DMA mode %d", drvp->UDMA_mode);
  935. if (drvp->UDMA_mode == 2)
  936. aprint_verbose(" (Ultra/33)");
  937. else if (drvp->UDMA_mode == 4)
  938. aprint_verbose(" (Ultra/66)");
  939. else if (drvp->UDMA_mode == 5)
  940. aprint_verbose(" (Ultra/100)");
  941. else if (drvp->UDMA_mode == 6)
  942. aprint_verbose(" (Ultra/133)");
  943. }
  944. #endif /* NATA_UDMA */
  945. #endif /* NATA_DMA */
  946. #if NATA_DMA || NATA_PIOBM
  947. if (0
  948. #if NATA_DMA
  949. || (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA))
  950. #endif
  951. #if NATA_PIOBM
  952. /* PIOBM capable controllers use DMA for PIO commands */
  953. || (atac->atac_cap & ATAC_CAP_PIOBM)
  954. #endif
  955. )
  956. aprint_verbose(" (using DMA)");
  957. #endif /* NATA_DMA || NATA_PIOBM */
  958. aprint_verbose("\n");
  959. }
  960. }
  961. #if NATA_DMA
  962. /*
  963. * downgrade the transfer mode of a drive after an error. return 1 if
  964. * downgrade was possible, 0 otherwise.
  965. *
  966. * MUST BE CALLED AT splbio()!
  967. */
  968. int
  969. ata_downgrade_mode(struct ata_drive_datas *drvp, int flags)
  970. {
  971. struct ata_channel *chp = drvp->chnl_softc;
  972. struct atac_softc *atac = chp->ch_atac;
  973. device_t drv_dev = drvp->drv_softc;
  974. int cf_flags = device_cfdata(drv_dev)->cf_flags;
  975. /* if drive or controller don't know its mode, we can't do much */
  976. if ((drvp->drive_flags & DRIVE_MODE) == 0 ||
  977. (atac->atac_set_modes == NULL))
  978. return 0;
  979. /* current drive mode was set by a config flag, let it this way */
  980. if ((cf_flags & ATA_CONFIG_PIO_SET) ||
  981. (cf_flags & ATA_CONFIG_DMA_SET) ||
  982. (cf_flags & ATA_CONFIG_UDMA_SET))
  983. return 0;
  984. #if NATA_UDMA
  985. /*
  986. * If we were using Ultra-DMA mode, downgrade to the next lower mode.
  987. */
  988. if ((drvp->drive_flags & DRIVE_UDMA) && drvp->UDMA_mode >= 2) {
  989. drvp->UDMA_mode--;
  990. aprint_error_dev(drv_dev,
  991. "transfer error, downgrading to Ultra-DMA mode %d\n",
  992. drvp->UDMA_mode);
  993. }
  994. #endif
  995. /*
  996. * If we were using ultra-DMA, don't downgrade to multiword DMA.
  997. */
  998. else if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) {
  999. drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA);
  1000. drvp->PIO_mode = drvp->PIO_cap;
  1001. aprint_error_dev(drv_dev,
  1002. "transfer error, downgrading to PIO mode %d\n",
  1003. drvp->PIO_mode);
  1004. } else /* already using PIO, can't downgrade */
  1005. return 0;
  1006. (*atac->atac_set_modes)(chp);
  1007. ata_print_modes(chp);
  1008. /* reset the channel, which will schedule all drives for setup */
  1009. ata_reset_channel(chp, flags | AT_RST_NOCMD);
  1010. return 1;
  1011. }
  1012. #endif /* NATA_DMA */
  1013. /*
  1014. * Probe drive's capabilities, for use by the controller later
  1015. * Assumes drvp points to an existing drive.
  1016. */
  1017. void
  1018. ata_probe_caps(struct ata_drive_datas *drvp)
  1019. {
  1020. struct ataparams params, params2;
  1021. struct ata_channel *chp = drvp->chnl_softc;
  1022. struct atac_softc *atac = chp->ch_atac;
  1023. device_t drv_dev = drvp->drv_softc;
  1024. int i, printed, s;
  1025. const char *sep = "";
  1026. int cf_flags;
  1027. if (ata_get_params(drvp, AT_WAIT, &params) != CMD_OK) {
  1028. /* IDENTIFY failed. Can't tell more about the device */
  1029. return;
  1030. }
  1031. if ((atac->atac_cap & (ATAC_CAP_DATA16 | ATAC_CAP_DATA32)) ==
  1032. (ATAC_CAP_DATA16 | ATAC_CAP_DATA32)) {
  1033. /*
  1034. * Controller claims 16 and 32 bit transfers.
  1035. * Re-do an IDENTIFY with 32-bit transfers,
  1036. * and compare results.
  1037. */
  1038. s = splbio();
  1039. drvp->drive_flags |= DRIVE_CAP32;
  1040. splx(s);
  1041. ata_get_params(drvp, AT_WAIT, &params2);
  1042. if (memcmp(&params, &params2, sizeof(struct ataparams)) != 0) {
  1043. /* Not good. fall back to 16bits */
  1044. s = splbio();
  1045. drvp->drive_flags &= ~DRIVE_CAP32;
  1046. splx(s);
  1047. } else {
  1048. aprint_verbose_dev(drv_dev, "32-bit data port\n");
  1049. }
  1050. }
  1051. #if 0 /* Some ultra-DMA drives claims to only support ATA-3. sigh */
  1052. if (params.atap_ata_major > 0x01 &&
  1053. params.atap_ata_major != 0xffff) {
  1054. for (i = 14; i > 0; i--) {
  1055. if (params.atap_ata_major & (1 << i)) {
  1056. aprint_verbose_dev(drv_dev,
  1057. "ATA version %d\n", i);
  1058. drvp->ata_vers = i;
  1059. break;
  1060. }
  1061. }
  1062. }
  1063. #endif
  1064. /* An ATAPI device is at last PIO mode 3 */
  1065. if (drvp->drive_flags & DRIVE_ATAPI)
  1066. drvp->PIO_mode = 3;
  1067. /*
  1068. * It's not in the specs, but it seems that some drive
  1069. * returns 0xffff in atap_extensions when this field is invalid
  1070. */
  1071. if (params.atap_extensions != 0xffff &&
  1072. (params.atap_extensions & WDC_EXT_MODES)) {
  1073. printed = 0;
  1074. /*
  1075. * XXX some drives report something wrong here (they claim to
  1076. * support PIO mode 8 !). As mode is coded on 3 bits in
  1077. * SET FEATURE, limit it to 7 (so limit i to 4).
  1078. * If higher mode than 7 is found, abort.
  1079. */
  1080. for (i = 7; i >= 0; i--) {
  1081. if ((params.atap_piomode_supp & (1 << i)) == 0)
  1082. continue;
  1083. if (i > 4)
  1084. return;
  1085. /*
  1086. * See if mode is accepted.
  1087. * If the controller can't set its PIO mode,
  1088. * assume the defaults are good, so don't try
  1089. * to set it
  1090. */
  1091. if (atac->atac_set_modes)
  1092. /*
  1093. * It's OK to pool here, it's fast enough
  1094. * to not bother waiting for interrupt
  1095. */
  1096. if (ata_set_mode(drvp, 0x08 | (i + 3),
  1097. AT_WAIT) != CMD_OK)
  1098. continue;
  1099. if (!printed) {
  1100. aprint_verbose_dev(drv_dev,
  1101. "drive supports PIO mode %d", i + 3);
  1102. sep = ",";
  1103. printed = 1;
  1104. }
  1105. /*
  1106. * If controller's driver can't set its PIO mode,
  1107. * get the highter one for the drive.
  1108. */
  1109. if (atac->atac_set_modes == NULL ||
  1110. atac->atac_pio_cap >= i + 3) {
  1111. drvp->PIO_mode = i + 3;
  1112. drvp->PIO_cap = i + 3;
  1113. break;
  1114. }
  1115. }
  1116. if (!printed) {
  1117. /*
  1118. * We didn't find a valid PIO mode.
  1119. * Assume the values returned for DMA are buggy too
  1120. */
  1121. return;
  1122. }
  1123. s = splbio();
  1124. drvp->drive_flags |= DRIVE_MODE;
  1125. splx(s);
  1126. printed = 0;
  1127. for (i = 7; i >= 0; i--) {
  1128. if ((params.atap_dmamode_supp & (1 << i)) == 0)
  1129. continue;
  1130. #if NATA_DMA
  1131. if ((atac->atac_cap & ATAC_CAP_DMA) &&
  1132. atac->atac_set_modes != NULL)
  1133. if (ata_set_mode(drvp, 0x20 | i, AT_WAIT)
  1134. != CMD_OK)
  1135. continue;
  1136. #endif
  1137. if (!printed) {
  1138. aprint_verbose("%s DMA mode %d", sep, i);
  1139. sep = ",";
  1140. printed = 1;
  1141. }
  1142. #if NATA_DMA
  1143. if (atac->atac_cap & ATAC_CAP_DMA) {
  1144. if (atac->atac_set_modes != NULL &&
  1145. atac->atac_dma_cap < i)
  1146. continue;
  1147. drvp->DMA_mode = i;
  1148. drvp->DMA_cap = i;
  1149. s = splbio();
  1150. drvp->drive_flags |= DRIVE_DMA;
  1151. splx(s);
  1152. }
  1153. #endif
  1154. break;
  1155. }
  1156. if (params.atap_extensions & WDC_EXT_UDMA_MODES) {
  1157. printed = 0;
  1158. for (i = 7; i >= 0; i--) {
  1159. if ((params.atap_udmamode_supp & (1 << i))
  1160. == 0)
  1161. continue;
  1162. #if NATA_UDMA
  1163. if (atac->atac_set_modes != NULL &&
  1164. (atac->atac_cap & ATAC_CAP_UDMA))
  1165. if (ata_set_mode(drvp, 0x40 | i,
  1166. AT_WAIT) != CMD_OK)
  1167. continue;
  1168. #endif
  1169. if (!printed) {
  1170. aprint_verbose("%s Ultra-DMA mode %d",
  1171. sep, i);
  1172. if (i == 2)
  1173. aprint_verbose(" (Ultra/33)");
  1174. else if (i == 4)
  1175. aprint_verbose(" (Ultra/66)");
  1176. else if (i == 5)
  1177. aprint_verbose(" (Ultra/100)");
  1178. else if (i == 6)
  1179. aprint_verbose(" (Ultra/133)");
  1180. sep = ",";
  1181. printed = 1;
  1182. }
  1183. #if NATA_UDMA
  1184. if (atac->atac_cap & ATAC_CAP_UDMA) {
  1185. if (atac->atac_set_modes != NULL &&
  1186. atac->atac_udma_cap < i)
  1187. continue;
  1188. drvp->UDMA_mode = i;
  1189. drvp->UDMA_cap = i;
  1190. s = splbio();
  1191. drvp->drive_flags |= DRIVE_UDMA;
  1192. splx(s);
  1193. }
  1194. #endif
  1195. break;
  1196. }
  1197. }
  1198. aprint_verbose("\n");
  1199. }
  1200. s = splbio();
  1201. drvp->drive_flags &= ~DRIVE_NOSTREAM;
  1202. if (drvp->drive_flags & DRIVE_ATAPI) {
  1203. if (atac->atac_cap & ATAC_CAP_ATAPI_NOSTREAM)
  1204. drvp->drive_flags |= DRIVE_NOSTREAM;
  1205. } else {
  1206. if (atac->atac_cap & ATAC_CAP_ATA_NOSTREAM)
  1207. drvp->drive_flags |= DRIVE_NOSTREAM;
  1208. }
  1209. splx(s);
  1210. /* Try to guess ATA version here, if it didn't get reported */
  1211. if (drvp->ata_vers == 0) {
  1212. #if NATA_UDMA
  1213. if (drvp->drive_flags & DRIVE_UDMA)
  1214. drvp->ata_vers = 4; /* should be at last ATA-4 */
  1215. else
  1216. #endif
  1217. if (drvp->PIO_cap > 2)
  1218. drvp->ata_vers = 2; /* should be at last ATA-2 */
  1219. }
  1220. cf_flags = device_cfdata(drv_dev)->cf_flags;
  1221. if (cf_flags & ATA_CONFIG_PIO_SET) {
  1222. s = splbio();
  1223. drvp->PIO_mode =
  1224. (cf_flags & ATA_CONFIG_PIO_MODES) >> ATA_CONFIG_PIO_OFF;
  1225. drvp->drive_flags |= DRIVE_MODE;
  1226. splx(s);
  1227. }
  1228. #if NATA_DMA
  1229. if ((atac->atac_cap & ATAC_CAP_DMA) == 0) {
  1230. /* don't care about DMA modes */
  1231. return;
  1232. }
  1233. if (cf_flags & ATA_CONFIG_DMA_SET) {
  1234. s = splbio();
  1235. if ((cf_flags & ATA_CONFIG_DMA_MODES) ==
  1236. ATA_CONFIG_DMA_DISABLE) {
  1237. drvp->drive_flags &= ~DRIVE_DMA;
  1238. } else {
  1239. drvp->DMA_mode = (cf_flags & ATA_CONFIG_DMA_MODES) >>
  1240. ATA_CONFIG_DMA_OFF;
  1241. drvp->drive_flags |= DRIVE_DMA | DRIVE_MODE;
  1242. }
  1243. splx(s);
  1244. }
  1245. #if NATA_UDMA
  1246. if ((atac->atac_cap & ATAC_CAP_UDMA) == 0) {
  1247. /* don't care about UDMA modes */
  1248. return;
  1249. }
  1250. if (cf_flags & ATA_CONFIG_UDMA_SET) {
  1251. s = splbio();
  1252. if ((cf_flags & ATA_CONFIG_UDMA_MODES) ==
  1253. ATA_CONFIG_UDMA_DISABLE) {
  1254. drvp->drive_flags &= ~DRIVE_UDMA;
  1255. } else {
  1256. drvp->UDMA_mode = (cf_flags & ATA_CONFIG_UDMA_MODES) >>
  1257. ATA_CONFIG_UDMA_OFF;
  1258. drvp->drive_flags |= DRIVE_UDMA | DRIVE_MODE;
  1259. }
  1260. splx(s);
  1261. }
  1262. #endif /* NATA_UDMA */
  1263. #endif /* NATA_DMA */
  1264. }
  1265. /* management of the /dev/atabus* devices */
  1266. int
  1267. atabusopen(dev_t dev, int flag, int fmt, struct lwp *l)
  1268. {
  1269. struct atabus_softc *sc;
  1270. int error;
  1271. sc = device_lookup_private(&atabus_cd, minor(dev));
  1272. if (sc == NULL)
  1273. return (ENXIO);
  1274. if (sc->sc_flags & ATABUSCF_OPEN)
  1275. return (EBUSY);
  1276. if ((error = ata_addref(sc->sc_chan)) != 0)
  1277. return (error);
  1278. sc->sc_flags |= ATABUSCF_OPEN;
  1279. return (0);
  1280. }
  1281. int
  1282. atabusclose(dev_t dev, int flag, int fmt, struct lwp *l)
  1283. {
  1284. struct atabus_softc *sc =
  1285. device_lookup_private(&atabus_cd, minor(dev));
  1286. ata_delref(sc->sc_chan);
  1287. sc->sc_flags &= ~ATABUSCF_OPEN;
  1288. return (0);
  1289. }
  1290. int
  1291. atabusioctl(dev_t dev, u_long cmd, void *addr, int flag, struct lwp *l)
  1292. {
  1293. struct atabus_softc *sc =
  1294. device_lookup_private(&atabus_cd, minor(dev));
  1295. struct ata_channel *chp = sc->sc_chan;
  1296. int min_drive, max_drive, drive;
  1297. int error;
  1298. int s;
  1299. /*
  1300. * Enforce write permission for ioctls that change the
  1301. * state of the bus. Host adapter specific ioctls must
  1302. * be checked by the adapter driver.
  1303. */
  1304. switch (cmd) {
  1305. case ATABUSIOSCAN:
  1306. case ATABUSIODETACH:
  1307. case ATABUSIORESET:
  1308. if ((flag & FWRITE) == 0)
  1309. return (EBADF);
  1310. }
  1311. switch (cmd) {
  1312. case ATABUSIORESET:
  1313. s = splbio();
  1314. ata_reset_channel(sc->sc_chan, AT_WAIT | AT_POLL);
  1315. splx(s);
  1316. return 0;
  1317. case ATABUSIOSCAN:
  1318. {
  1319. #if 0
  1320. struct atabusioscan_args *a=
  1321. (struct atabusioscan_args *)addr;
  1322. #endif
  1323. if ((chp->ch_drive[0].drive_flags & DRIVE_OLD) ||
  1324. (chp->ch_drive[1].drive_flags & DRIVE_OLD))
  1325. return (EOPNOTSUPP);
  1326. return (EOPNOTSUPP);
  1327. }
  1328. case ATABUSIODETACH:
  1329. {
  1330. struct atabusioscan_args *a=
  1331. (struct atabusioscan_args *)addr;
  1332. if ((chp->ch_drive[0].drive_flags & DRIVE_OLD) ||
  1333. (chp->ch_drive[1].drive_flags & DRIVE_OLD))
  1334. return (EOPNOTSUPP);
  1335. switch (a->at_dev) {
  1336. case -1:
  1337. min_drive = 0;
  1338. max_drive = 1;
  1339. break;
  1340. case 0:
  1341. case 1:
  1342. min_drive = max_drive = a->at_dev;
  1343. break;
  1344. default:
  1345. return (EINVAL);
  1346. }
  1347. for (drive = min_drive; drive <= max_drive; drive++) {
  1348. if (chp->ch_drive[drive].drv_softc != NULL) {
  1349. error = config_detach(
  1350. chp->ch_drive[drive].drv_softc, 0);
  1351. if (error)
  1352. return (error);
  1353. KASSERT(chp->ch_drive[drive].drv_softc == NULL);
  1354. }
  1355. }
  1356. return 0;
  1357. }
  1358. default:
  1359. return ENOTTY;
  1360. }
  1361. }
  1362. static bool
  1363. atabus_suspend(device_t dv, const pmf_qual_t *qual)
  1364. {
  1365. struct atabus_softc *sc = device_private(dv);
  1366. struct ata_channel *chp = sc->sc_chan;
  1367. ata_queue_idle(chp->ch_queue);
  1368. return true;
  1369. }
  1370. static bool
  1371. atabus_resume(device_t dv, const pmf_qual_t *qual)
  1372. {
  1373. struct atabus_softc *sc = device_private(dv);
  1374. struct ata_channel *chp = sc->sc_chan;
  1375. int s;
  1376. /*
  1377. * XXX joerg: with wdc, the first channel unfreezes the controler.
  1378. * Move this the reset and queue idling into wdc.
  1379. */
  1380. s = splbio();
  1381. if (chp->ch_queue->queue_freeze == 0) {
  1382. splx(s);
  1383. return true;
  1384. }
  1385. KASSERT(chp->ch_queue->queue_freeze > 0);
  1386. /* unfreeze the queue and reset drives */
  1387. chp->ch_queue->queue_freeze--;
  1388. ata_reset_channel(chp, AT_WAIT);
  1389. splx(s);
  1390. return true;
  1391. }