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/vhdl/core/leros.vhd

https://code.google.com/p/leros/
VHDL | 62 lines | 41 code | 17 blank | 4 comment | 1 complexity | 306a225f599781c5fd0de764d8c8e022 MD5 | raw file
 1
 2-- top level of the Leros CPU
 3-- That should be instanziated in a FPGA specific top level
 4
 5
 6library ieee;
 7use ieee.std_logic_1164.all;
 8use ieee.numeric_std.all;
 9
10use work.leros_types.all;
11
12entity leros is
13	port  (
14		clk : in std_logic;
15		reset : in std_logic;
16		out_port : out std_logic_vector(15 downto 0)
17	);
18end leros;
19
20architecture rtl of leros is
21
22	signal fdin : fedec_in_type;
23	signal fdout : fedec_out_type;
24	
25	signal exin : ex_in_type;
26	signal exout : ex_out_type;
27
28	signal outreg1, outreg2, outreg3 : std_logic_vector(15 downto 0);
29
30begin
31
32-- relax all I/O pin pathes
33process(clk)
34begin
35
36	-- plain register assignments generate something strange 
37	if rising_edge(clk) then
38		out_port <= outreg3;
39		outreg3 <= not outreg2;
40		outreg2 <= outreg1;
41	end if;
42end process;
43
44	exin.imm <= fdout.imm;
45	exin.dec <= fdout.dec;
46	exin.wren <= fdout.data(10);
47	exin.dm_rdaddr <= fdout.data(7 downto 0); -- this is the smae as imm at the moment
48	exin.dm_wraddr <= fdout.data(15 downto 8);
49	
50	fdin.accu <= exout.accu;
51	fdin.zf <= exout.zf;
52	
53	outreg1 <= exout.outp;
54	
55	fd: entity work.leros_fedec port map (
56		clk, reset, fdin, fdout
57	);
58	ex: entity work.leros_ex port map(
59		clk, reset, exin, exout
60	);
61	
62end rtl;