/3rd_party/llvm/include/llvm/CodeGen/ScheduleDAG.h

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  1. //===------- llvm/CodeGen/ScheduleDAG.h - Common Base Class------*- C++ -*-===//
  2. //
  3. // The LLVM Compiler Infrastructure
  4. //
  5. // This file is distributed under the University of Illinois Open Source
  6. // License. See LICENSE.TXT for details.
  7. //
  8. //===----------------------------------------------------------------------===//
  9. //
  10. // This file implements the ScheduleDAG class, which is used as the common
  11. // base class for instruction schedulers. This encapsulates the scheduling DAG,
  12. // which is shared between SelectionDAG and MachineInstr scheduling.
  13. //
  14. //===----------------------------------------------------------------------===//
  15. #ifndef LLVM_CODEGEN_SCHEDULEDAG_H
  16. #define LLVM_CODEGEN_SCHEDULEDAG_H
  17. #include "llvm/ADT/BitVector.h"
  18. #include "llvm/ADT/GraphTraits.h"
  19. #include "llvm/ADT/PointerIntPair.h"
  20. #include "llvm/ADT/SmallVector.h"
  21. #include "llvm/CodeGen/MachineInstr.h"
  22. #include "llvm/Target/TargetLowering.h"
  23. namespace llvm {
  24. class AliasAnalysis;
  25. class SUnit;
  26. class MachineConstantPool;
  27. class MachineFunction;
  28. class MachineRegisterInfo;
  29. class MachineInstr;
  30. struct MCSchedClassDesc;
  31. class TargetRegisterInfo;
  32. class ScheduleDAG;
  33. class SDNode;
  34. class TargetInstrInfo;
  35. class MCInstrDesc;
  36. class TargetMachine;
  37. class TargetRegisterClass;
  38. template<class Graph> class GraphWriter;
  39. /// SDep - Scheduling dependency. This represents one direction of an
  40. /// edge in the scheduling DAG.
  41. class SDep {
  42. public:
  43. /// Kind - These are the different kinds of scheduling dependencies.
  44. enum Kind {
  45. Data, ///< Regular data dependence (aka true-dependence).
  46. Anti, ///< A register anti-dependedence (aka WAR).
  47. Output, ///< A register output-dependence (aka WAW).
  48. Order ///< Any other ordering dependency.
  49. };
  50. // Strong dependencies must be respected by the scheduler. Artificial
  51. // dependencies may be removed only if they are redundant with another
  52. // strong depedence.
  53. //
  54. // Weak dependencies may be violated by the scheduling strategy, but only if
  55. // the strategy can prove it is correct to do so.
  56. //
  57. // Strong OrderKinds must occur before "Weak".
  58. // Weak OrderKinds must occur after "Weak".
  59. enum OrderKind {
  60. Barrier, ///< An unknown scheduling barrier.
  61. MayAliasMem, ///< Nonvolatile load/Store instructions that may alias.
  62. MustAliasMem, ///< Nonvolatile load/Store instructions that must alias.
  63. Artificial, ///< Arbitrary strong DAG edge (no real dependence).
  64. Weak, ///< Arbitrary weak DAG edge.
  65. Cluster ///< Weak DAG edge linking a chain of clustered instrs.
  66. };
  67. private:
  68. /// Dep - A pointer to the depending/depended-on SUnit, and an enum
  69. /// indicating the kind of the dependency.
  70. PointerIntPair<SUnit *, 2, Kind> Dep;
  71. /// Contents - A union discriminated by the dependence kind.
  72. union {
  73. /// Reg - For Data, Anti, and Output dependencies, the associated
  74. /// register. For Data dependencies that don't currently have a register
  75. /// assigned, this is set to zero.
  76. unsigned Reg;
  77. /// Order - Additional information about Order dependencies.
  78. unsigned OrdKind; // enum OrderKind
  79. } Contents;
  80. /// Latency - The time associated with this edge. Often this is just
  81. /// the value of the Latency field of the predecessor, however advanced
  82. /// models may provide additional information about specific edges.
  83. unsigned Latency;
  84. public:
  85. /// SDep - Construct a null SDep. This is only for use by container
  86. /// classes which require default constructors. SUnits may not
  87. /// have null SDep edges.
  88. SDep() : Dep(0, Data) {}
  89. /// SDep - Construct an SDep with the specified values.
  90. SDep(SUnit *S, Kind kind, unsigned Reg)
  91. : Dep(S, kind), Contents() {
  92. switch (kind) {
  93. default:
  94. llvm_unreachable("Reg given for non-register dependence!");
  95. case Anti:
  96. case Output:
  97. assert(Reg != 0 &&
  98. "SDep::Anti and SDep::Output must use a non-zero Reg!");
  99. Contents.Reg = Reg;
  100. Latency = 0;
  101. break;
  102. case Data:
  103. Contents.Reg = Reg;
  104. Latency = 1;
  105. break;
  106. }
  107. }
  108. SDep(SUnit *S, OrderKind kind)
  109. : Dep(S, Order), Contents(), Latency(0) {
  110. Contents.OrdKind = kind;
  111. }
  112. /// Return true if the specified SDep is equivalent except for latency.
  113. bool overlaps(const SDep &Other) const {
  114. if (Dep != Other.Dep) return false;
  115. switch (Dep.getInt()) {
  116. case Data:
  117. case Anti:
  118. case Output:
  119. return Contents.Reg == Other.Contents.Reg;
  120. case Order:
  121. return Contents.OrdKind == Other.Contents.OrdKind;
  122. }
  123. llvm_unreachable("Invalid dependency kind!");
  124. }
  125. bool operator==(const SDep &Other) const {
  126. return overlaps(Other) && Latency == Other.Latency;
  127. }
  128. bool operator!=(const SDep &Other) const {
  129. return !operator==(Other);
  130. }
  131. /// getLatency - Return the latency value for this edge, which roughly
  132. /// means the minimum number of cycles that must elapse between the
  133. /// predecessor and the successor, given that they have this edge
  134. /// between them.
  135. unsigned getLatency() const {
  136. return Latency;
  137. }
  138. /// setLatency - Set the latency for this edge.
  139. void setLatency(unsigned Lat) {
  140. Latency = Lat;
  141. }
  142. //// getSUnit - Return the SUnit to which this edge points.
  143. SUnit *getSUnit() const {
  144. return Dep.getPointer();
  145. }
  146. //// setSUnit - Assign the SUnit to which this edge points.
  147. void setSUnit(SUnit *SU) {
  148. Dep.setPointer(SU);
  149. }
  150. /// getKind - Return an enum value representing the kind of the dependence.
  151. Kind getKind() const {
  152. return Dep.getInt();
  153. }
  154. /// isCtrl - Shorthand for getKind() != SDep::Data.
  155. bool isCtrl() const {
  156. return getKind() != Data;
  157. }
  158. /// isNormalMemory - Test if this is an Order dependence between two
  159. /// memory accesses where both sides of the dependence access memory
  160. /// in non-volatile and fully modeled ways.
  161. bool isNormalMemory() const {
  162. return getKind() == Order && (Contents.OrdKind == MayAliasMem
  163. || Contents.OrdKind == MustAliasMem);
  164. }
  165. /// isMustAlias - Test if this is an Order dependence that is marked
  166. /// as "must alias", meaning that the SUnits at either end of the edge
  167. /// have a memory dependence on a known memory location.
  168. bool isMustAlias() const {
  169. return getKind() == Order && Contents.OrdKind == MustAliasMem;
  170. }
  171. /// isWeak - Test if this a weak dependence. Weak dependencies are
  172. /// considered DAG edges for height computation and other heuristics, but do
  173. /// not force ordering. Breaking a weak edge may require the scheduler to
  174. /// compensate, for example by inserting a copy.
  175. bool isWeak() const {
  176. return getKind() == Order && Contents.OrdKind >= Weak;
  177. }
  178. /// isArtificial - Test if this is an Order dependence that is marked
  179. /// as "artificial", meaning it isn't necessary for correctness.
  180. bool isArtificial() const {
  181. return getKind() == Order && Contents.OrdKind == Artificial;
  182. }
  183. /// isCluster - Test if this is an Order dependence that is marked
  184. /// as "cluster", meaning it is artificial and wants to be adjacent.
  185. bool isCluster() const {
  186. return getKind() == Order && Contents.OrdKind == Cluster;
  187. }
  188. /// isAssignedRegDep - Test if this is a Data dependence that is
  189. /// associated with a register.
  190. bool isAssignedRegDep() const {
  191. return getKind() == Data && Contents.Reg != 0;
  192. }
  193. /// getReg - Return the register associated with this edge. This is
  194. /// only valid on Data, Anti, and Output edges. On Data edges, this
  195. /// value may be zero, meaning there is no associated register.
  196. unsigned getReg() const {
  197. assert((getKind() == Data || getKind() == Anti || getKind() == Output) &&
  198. "getReg called on non-register dependence edge!");
  199. return Contents.Reg;
  200. }
  201. /// setReg - Assign the associated register for this edge. This is
  202. /// only valid on Data, Anti, and Output edges. On Anti and Output
  203. /// edges, this value must not be zero. On Data edges, the value may
  204. /// be zero, which would mean that no specific register is associated
  205. /// with this edge.
  206. void setReg(unsigned Reg) {
  207. assert((getKind() == Data || getKind() == Anti || getKind() == Output) &&
  208. "setReg called on non-register dependence edge!");
  209. assert((getKind() != Anti || Reg != 0) &&
  210. "SDep::Anti edge cannot use the zero register!");
  211. assert((getKind() != Output || Reg != 0) &&
  212. "SDep::Output edge cannot use the zero register!");
  213. Contents.Reg = Reg;
  214. }
  215. };
  216. template <>
  217. struct isPodLike<SDep> { static const bool value = true; };
  218. /// SUnit - Scheduling unit. This is a node in the scheduling DAG.
  219. class SUnit {
  220. private:
  221. enum LLVM_ENUM_INT_TYPE(unsigned) { BoundaryID = ~0u };
  222. SDNode *Node; // Representative node.
  223. MachineInstr *Instr; // Alternatively, a MachineInstr.
  224. public:
  225. SUnit *OrigNode; // If not this, the node from which
  226. // this node was cloned.
  227. // (SD scheduling only)
  228. const MCSchedClassDesc *SchedClass; // NULL or resolved SchedClass.
  229. // Preds/Succs - The SUnits before/after us in the graph.
  230. SmallVector<SDep, 4> Preds; // All sunit predecessors.
  231. SmallVector<SDep, 4> Succs; // All sunit successors.
  232. typedef SmallVectorImpl<SDep>::iterator pred_iterator;
  233. typedef SmallVectorImpl<SDep>::iterator succ_iterator;
  234. typedef SmallVectorImpl<SDep>::const_iterator const_pred_iterator;
  235. typedef SmallVectorImpl<SDep>::const_iterator const_succ_iterator;
  236. unsigned NodeNum; // Entry # of node in the node vector.
  237. unsigned NodeQueueId; // Queue id of node.
  238. unsigned NumPreds; // # of SDep::Data preds.
  239. unsigned NumSuccs; // # of SDep::Data sucss.
  240. unsigned NumPredsLeft; // # of preds not scheduled.
  241. unsigned NumSuccsLeft; // # of succs not scheduled.
  242. unsigned WeakPredsLeft; // # of weak preds not scheduled.
  243. unsigned WeakSuccsLeft; // # of weak succs not scheduled.
  244. unsigned short NumRegDefsLeft; // # of reg defs with no scheduled use.
  245. unsigned short Latency; // Node latency.
  246. bool isVRegCycle : 1; // May use and def the same vreg.
  247. bool isCall : 1; // Is a function call.
  248. bool isCallOp : 1; // Is a function call operand.
  249. bool isTwoAddress : 1; // Is a two-address instruction.
  250. bool isCommutable : 1; // Is a commutable instruction.
  251. bool hasPhysRegUses : 1; // Has physreg uses.
  252. bool hasPhysRegDefs : 1; // Has physreg defs that are being used.
  253. bool hasPhysRegClobbers : 1; // Has any physreg defs, used or not.
  254. bool isPending : 1; // True once pending.
  255. bool isAvailable : 1; // True once available.
  256. bool isScheduled : 1; // True once scheduled.
  257. bool isScheduleHigh : 1; // True if preferable to schedule high.
  258. bool isScheduleLow : 1; // True if preferable to schedule low.
  259. bool isCloned : 1; // True if this node has been cloned.
  260. Sched::Preference SchedulingPref; // Scheduling preference.
  261. private:
  262. bool isDepthCurrent : 1; // True if Depth is current.
  263. bool isHeightCurrent : 1; // True if Height is current.
  264. unsigned Depth; // Node depth.
  265. unsigned Height; // Node height.
  266. public:
  267. unsigned TopReadyCycle; // Cycle relative to start when node is ready.
  268. unsigned BotReadyCycle; // Cycle relative to end when node is ready.
  269. const TargetRegisterClass *CopyDstRC; // Is a special copy node if not null.
  270. const TargetRegisterClass *CopySrcRC;
  271. /// SUnit - Construct an SUnit for pre-regalloc scheduling to represent
  272. /// an SDNode and any nodes flagged to it.
  273. SUnit(SDNode *node, unsigned nodenum)
  274. : Node(node), Instr(0), OrigNode(0), SchedClass(0), NodeNum(nodenum),
  275. NodeQueueId(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0),
  276. NumSuccsLeft(0), WeakPredsLeft(0), WeakSuccsLeft(0), NumRegDefsLeft(0),
  277. Latency(0), isVRegCycle(false), isCall(false), isCallOp(false),
  278. isTwoAddress(false), isCommutable(false), hasPhysRegUses(false),
  279. hasPhysRegDefs(false), hasPhysRegClobbers(false), isPending(false),
  280. isAvailable(false), isScheduled(false), isScheduleHigh(false),
  281. isScheduleLow(false), isCloned(false), SchedulingPref(Sched::None),
  282. isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0),
  283. TopReadyCycle(0), BotReadyCycle(0), CopyDstRC(NULL), CopySrcRC(NULL) {}
  284. /// SUnit - Construct an SUnit for post-regalloc scheduling to represent
  285. /// a MachineInstr.
  286. SUnit(MachineInstr *instr, unsigned nodenum)
  287. : Node(0), Instr(instr), OrigNode(0), SchedClass(0), NodeNum(nodenum),
  288. NodeQueueId(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0),
  289. NumSuccsLeft(0), WeakPredsLeft(0), WeakSuccsLeft(0), NumRegDefsLeft(0),
  290. Latency(0), isVRegCycle(false), isCall(false), isCallOp(false),
  291. isTwoAddress(false), isCommutable(false), hasPhysRegUses(false),
  292. hasPhysRegDefs(false), hasPhysRegClobbers(false), isPending(false),
  293. isAvailable(false), isScheduled(false), isScheduleHigh(false),
  294. isScheduleLow(false), isCloned(false), SchedulingPref(Sched::None),
  295. isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0),
  296. TopReadyCycle(0), BotReadyCycle(0), CopyDstRC(NULL), CopySrcRC(NULL) {}
  297. /// SUnit - Construct a placeholder SUnit.
  298. SUnit()
  299. : Node(0), Instr(0), OrigNode(0), SchedClass(0), NodeNum(BoundaryID),
  300. NodeQueueId(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0),
  301. NumSuccsLeft(0), WeakPredsLeft(0), WeakSuccsLeft(0), NumRegDefsLeft(0),
  302. Latency(0), isVRegCycle(false), isCall(false), isCallOp(false),
  303. isTwoAddress(false), isCommutable(false), hasPhysRegUses(false),
  304. hasPhysRegDefs(false), hasPhysRegClobbers(false), isPending(false),
  305. isAvailable(false), isScheduled(false), isScheduleHigh(false),
  306. isScheduleLow(false), isCloned(false), SchedulingPref(Sched::None),
  307. isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0),
  308. TopReadyCycle(0), BotReadyCycle(0), CopyDstRC(NULL), CopySrcRC(NULL) {}
  309. /// \brief Boundary nodes are placeholders for the boundary of the
  310. /// scheduling region.
  311. ///
  312. /// BoundaryNodes can have DAG edges, including Data edges, but they do not
  313. /// correspond to schedulable entities (e.g. instructions) and do not have a
  314. /// valid ID. Consequently, always check for boundary nodes before accessing
  315. /// an assoicative data structure keyed on node ID.
  316. bool isBoundaryNode() const { return NodeNum == BoundaryID; };
  317. /// setNode - Assign the representative SDNode for this SUnit.
  318. /// This may be used during pre-regalloc scheduling.
  319. void setNode(SDNode *N) {
  320. assert(!Instr && "Setting SDNode of SUnit with MachineInstr!");
  321. Node = N;
  322. }
  323. /// getNode - Return the representative SDNode for this SUnit.
  324. /// This may be used during pre-regalloc scheduling.
  325. SDNode *getNode() const {
  326. assert(!Instr && "Reading SDNode of SUnit with MachineInstr!");
  327. return Node;
  328. }
  329. /// isInstr - Return true if this SUnit refers to a machine instruction as
  330. /// opposed to an SDNode.
  331. bool isInstr() const { return Instr; }
  332. /// setInstr - Assign the instruction for the SUnit.
  333. /// This may be used during post-regalloc scheduling.
  334. void setInstr(MachineInstr *MI) {
  335. assert(!Node && "Setting MachineInstr of SUnit with SDNode!");
  336. Instr = MI;
  337. }
  338. /// getInstr - Return the representative MachineInstr for this SUnit.
  339. /// This may be used during post-regalloc scheduling.
  340. MachineInstr *getInstr() const {
  341. assert(!Node && "Reading MachineInstr of SUnit with SDNode!");
  342. return Instr;
  343. }
  344. /// addPred - This adds the specified edge as a pred of the current node if
  345. /// not already. It also adds the current node as a successor of the
  346. /// specified node.
  347. bool addPred(const SDep &D, bool Required = true);
  348. /// removePred - This removes the specified edge as a pred of the current
  349. /// node if it exists. It also removes the current node as a successor of
  350. /// the specified node.
  351. void removePred(const SDep &D);
  352. /// getDepth - Return the depth of this node, which is the length of the
  353. /// maximum path up to any node which has no predecessors.
  354. unsigned getDepth() const {
  355. if (!isDepthCurrent)
  356. const_cast<SUnit *>(this)->ComputeDepth();
  357. return Depth;
  358. }
  359. /// getHeight - Return the height of this node, which is the length of the
  360. /// maximum path down to any node which has no successors.
  361. unsigned getHeight() const {
  362. if (!isHeightCurrent)
  363. const_cast<SUnit *>(this)->ComputeHeight();
  364. return Height;
  365. }
  366. /// setDepthToAtLeast - If NewDepth is greater than this node's
  367. /// depth value, set it to be the new depth value. This also
  368. /// recursively marks successor nodes dirty.
  369. void setDepthToAtLeast(unsigned NewDepth);
  370. /// setDepthToAtLeast - If NewDepth is greater than this node's
  371. /// depth value, set it to be the new height value. This also
  372. /// recursively marks predecessor nodes dirty.
  373. void setHeightToAtLeast(unsigned NewHeight);
  374. /// setDepthDirty - Set a flag in this node to indicate that its
  375. /// stored Depth value will require recomputation the next time
  376. /// getDepth() is called.
  377. void setDepthDirty();
  378. /// setHeightDirty - Set a flag in this node to indicate that its
  379. /// stored Height value will require recomputation the next time
  380. /// getHeight() is called.
  381. void setHeightDirty();
  382. /// isPred - Test if node N is a predecessor of this node.
  383. bool isPred(SUnit *N) {
  384. for (unsigned i = 0, e = (unsigned)Preds.size(); i != e; ++i)
  385. if (Preds[i].getSUnit() == N)
  386. return true;
  387. return false;
  388. }
  389. /// isSucc - Test if node N is a successor of this node.
  390. bool isSucc(SUnit *N) {
  391. for (unsigned i = 0, e = (unsigned)Succs.size(); i != e; ++i)
  392. if (Succs[i].getSUnit() == N)
  393. return true;
  394. return false;
  395. }
  396. bool isTopReady() const {
  397. return NumPredsLeft == 0;
  398. }
  399. bool isBottomReady() const {
  400. return NumSuccsLeft == 0;
  401. }
  402. /// \brief Order this node's predecessor edges such that the critical path
  403. /// edge occurs first.
  404. void biasCriticalPath();
  405. void dump(const ScheduleDAG *G) const;
  406. void dumpAll(const ScheduleDAG *G) const;
  407. void print(raw_ostream &O, const ScheduleDAG *G) const;
  408. private:
  409. void ComputeDepth();
  410. void ComputeHeight();
  411. };
  412. //===--------------------------------------------------------------------===//
  413. /// SchedulingPriorityQueue - This interface is used to plug different
  414. /// priorities computation algorithms into the list scheduler. It implements
  415. /// the interface of a standard priority queue, where nodes are inserted in
  416. /// arbitrary order and returned in priority order. The computation of the
  417. /// priority and the representation of the queue are totally up to the
  418. /// implementation to decide.
  419. ///
  420. class SchedulingPriorityQueue {
  421. virtual void anchor();
  422. unsigned CurCycle;
  423. bool HasReadyFilter;
  424. public:
  425. SchedulingPriorityQueue(bool rf = false):
  426. CurCycle(0), HasReadyFilter(rf) {}
  427. virtual ~SchedulingPriorityQueue() {}
  428. virtual bool isBottomUp() const = 0;
  429. virtual void initNodes(std::vector<SUnit> &SUnits) = 0;
  430. virtual void addNode(const SUnit *SU) = 0;
  431. virtual void updateNode(const SUnit *SU) = 0;
  432. virtual void releaseState() = 0;
  433. virtual bool empty() const = 0;
  434. bool hasReadyFilter() const { return HasReadyFilter; }
  435. virtual bool tracksRegPressure() const { return false; }
  436. virtual bool isReady(SUnit *) const {
  437. assert(!HasReadyFilter && "The ready filter must override isReady()");
  438. return true;
  439. }
  440. virtual void push(SUnit *U) = 0;
  441. void push_all(const std::vector<SUnit *> &Nodes) {
  442. for (std::vector<SUnit *>::const_iterator I = Nodes.begin(),
  443. E = Nodes.end(); I != E; ++I)
  444. push(*I);
  445. }
  446. virtual SUnit *pop() = 0;
  447. virtual void remove(SUnit *SU) = 0;
  448. virtual void dump(ScheduleDAG *) const {}
  449. /// scheduledNode - As each node is scheduled, this method is invoked. This
  450. /// allows the priority function to adjust the priority of related
  451. /// unscheduled nodes, for example.
  452. ///
  453. virtual void scheduledNode(SUnit *) {}
  454. virtual void unscheduledNode(SUnit *) {}
  455. void setCurCycle(unsigned Cycle) {
  456. CurCycle = Cycle;
  457. }
  458. unsigned getCurCycle() const {
  459. return CurCycle;
  460. }
  461. };
  462. class ScheduleDAG {
  463. public:
  464. const TargetMachine &TM; // Target processor
  465. const TargetInstrInfo *TII; // Target instruction information
  466. const TargetRegisterInfo *TRI; // Target processor register info
  467. MachineFunction &MF; // Machine function
  468. MachineRegisterInfo &MRI; // Virtual/real register map
  469. std::vector<SUnit> SUnits; // The scheduling units.
  470. SUnit EntrySU; // Special node for the region entry.
  471. SUnit ExitSU; // Special node for the region exit.
  472. #ifdef NDEBUG
  473. static const bool StressSched = false;
  474. #else
  475. bool StressSched;
  476. #endif
  477. explicit ScheduleDAG(MachineFunction &mf);
  478. virtual ~ScheduleDAG();
  479. /// clearDAG - clear the DAG state (between regions).
  480. void clearDAG();
  481. /// getInstrDesc - Return the MCInstrDesc of this SUnit.
  482. /// Return NULL for SDNodes without a machine opcode.
  483. const MCInstrDesc *getInstrDesc(const SUnit *SU) const {
  484. if (SU->isInstr()) return &SU->getInstr()->getDesc();
  485. return getNodeDesc(SU->getNode());
  486. }
  487. /// viewGraph - Pop up a GraphViz/gv window with the ScheduleDAG rendered
  488. /// using 'dot'.
  489. ///
  490. virtual void viewGraph(const Twine &Name, const Twine &Title);
  491. virtual void viewGraph();
  492. virtual void dumpNode(const SUnit *SU) const = 0;
  493. /// getGraphNodeLabel - Return a label for an SUnit node in a visualization
  494. /// of the ScheduleDAG.
  495. virtual std::string getGraphNodeLabel(const SUnit *SU) const = 0;
  496. /// getDAGLabel - Return a label for the region of code covered by the DAG.
  497. virtual std::string getDAGName() const = 0;
  498. /// addCustomGraphFeatures - Add custom features for a visualization of
  499. /// the ScheduleDAG.
  500. virtual void addCustomGraphFeatures(GraphWriter<ScheduleDAG*> &) const {}
  501. #ifndef NDEBUG
  502. /// VerifyScheduledDAG - Verify that all SUnits were scheduled and that
  503. /// their state is consistent. Return the number of scheduled SUnits.
  504. unsigned VerifyScheduledDAG(bool isBottomUp);
  505. #endif
  506. private:
  507. // Return the MCInstrDesc of this SDNode or NULL.
  508. const MCInstrDesc *getNodeDesc(const SDNode *Node) const;
  509. };
  510. class SUnitIterator : public std::iterator<std::forward_iterator_tag,
  511. SUnit, ptrdiff_t> {
  512. SUnit *Node;
  513. unsigned Operand;
  514. SUnitIterator(SUnit *N, unsigned Op) : Node(N), Operand(Op) {}
  515. public:
  516. bool operator==(const SUnitIterator& x) const {
  517. return Operand == x.Operand;
  518. }
  519. bool operator!=(const SUnitIterator& x) const { return !operator==(x); }
  520. const SUnitIterator &operator=(const SUnitIterator &I) {
  521. assert(I.Node==Node && "Cannot assign iterators to two different nodes!");
  522. Operand = I.Operand;
  523. return *this;
  524. }
  525. pointer operator*() const {
  526. return Node->Preds[Operand].getSUnit();
  527. }
  528. pointer operator->() const { return operator*(); }
  529. SUnitIterator& operator++() { // Preincrement
  530. ++Operand;
  531. return *this;
  532. }
  533. SUnitIterator operator++(int) { // Postincrement
  534. SUnitIterator tmp = *this; ++*this; return tmp;
  535. }
  536. static SUnitIterator begin(SUnit *N) { return SUnitIterator(N, 0); }
  537. static SUnitIterator end (SUnit *N) {
  538. return SUnitIterator(N, (unsigned)N->Preds.size());
  539. }
  540. unsigned getOperand() const { return Operand; }
  541. const SUnit *getNode() const { return Node; }
  542. /// isCtrlDep - Test if this is not an SDep::Data dependence.
  543. bool isCtrlDep() const {
  544. return getSDep().isCtrl();
  545. }
  546. bool isArtificialDep() const {
  547. return getSDep().isArtificial();
  548. }
  549. const SDep &getSDep() const {
  550. return Node->Preds[Operand];
  551. }
  552. };
  553. template <> struct GraphTraits<SUnit*> {
  554. typedef SUnit NodeType;
  555. typedef SUnitIterator ChildIteratorType;
  556. static inline NodeType *getEntryNode(SUnit *N) { return N; }
  557. static inline ChildIteratorType child_begin(NodeType *N) {
  558. return SUnitIterator::begin(N);
  559. }
  560. static inline ChildIteratorType child_end(NodeType *N) {
  561. return SUnitIterator::end(N);
  562. }
  563. };
  564. template <> struct GraphTraits<ScheduleDAG*> : public GraphTraits<SUnit*> {
  565. typedef std::vector<SUnit>::iterator nodes_iterator;
  566. static nodes_iterator nodes_begin(ScheduleDAG *G) {
  567. return G->SUnits.begin();
  568. }
  569. static nodes_iterator nodes_end(ScheduleDAG *G) {
  570. return G->SUnits.end();
  571. }
  572. };
  573. /// ScheduleDAGTopologicalSort is a class that computes a topological
  574. /// ordering for SUnits and provides methods for dynamically updating
  575. /// the ordering as new edges are added.
  576. ///
  577. /// This allows a very fast implementation of IsReachable, for example.
  578. ///
  579. class ScheduleDAGTopologicalSort {
  580. /// SUnits - A reference to the ScheduleDAG's SUnits.
  581. std::vector<SUnit> &SUnits;
  582. SUnit *ExitSU;
  583. /// Index2Node - Maps topological index to the node number.
  584. std::vector<int> Index2Node;
  585. /// Node2Index - Maps the node number to its topological index.
  586. std::vector<int> Node2Index;
  587. /// Visited - a set of nodes visited during a DFS traversal.
  588. BitVector Visited;
  589. /// DFS - make a DFS traversal and mark all nodes affected by the
  590. /// edge insertion. These nodes will later get new topological indexes
  591. /// by means of the Shift method.
  592. void DFS(const SUnit *SU, int UpperBound, bool& HasLoop);
  593. /// Shift - reassign topological indexes for the nodes in the DAG
  594. /// to preserve the topological ordering.
  595. void Shift(BitVector& Visited, int LowerBound, int UpperBound);
  596. /// Allocate - assign the topological index to the node n.
  597. void Allocate(int n, int index);
  598. public:
  599. ScheduleDAGTopologicalSort(std::vector<SUnit> &SUnits, SUnit *ExitSU);
  600. /// InitDAGTopologicalSorting - create the initial topological
  601. /// ordering from the DAG to be scheduled.
  602. void InitDAGTopologicalSorting();
  603. /// IsReachable - Checks if SU is reachable from TargetSU.
  604. bool IsReachable(const SUnit *SU, const SUnit *TargetSU);
  605. /// WillCreateCycle - Return true if addPred(TargetSU, SU) creates a cycle.
  606. bool WillCreateCycle(SUnit *TargetSU, SUnit *SU);
  607. /// AddPred - Updates the topological ordering to accommodate an edge
  608. /// to be added from SUnit X to SUnit Y.
  609. void AddPred(SUnit *Y, SUnit *X);
  610. /// RemovePred - Updates the topological ordering to accommodate an
  611. /// an edge to be removed from the specified node N from the predecessors
  612. /// of the current node M.
  613. void RemovePred(SUnit *M, SUnit *N);
  614. typedef std::vector<int>::iterator iterator;
  615. typedef std::vector<int>::const_iterator const_iterator;
  616. iterator begin() { return Index2Node.begin(); }
  617. const_iterator begin() const { return Index2Node.begin(); }
  618. iterator end() { return Index2Node.end(); }
  619. const_iterator end() const { return Index2Node.end(); }
  620. typedef std::vector<int>::reverse_iterator reverse_iterator;
  621. typedef std::vector<int>::const_reverse_iterator const_reverse_iterator;
  622. reverse_iterator rbegin() { return Index2Node.rbegin(); }
  623. const_reverse_iterator rbegin() const { return Index2Node.rbegin(); }
  624. reverse_iterator rend() { return Index2Node.rend(); }
  625. const_reverse_iterator rend() const { return Index2Node.rend(); }
  626. };
  627. }
  628. #endif