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/3rd_party/llvm/lib/CodeGen/MachineVerifier.cpp

https://code.google.com/p/softart/
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   1//===-- MachineVerifier.cpp - Machine Code Verifier -----------------------===//
   2//
   3//                     The LLVM Compiler Infrastructure
   4//
   5// This file is distributed under the University of Illinois Open Source
   6// License. See LICENSE.TXT for details.
   7//
   8//===----------------------------------------------------------------------===//
   9//
  10// Pass to verify generated machine code. The following is checked:
  11//
  12// Operand counts: All explicit operands must be present.
  13//
  14// Register classes: All physical and virtual register operands must be
  15// compatible with the register class required by the instruction descriptor.
  16//
  17// Register live intervals: Registers must be defined only once, and must be
  18// defined before use.
  19//
  20// The machine code verifier is enabled from LLVMTargetMachine.cpp with the
  21// command-line option -verify-machineinstrs, or by defining the environment
  22// variable LLVM_VERIFY_MACHINEINSTRS to the name of a file that will receive
  23// the verifier errors.
  24//===----------------------------------------------------------------------===//
  25
  26#include "llvm/CodeGen/Passes.h"
  27#include "llvm/ADT/DenseSet.h"
  28#include "llvm/ADT/DepthFirstIterator.h"
  29#include "llvm/ADT/SetOperations.h"
  30#include "llvm/ADT/SmallVector.h"
  31#include "llvm/CodeGen/LiveIntervalAnalysis.h"
  32#include "llvm/CodeGen/LiveStackAnalysis.h"
  33#include "llvm/CodeGen/LiveVariables.h"
  34#include "llvm/CodeGen/MachineFrameInfo.h"
  35#include "llvm/CodeGen/MachineFunctionPass.h"
  36#include "llvm/CodeGen/MachineInstrBundle.h"
  37#include "llvm/CodeGen/MachineMemOperand.h"
  38#include "llvm/CodeGen/MachineRegisterInfo.h"
  39#include "llvm/IR/BasicBlock.h"
  40#include "llvm/IR/InlineAsm.h"
  41#include "llvm/IR/Instructions.h"
  42#include "llvm/MC/MCAsmInfo.h"
  43#include "llvm/Support/Debug.h"
  44#include "llvm/Support/ErrorHandling.h"
  45#include "llvm/Support/raw_ostream.h"
  46#include "llvm/Target/TargetInstrInfo.h"
  47#include "llvm/Target/TargetMachine.h"
  48#include "llvm/Target/TargetRegisterInfo.h"
  49using namespace llvm;
  50
  51namespace {
  52  struct MachineVerifier {
  53
  54    MachineVerifier(Pass *pass, const char *b) :
  55      PASS(pass),
  56      Banner(b),
  57      OutFileName(getenv("LLVM_VERIFY_MACHINEINSTRS"))
  58      {}
  59
  60    bool runOnMachineFunction(MachineFunction &MF);
  61
  62    Pass *const PASS;
  63    const char *Banner;
  64    const char *const OutFileName;
  65    raw_ostream *OS;
  66    const MachineFunction *MF;
  67    const TargetMachine *TM;
  68    const TargetInstrInfo *TII;
  69    const TargetRegisterInfo *TRI;
  70    const MachineRegisterInfo *MRI;
  71
  72    unsigned foundErrors;
  73
  74    typedef SmallVector<unsigned, 16> RegVector;
  75    typedef SmallVector<const uint32_t*, 4> RegMaskVector;
  76    typedef DenseSet<unsigned> RegSet;
  77    typedef DenseMap<unsigned, const MachineInstr*> RegMap;
  78    typedef SmallPtrSet<const MachineBasicBlock*, 8> BlockSet;
  79
  80    const MachineInstr *FirstTerminator;
  81    BlockSet FunctionBlocks;
  82
  83    BitVector regsReserved;
  84    RegSet regsLive;
  85    RegVector regsDefined, regsDead, regsKilled;
  86    RegMaskVector regMasks;
  87    RegSet regsLiveInButUnused;
  88
  89    SlotIndex lastIndex;
  90
  91    // Add Reg and any sub-registers to RV
  92    void addRegWithSubRegs(RegVector &RV, unsigned Reg) {
  93      RV.push_back(Reg);
  94      if (TargetRegisterInfo::isPhysicalRegister(Reg))
  95        for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs)
  96          RV.push_back(*SubRegs);
  97    }
  98
  99    struct BBInfo {
 100      // Is this MBB reachable from the MF entry point?
 101      bool reachable;
 102
 103      // Vregs that must be live in because they are used without being
 104      // defined. Map value is the user.
 105      RegMap vregsLiveIn;
 106
 107      // Regs killed in MBB. They may be defined again, and will then be in both
 108      // regsKilled and regsLiveOut.
 109      RegSet regsKilled;
 110
 111      // Regs defined in MBB and live out. Note that vregs passing through may
 112      // be live out without being mentioned here.
 113      RegSet regsLiveOut;
 114
 115      // Vregs that pass through MBB untouched. This set is disjoint from
 116      // regsKilled and regsLiveOut.
 117      RegSet vregsPassed;
 118
 119      // Vregs that must pass through MBB because they are needed by a successor
 120      // block. This set is disjoint from regsLiveOut.
 121      RegSet vregsRequired;
 122
 123      // Set versions of block's predecessor and successor lists.
 124      BlockSet Preds, Succs;
 125
 126      BBInfo() : reachable(false) {}
 127
 128      // Add register to vregsPassed if it belongs there. Return true if
 129      // anything changed.
 130      bool addPassed(unsigned Reg) {
 131        if (!TargetRegisterInfo::isVirtualRegister(Reg))
 132          return false;
 133        if (regsKilled.count(Reg) || regsLiveOut.count(Reg))
 134          return false;
 135        return vregsPassed.insert(Reg).second;
 136      }
 137
 138      // Same for a full set.
 139      bool addPassed(const RegSet &RS) {
 140        bool changed = false;
 141        for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
 142          if (addPassed(*I))
 143            changed = true;
 144        return changed;
 145      }
 146
 147      // Add register to vregsRequired if it belongs there. Return true if
 148      // anything changed.
 149      bool addRequired(unsigned Reg) {
 150        if (!TargetRegisterInfo::isVirtualRegister(Reg))
 151          return false;
 152        if (regsLiveOut.count(Reg))
 153          return false;
 154        return vregsRequired.insert(Reg).second;
 155      }
 156
 157      // Same for a full set.
 158      bool addRequired(const RegSet &RS) {
 159        bool changed = false;
 160        for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
 161          if (addRequired(*I))
 162            changed = true;
 163        return changed;
 164      }
 165
 166      // Same for a full map.
 167      bool addRequired(const RegMap &RM) {
 168        bool changed = false;
 169        for (RegMap::const_iterator I = RM.begin(), E = RM.end(); I != E; ++I)
 170          if (addRequired(I->first))
 171            changed = true;
 172        return changed;
 173      }
 174
 175      // Live-out registers are either in regsLiveOut or vregsPassed.
 176      bool isLiveOut(unsigned Reg) const {
 177        return regsLiveOut.count(Reg) || vregsPassed.count(Reg);
 178      }
 179    };
 180
 181    // Extra register info per MBB.
 182    DenseMap<const MachineBasicBlock*, BBInfo> MBBInfoMap;
 183
 184    bool isReserved(unsigned Reg) {
 185      return Reg < regsReserved.size() && regsReserved.test(Reg);
 186    }
 187
 188    bool isAllocatable(unsigned Reg) {
 189      return Reg < TRI->getNumRegs() && MRI->isAllocatable(Reg);
 190    }
 191
 192    // Analysis information if available
 193    LiveVariables *LiveVars;
 194    LiveIntervals *LiveInts;
 195    LiveStacks *LiveStks;
 196    SlotIndexes *Indexes;
 197
 198    void visitMachineFunctionBefore();
 199    void visitMachineBasicBlockBefore(const MachineBasicBlock *MBB);
 200    void visitMachineBundleBefore(const MachineInstr *MI);
 201    void visitMachineInstrBefore(const MachineInstr *MI);
 202    void visitMachineOperand(const MachineOperand *MO, unsigned MONum);
 203    void visitMachineInstrAfter(const MachineInstr *MI);
 204    void visitMachineBundleAfter(const MachineInstr *MI);
 205    void visitMachineBasicBlockAfter(const MachineBasicBlock *MBB);
 206    void visitMachineFunctionAfter();
 207
 208    void report(const char *msg, const MachineFunction *MF);
 209    void report(const char *msg, const MachineBasicBlock *MBB);
 210    void report(const char *msg, const MachineInstr *MI);
 211    void report(const char *msg, const MachineOperand *MO, unsigned MONum);
 212    void report(const char *msg, const MachineFunction *MF,
 213                const LiveInterval &LI);
 214    void report(const char *msg, const MachineBasicBlock *MBB,
 215                const LiveInterval &LI);
 216    void report(const char *msg, const MachineFunction *MF,
 217                const LiveRange &LR);
 218    void report(const char *msg, const MachineBasicBlock *MBB,
 219                const LiveRange &LR);
 220
 221    void verifyInlineAsm(const MachineInstr *MI);
 222
 223    void checkLiveness(const MachineOperand *MO, unsigned MONum);
 224    void markReachable(const MachineBasicBlock *MBB);
 225    void calcRegsPassed();
 226    void checkPHIOps(const MachineBasicBlock *MBB);
 227
 228    void calcRegsRequired();
 229    void verifyLiveVariables();
 230    void verifyLiveIntervals();
 231    void verifyLiveInterval(const LiveInterval&);
 232    void verifyLiveRangeValue(const LiveRange&, const VNInfo*, unsigned);
 233    void verifyLiveRangeSegment(const LiveRange&,
 234                                const LiveRange::const_iterator I, unsigned);
 235    void verifyLiveRange(const LiveRange&, unsigned);
 236
 237    void verifyStackFrame();
 238  };
 239
 240  struct MachineVerifierPass : public MachineFunctionPass {
 241    static char ID; // Pass ID, replacement for typeid
 242    const char *const Banner;
 243
 244    MachineVerifierPass(const char *b = 0)
 245      : MachineFunctionPass(ID), Banner(b) {
 246        initializeMachineVerifierPassPass(*PassRegistry::getPassRegistry());
 247      }
 248
 249    void getAnalysisUsage(AnalysisUsage &AU) const {
 250      AU.setPreservesAll();
 251      MachineFunctionPass::getAnalysisUsage(AU);
 252    }
 253
 254    bool runOnMachineFunction(MachineFunction &MF) {
 255      MF.verify(this, Banner);
 256      return false;
 257    }
 258  };
 259
 260}
 261
 262char MachineVerifierPass::ID = 0;
 263INITIALIZE_PASS(MachineVerifierPass, "machineverifier",
 264                "Verify generated machine code", false, false)
 265
 266FunctionPass *llvm::createMachineVerifierPass(const char *Banner) {
 267  return new MachineVerifierPass(Banner);
 268}
 269
 270void MachineFunction::verify(Pass *p, const char *Banner) const {
 271  MachineVerifier(p, Banner)
 272    .runOnMachineFunction(const_cast<MachineFunction&>(*this));
 273}
 274
 275bool MachineVerifier::runOnMachineFunction(MachineFunction &MF) {
 276  raw_ostream *OutFile = 0;
 277  if (OutFileName) {
 278    std::string ErrorInfo;
 279    OutFile = new raw_fd_ostream(OutFileName, ErrorInfo, sys::fs::F_Append);
 280    if (!ErrorInfo.empty()) {
 281      errs() << "Error opening '" << OutFileName << "': " << ErrorInfo << '\n';
 282      exit(1);
 283    }
 284
 285    OS = OutFile;
 286  } else {
 287    OS = &errs();
 288  }
 289
 290  foundErrors = 0;
 291
 292  this->MF = &MF;
 293  TM = &MF.getTarget();
 294  TII = TM->getInstrInfo();
 295  TRI = TM->getRegisterInfo();
 296  MRI = &MF.getRegInfo();
 297
 298  LiveVars = NULL;
 299  LiveInts = NULL;
 300  LiveStks = NULL;
 301  Indexes = NULL;
 302  if (PASS) {
 303    LiveInts = PASS->getAnalysisIfAvailable<LiveIntervals>();
 304    // We don't want to verify LiveVariables if LiveIntervals is available.
 305    if (!LiveInts)
 306      LiveVars = PASS->getAnalysisIfAvailable<LiveVariables>();
 307    LiveStks = PASS->getAnalysisIfAvailable<LiveStacks>();
 308    Indexes = PASS->getAnalysisIfAvailable<SlotIndexes>();
 309  }
 310
 311  visitMachineFunctionBefore();
 312  for (MachineFunction::const_iterator MFI = MF.begin(), MFE = MF.end();
 313       MFI!=MFE; ++MFI) {
 314    visitMachineBasicBlockBefore(MFI);
 315    // Keep track of the current bundle header.
 316    const MachineInstr *CurBundle = 0;
 317    // Do we expect the next instruction to be part of the same bundle?
 318    bool InBundle = false;
 319
 320    for (MachineBasicBlock::const_instr_iterator MBBI = MFI->instr_begin(),
 321           MBBE = MFI->instr_end(); MBBI != MBBE; ++MBBI) {
 322      if (MBBI->getParent() != MFI) {
 323        report("Bad instruction parent pointer", MFI);
 324        *OS << "Instruction: " << *MBBI;
 325        continue;
 326      }
 327
 328      // Check for consistent bundle flags.
 329      if (InBundle && !MBBI->isBundledWithPred())
 330        report("Missing BundledPred flag, "
 331               "BundledSucc was set on predecessor", MBBI);
 332      if (!InBundle && MBBI->isBundledWithPred())
 333        report("BundledPred flag is set, "
 334               "but BundledSucc not set on predecessor", MBBI);
 335
 336      // Is this a bundle header?
 337      if (!MBBI->isInsideBundle()) {
 338        if (CurBundle)
 339          visitMachineBundleAfter(CurBundle);
 340        CurBundle = MBBI;
 341        visitMachineBundleBefore(CurBundle);
 342      } else if (!CurBundle)
 343        report("No bundle header", MBBI);
 344      visitMachineInstrBefore(MBBI);
 345      for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I)
 346        visitMachineOperand(&MBBI->getOperand(I), I);
 347      visitMachineInstrAfter(MBBI);
 348
 349      // Was this the last bundled instruction?
 350      InBundle = MBBI->isBundledWithSucc();
 351    }
 352    if (CurBundle)
 353      visitMachineBundleAfter(CurBundle);
 354    if (InBundle)
 355      report("BundledSucc flag set on last instruction in block", &MFI->back());
 356    visitMachineBasicBlockAfter(MFI);
 357  }
 358  visitMachineFunctionAfter();
 359
 360  if (OutFile)
 361    delete OutFile;
 362  else if (foundErrors)
 363    report_fatal_error("Found "+Twine(foundErrors)+" machine code errors.");
 364
 365  // Clean up.
 366  regsLive.clear();
 367  regsDefined.clear();
 368  regsDead.clear();
 369  regsKilled.clear();
 370  regMasks.clear();
 371  regsLiveInButUnused.clear();
 372  MBBInfoMap.clear();
 373
 374  return false;                 // no changes
 375}
 376
 377void MachineVerifier::report(const char *msg, const MachineFunction *MF) {
 378  assert(MF);
 379  *OS << '\n';
 380  if (!foundErrors++) {
 381    if (Banner)
 382      *OS << "# " << Banner << '\n';
 383    MF->print(*OS, Indexes);
 384  }
 385  *OS << "*** Bad machine code: " << msg << " ***\n"
 386      << "- function:    " << MF->getName() << "\n";
 387}
 388
 389void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB) {
 390  assert(MBB);
 391  report(msg, MBB->getParent());
 392  *OS << "- basic block: BB#" << MBB->getNumber()
 393      << ' ' << MBB->getName()
 394      << " (" << (const void*)MBB << ')';
 395  if (Indexes)
 396    *OS << " [" << Indexes->getMBBStartIdx(MBB)
 397        << ';' <<  Indexes->getMBBEndIdx(MBB) << ')';
 398  *OS << '\n';
 399}
 400
 401void MachineVerifier::report(const char *msg, const MachineInstr *MI) {
 402  assert(MI);
 403  report(msg, MI->getParent());
 404  *OS << "- instruction: ";
 405  if (Indexes && Indexes->hasIndex(MI))
 406    *OS << Indexes->getInstructionIndex(MI) << '\t';
 407  MI->print(*OS, TM);
 408}
 409
 410void MachineVerifier::report(const char *msg,
 411                             const MachineOperand *MO, unsigned MONum) {
 412  assert(MO);
 413  report(msg, MO->getParent());
 414  *OS << "- operand " << MONum << ":   ";
 415  MO->print(*OS, TM);
 416  *OS << "\n";
 417}
 418
 419void MachineVerifier::report(const char *msg, const MachineFunction *MF,
 420                             const LiveInterval &LI) {
 421  report(msg, MF);
 422  *OS << "- interval:    " << LI << '\n';
 423}
 424
 425void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB,
 426                             const LiveInterval &LI) {
 427  report(msg, MBB);
 428  *OS << "- interval:    " << LI << '\n';
 429}
 430
 431void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB,
 432                             const LiveRange &LR) {
 433  report(msg, MBB);
 434  *OS << "- liverange:    " << LR << "\n";
 435}
 436
 437void MachineVerifier::report(const char *msg, const MachineFunction *MF,
 438                             const LiveRange &LR) {
 439  report(msg, MF);
 440  *OS << "- liverange:    " << LR << "\n";
 441}
 442
 443void MachineVerifier::markReachable(const MachineBasicBlock *MBB) {
 444  BBInfo &MInfo = MBBInfoMap[MBB];
 445  if (!MInfo.reachable) {
 446    MInfo.reachable = true;
 447    for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
 448           SuE = MBB->succ_end(); SuI != SuE; ++SuI)
 449      markReachable(*SuI);
 450  }
 451}
 452
 453void MachineVerifier::visitMachineFunctionBefore() {
 454  lastIndex = SlotIndex();
 455  regsReserved = MRI->getReservedRegs();
 456
 457  // A sub-register of a reserved register is also reserved
 458  for (int Reg = regsReserved.find_first(); Reg>=0;
 459       Reg = regsReserved.find_next(Reg)) {
 460    for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
 461      // FIXME: This should probably be:
 462      // assert(regsReserved.test(*SubRegs) && "Non-reserved sub-register");
 463      regsReserved.set(*SubRegs);
 464    }
 465  }
 466
 467  markReachable(&MF->front());
 468
 469  // Build a set of the basic blocks in the function.
 470  FunctionBlocks.clear();
 471  for (MachineFunction::const_iterator
 472       I = MF->begin(), E = MF->end(); I != E; ++I) {
 473    FunctionBlocks.insert(I);
 474    BBInfo &MInfo = MBBInfoMap[I];
 475
 476    MInfo.Preds.insert(I->pred_begin(), I->pred_end());
 477    if (MInfo.Preds.size() != I->pred_size())
 478      report("MBB has duplicate entries in its predecessor list.", I);
 479
 480    MInfo.Succs.insert(I->succ_begin(), I->succ_end());
 481    if (MInfo.Succs.size() != I->succ_size())
 482      report("MBB has duplicate entries in its successor list.", I);
 483  }
 484
 485  // Check that the register use lists are sane.
 486  MRI->verifyUseLists();
 487
 488  verifyStackFrame();
 489}
 490
 491// Does iterator point to a and b as the first two elements?
 492static bool matchPair(MachineBasicBlock::const_succ_iterator i,
 493                      const MachineBasicBlock *a, const MachineBasicBlock *b) {
 494  if (*i == a)
 495    return *++i == b;
 496  if (*i == b)
 497    return *++i == a;
 498  return false;
 499}
 500
 501void
 502MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
 503  FirstTerminator = 0;
 504
 505  if (MRI->isSSA()) {
 506    // If this block has allocatable physical registers live-in, check that
 507    // it is an entry block or landing pad.
 508    for (MachineBasicBlock::livein_iterator LI = MBB->livein_begin(),
 509           LE = MBB->livein_end();
 510         LI != LE; ++LI) {
 511      unsigned reg = *LI;
 512      if (isAllocatable(reg) && !MBB->isLandingPad() &&
 513          MBB != MBB->getParent()->begin()) {
 514        report("MBB has allocable live-in, but isn't entry or landing-pad.", MBB);
 515      }
 516    }
 517  }
 518
 519  // Count the number of landing pad successors.
 520  SmallPtrSet<MachineBasicBlock*, 4> LandingPadSuccs;
 521  for (MachineBasicBlock::const_succ_iterator I = MBB->succ_begin(),
 522       E = MBB->succ_end(); I != E; ++I) {
 523    if ((*I)->isLandingPad())
 524      LandingPadSuccs.insert(*I);
 525    if (!FunctionBlocks.count(*I))
 526      report("MBB has successor that isn't part of the function.", MBB);
 527    if (!MBBInfoMap[*I].Preds.count(MBB)) {
 528      report("Inconsistent CFG", MBB);
 529      *OS << "MBB is not in the predecessor list of the successor BB#"
 530          << (*I)->getNumber() << ".\n";
 531    }
 532  }
 533
 534  // Check the predecessor list.
 535  for (MachineBasicBlock::const_pred_iterator I = MBB->pred_begin(),
 536       E = MBB->pred_end(); I != E; ++I) {
 537    if (!FunctionBlocks.count(*I))
 538      report("MBB has predecessor that isn't part of the function.", MBB);
 539    if (!MBBInfoMap[*I].Succs.count(MBB)) {
 540      report("Inconsistent CFG", MBB);
 541      *OS << "MBB is not in the successor list of the predecessor BB#"
 542          << (*I)->getNumber() << ".\n";
 543    }
 544  }
 545
 546  const MCAsmInfo *AsmInfo = TM->getMCAsmInfo();
 547  const BasicBlock *BB = MBB->getBasicBlock();
 548  if (LandingPadSuccs.size() > 1 &&
 549      !(AsmInfo &&
 550        AsmInfo->getExceptionHandlingType() == ExceptionHandling::SjLj &&
 551        BB && isa<SwitchInst>(BB->getTerminator())))
 552    report("MBB has more than one landing pad successor", MBB);
 553
 554  // Call AnalyzeBranch. If it succeeds, there several more conditions to check.
 555  MachineBasicBlock *TBB = 0, *FBB = 0;
 556  SmallVector<MachineOperand, 4> Cond;
 557  if (!TII->AnalyzeBranch(*const_cast<MachineBasicBlock *>(MBB),
 558                          TBB, FBB, Cond)) {
 559    // Ok, AnalyzeBranch thinks it knows what's going on with this block. Let's
 560    // check whether its answers match up with reality.
 561    if (!TBB && !FBB) {
 562      // Block falls through to its successor.
 563      MachineFunction::const_iterator MBBI = MBB;
 564      ++MBBI;
 565      if (MBBI == MF->end()) {
 566        // It's possible that the block legitimately ends with a noreturn
 567        // call or an unreachable, in which case it won't actually fall
 568        // out the bottom of the function.
 569      } else if (MBB->succ_size() == LandingPadSuccs.size()) {
 570        // It's possible that the block legitimately ends with a noreturn
 571        // call or an unreachable, in which case it won't actuall fall
 572        // out of the block.
 573      } else if (MBB->succ_size() != 1+LandingPadSuccs.size()) {
 574        report("MBB exits via unconditional fall-through but doesn't have "
 575               "exactly one CFG successor!", MBB);
 576      } else if (!MBB->isSuccessor(MBBI)) {
 577        report("MBB exits via unconditional fall-through but its successor "
 578               "differs from its CFG successor!", MBB);
 579      }
 580      if (!MBB->empty() && getBundleStart(&MBB->back())->isBarrier() &&
 581          !TII->isPredicated(getBundleStart(&MBB->back()))) {
 582        report("MBB exits via unconditional fall-through but ends with a "
 583               "barrier instruction!", MBB);
 584      }
 585      if (!Cond.empty()) {
 586        report("MBB exits via unconditional fall-through but has a condition!",
 587               MBB);
 588      }
 589    } else if (TBB && !FBB && Cond.empty()) {
 590      // Block unconditionally branches somewhere.
 591      if (MBB->succ_size() != 1+LandingPadSuccs.size()) {
 592        report("MBB exits via unconditional branch but doesn't have "
 593               "exactly one CFG successor!", MBB);
 594      } else if (!MBB->isSuccessor(TBB)) {
 595        report("MBB exits via unconditional branch but the CFG "
 596               "successor doesn't match the actual successor!", MBB);
 597      }
 598      if (MBB->empty()) {
 599        report("MBB exits via unconditional branch but doesn't contain "
 600               "any instructions!", MBB);
 601      } else if (!getBundleStart(&MBB->back())->isBarrier()) {
 602        report("MBB exits via unconditional branch but doesn't end with a "
 603               "barrier instruction!", MBB);
 604      } else if (!getBundleStart(&MBB->back())->isTerminator()) {
 605        report("MBB exits via unconditional branch but the branch isn't a "
 606               "terminator instruction!", MBB);
 607      }
 608    } else if (TBB && !FBB && !Cond.empty()) {
 609      // Block conditionally branches somewhere, otherwise falls through.
 610      MachineFunction::const_iterator MBBI = MBB;
 611      ++MBBI;
 612      if (MBBI == MF->end()) {
 613        report("MBB conditionally falls through out of function!", MBB);
 614      } else if (MBB->succ_size() == 1) {
 615        // A conditional branch with only one successor is weird, but allowed.
 616        if (&*MBBI != TBB)
 617          report("MBB exits via conditional branch/fall-through but only has "
 618                 "one CFG successor!", MBB);
 619        else if (TBB != *MBB->succ_begin())
 620          report("MBB exits via conditional branch/fall-through but the CFG "
 621                 "successor don't match the actual successor!", MBB);
 622      } else if (MBB->succ_size() != 2) {
 623        report("MBB exits via conditional branch/fall-through but doesn't have "
 624               "exactly two CFG successors!", MBB);
 625      } else if (!matchPair(MBB->succ_begin(), TBB, MBBI)) {
 626        report("MBB exits via conditional branch/fall-through but the CFG "
 627               "successors don't match the actual successors!", MBB);
 628      }
 629      if (MBB->empty()) {
 630        report("MBB exits via conditional branch/fall-through but doesn't "
 631               "contain any instructions!", MBB);
 632      } else if (getBundleStart(&MBB->back())->isBarrier()) {
 633        report("MBB exits via conditional branch/fall-through but ends with a "
 634               "barrier instruction!", MBB);
 635      } else if (!getBundleStart(&MBB->back())->isTerminator()) {
 636        report("MBB exits via conditional branch/fall-through but the branch "
 637               "isn't a terminator instruction!", MBB);
 638      }
 639    } else if (TBB && FBB) {
 640      // Block conditionally branches somewhere, otherwise branches
 641      // somewhere else.
 642      if (MBB->succ_size() == 1) {
 643        // A conditional branch with only one successor is weird, but allowed.
 644        if (FBB != TBB)
 645          report("MBB exits via conditional branch/branch through but only has "
 646                 "one CFG successor!", MBB);
 647        else if (TBB != *MBB->succ_begin())
 648          report("MBB exits via conditional branch/branch through but the CFG "
 649                 "successor don't match the actual successor!", MBB);
 650      } else if (MBB->succ_size() != 2) {
 651        report("MBB exits via conditional branch/branch but doesn't have "
 652               "exactly two CFG successors!", MBB);
 653      } else if (!matchPair(MBB->succ_begin(), TBB, FBB)) {
 654        report("MBB exits via conditional branch/branch but the CFG "
 655               "successors don't match the actual successors!", MBB);
 656      }
 657      if (MBB->empty()) {
 658        report("MBB exits via conditional branch/branch but doesn't "
 659               "contain any instructions!", MBB);
 660      } else if (!getBundleStart(&MBB->back())->isBarrier()) {
 661        report("MBB exits via conditional branch/branch but doesn't end with a "
 662               "barrier instruction!", MBB);
 663      } else if (!getBundleStart(&MBB->back())->isTerminator()) {
 664        report("MBB exits via conditional branch/branch but the branch "
 665               "isn't a terminator instruction!", MBB);
 666      }
 667      if (Cond.empty()) {
 668        report("MBB exits via conditinal branch/branch but there's no "
 669               "condition!", MBB);
 670      }
 671    } else {
 672      report("AnalyzeBranch returned invalid data!", MBB);
 673    }
 674  }
 675
 676  regsLive.clear();
 677  for (MachineBasicBlock::livein_iterator I = MBB->livein_begin(),
 678         E = MBB->livein_end(); I != E; ++I) {
 679    if (!TargetRegisterInfo::isPhysicalRegister(*I)) {
 680      report("MBB live-in list contains non-physical register", MBB);
 681      continue;
 682    }
 683    for (MCSubRegIterator SubRegs(*I, TRI, /*IncludeSelf=*/true);
 684         SubRegs.isValid(); ++SubRegs)
 685      regsLive.insert(*SubRegs);
 686  }
 687  regsLiveInButUnused = regsLive;
 688
 689  const MachineFrameInfo *MFI = MF->getFrameInfo();
 690  assert(MFI && "Function has no frame info");
 691  BitVector PR = MFI->getPristineRegs(MBB);
 692  for (int I = PR.find_first(); I>0; I = PR.find_next(I)) {
 693    for (MCSubRegIterator SubRegs(I, TRI, /*IncludeSelf=*/true);
 694         SubRegs.isValid(); ++SubRegs)
 695      regsLive.insert(*SubRegs);
 696  }
 697
 698  regsKilled.clear();
 699  regsDefined.clear();
 700
 701  if (Indexes)
 702    lastIndex = Indexes->getMBBStartIdx(MBB);
 703}
 704
 705// This function gets called for all bundle headers, including normal
 706// stand-alone unbundled instructions.
 707void MachineVerifier::visitMachineBundleBefore(const MachineInstr *MI) {
 708  if (Indexes && Indexes->hasIndex(MI)) {
 709    SlotIndex idx = Indexes->getInstructionIndex(MI);
 710    if (!(idx > lastIndex)) {
 711      report("Instruction index out of order", MI);
 712      *OS << "Last instruction was at " << lastIndex << '\n';
 713    }
 714    lastIndex = idx;
 715  }
 716
 717  // Ensure non-terminators don't follow terminators.
 718  // Ignore predicated terminators formed by if conversion.
 719  // FIXME: If conversion shouldn't need to violate this rule.
 720  if (MI->isTerminator() && !TII->isPredicated(MI)) {
 721    if (!FirstTerminator)
 722      FirstTerminator = MI;
 723  } else if (FirstTerminator) {
 724    report("Non-terminator instruction after the first terminator", MI);
 725    *OS << "First terminator was:\t" << *FirstTerminator;
 726  }
 727}
 728
 729// The operands on an INLINEASM instruction must follow a template.
 730// Verify that the flag operands make sense.
 731void MachineVerifier::verifyInlineAsm(const MachineInstr *MI) {
 732  // The first two operands on INLINEASM are the asm string and global flags.
 733  if (MI->getNumOperands() < 2) {
 734    report("Too few operands on inline asm", MI);
 735    return;
 736  }
 737  if (!MI->getOperand(0).isSymbol())
 738    report("Asm string must be an external symbol", MI);
 739  if (!MI->getOperand(1).isImm())
 740    report("Asm flags must be an immediate", MI);
 741  // Allowed flags are Extra_HasSideEffects = 1, Extra_IsAlignStack = 2,
 742  // Extra_AsmDialect = 4, Extra_MayLoad = 8, and Extra_MayStore = 16.
 743  if (!isUInt<5>(MI->getOperand(1).getImm()))
 744    report("Unknown asm flags", &MI->getOperand(1), 1);
 745
 746  assert(InlineAsm::MIOp_FirstOperand == 2 && "Asm format changed");
 747
 748  unsigned OpNo = InlineAsm::MIOp_FirstOperand;
 749  unsigned NumOps;
 750  for (unsigned e = MI->getNumOperands(); OpNo < e; OpNo += NumOps) {
 751    const MachineOperand &MO = MI->getOperand(OpNo);
 752    // There may be implicit ops after the fixed operands.
 753    if (!MO.isImm())
 754      break;
 755    NumOps = 1 + InlineAsm::getNumOperandRegisters(MO.getImm());
 756  }
 757
 758  if (OpNo > MI->getNumOperands())
 759    report("Missing operands in last group", MI);
 760
 761  // An optional MDNode follows the groups.
 762  if (OpNo < MI->getNumOperands() && MI->getOperand(OpNo).isMetadata())
 763    ++OpNo;
 764
 765  // All trailing operands must be implicit registers.
 766  for (unsigned e = MI->getNumOperands(); OpNo < e; ++OpNo) {
 767    const MachineOperand &MO = MI->getOperand(OpNo);
 768    if (!MO.isReg() || !MO.isImplicit())
 769      report("Expected implicit register after groups", &MO, OpNo);
 770  }
 771}
 772
 773void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
 774  const MCInstrDesc &MCID = MI->getDesc();
 775  if (MI->getNumOperands() < MCID.getNumOperands()) {
 776    report("Too few operands", MI);
 777    *OS << MCID.getNumOperands() << " operands expected, but "
 778        << MI->getNumOperands() << " given.\n";
 779  }
 780
 781  // Check the tied operands.
 782  if (MI->isInlineAsm())
 783    verifyInlineAsm(MI);
 784
 785  // Check the MachineMemOperands for basic consistency.
 786  for (MachineInstr::mmo_iterator I = MI->memoperands_begin(),
 787       E = MI->memoperands_end(); I != E; ++I) {
 788    if ((*I)->isLoad() && !MI->mayLoad())
 789      report("Missing mayLoad flag", MI);
 790    if ((*I)->isStore() && !MI->mayStore())
 791      report("Missing mayStore flag", MI);
 792  }
 793
 794  // Debug values must not have a slot index.
 795  // Other instructions must have one, unless they are inside a bundle.
 796  if (LiveInts) {
 797    bool mapped = !LiveInts->isNotInMIMap(MI);
 798    if (MI->isDebugValue()) {
 799      if (mapped)
 800        report("Debug instruction has a slot index", MI);
 801    } else if (MI->isInsideBundle()) {
 802      if (mapped)
 803        report("Instruction inside bundle has a slot index", MI);
 804    } else {
 805      if (!mapped)
 806        report("Missing slot index", MI);
 807    }
 808  }
 809
 810  StringRef ErrorInfo;
 811  if (!TII->verifyInstruction(MI, ErrorInfo))
 812    report(ErrorInfo.data(), MI);
 813}
 814
 815void
 816MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
 817  const MachineInstr *MI = MO->getParent();
 818  const MCInstrDesc &MCID = MI->getDesc();
 819
 820  // The first MCID.NumDefs operands must be explicit register defines
 821  if (MONum < MCID.getNumDefs()) {
 822    const MCOperandInfo &MCOI = MCID.OpInfo[MONum];
 823    if (!MO->isReg())
 824      report("Explicit definition must be a register", MO, MONum);
 825    else if (!MO->isDef() && !MCOI.isOptionalDef())
 826      report("Explicit definition marked as use", MO, MONum);
 827    else if (MO->isImplicit())
 828      report("Explicit definition marked as implicit", MO, MONum);
 829  } else if (MONum < MCID.getNumOperands()) {
 830    const MCOperandInfo &MCOI = MCID.OpInfo[MONum];
 831    // Don't check if it's the last operand in a variadic instruction. See,
 832    // e.g., LDM_RET in the arm back end.
 833    if (MO->isReg() &&
 834        !(MI->isVariadic() && MONum == MCID.getNumOperands()-1)) {
 835      if (MO->isDef() && !MCOI.isOptionalDef())
 836        report("Explicit operand marked as def", MO, MONum);
 837      if (MO->isImplicit())
 838        report("Explicit operand marked as implicit", MO, MONum);
 839    }
 840
 841    int TiedTo = MCID.getOperandConstraint(MONum, MCOI::TIED_TO);
 842    if (TiedTo != -1) {
 843      if (!MO->isReg())
 844        report("Tied use must be a register", MO, MONum);
 845      else if (!MO->isTied())
 846        report("Operand should be tied", MO, MONum);
 847      else if (unsigned(TiedTo) != MI->findTiedOperandIdx(MONum))
 848        report("Tied def doesn't match MCInstrDesc", MO, MONum);
 849    } else if (MO->isReg() && MO->isTied())
 850      report("Explicit operand should not be tied", MO, MONum);
 851  } else {
 852    // ARM adds %reg0 operands to indicate predicates. We'll allow that.
 853    if (MO->isReg() && !MO->isImplicit() && !MI->isVariadic() && MO->getReg())
 854      report("Extra explicit operand on non-variadic instruction", MO, MONum);
 855  }
 856
 857  switch (MO->getType()) {
 858  case MachineOperand::MO_Register: {
 859    const unsigned Reg = MO->getReg();
 860    if (!Reg)
 861      return;
 862    if (MRI->tracksLiveness() && !MI->isDebugValue())
 863      checkLiveness(MO, MONum);
 864
 865    // Verify the consistency of tied operands.
 866    if (MO->isTied()) {
 867      unsigned OtherIdx = MI->findTiedOperandIdx(MONum);
 868      const MachineOperand &OtherMO = MI->getOperand(OtherIdx);
 869      if (!OtherMO.isReg())
 870        report("Must be tied to a register", MO, MONum);
 871      if (!OtherMO.isTied())
 872        report("Missing tie flags on tied operand", MO, MONum);
 873      if (MI->findTiedOperandIdx(OtherIdx) != MONum)
 874        report("Inconsistent tie links", MO, MONum);
 875      if (MONum < MCID.getNumDefs()) {
 876        if (OtherIdx < MCID.getNumOperands()) {
 877          if (-1 == MCID.getOperandConstraint(OtherIdx, MCOI::TIED_TO))
 878            report("Explicit def tied to explicit use without tie constraint",
 879                   MO, MONum);
 880        } else {
 881          if (!OtherMO.isImplicit())
 882            report("Explicit def should be tied to implicit use", MO, MONum);
 883        }
 884      }
 885    }
 886
 887    // Verify two-address constraints after leaving SSA form.
 888    unsigned DefIdx;
 889    if (!MRI->isSSA() && MO->isUse() &&
 890        MI->isRegTiedToDefOperand(MONum, &DefIdx) &&
 891        Reg != MI->getOperand(DefIdx).getReg())
 892      report("Two-address instruction operands must be identical", MO, MONum);
 893
 894    // Check register classes.
 895    if (MONum < MCID.getNumOperands() && !MO->isImplicit()) {
 896      unsigned SubIdx = MO->getSubReg();
 897
 898      if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
 899        if (SubIdx) {
 900          report("Illegal subregister index for physical register", MO, MONum);
 901          return;
 902        }
 903        if (const TargetRegisterClass *DRC =
 904              TII->getRegClass(MCID, MONum, TRI, *MF)) {
 905          if (!DRC->contains(Reg)) {
 906            report("Illegal physical register for instruction", MO, MONum);
 907            *OS << TRI->getName(Reg) << " is not a "
 908                << DRC->getName() << " register.\n";
 909          }
 910        }
 911      } else {
 912        // Virtual register.
 913        const TargetRegisterClass *RC = MRI->getRegClass(Reg);
 914        if (SubIdx) {
 915          const TargetRegisterClass *SRC =
 916            TRI->getSubClassWithSubReg(RC, SubIdx);
 917          if (!SRC) {
 918            report("Invalid subregister index for virtual register", MO, MONum);
 919            *OS << "Register class " << RC->getName()
 920                << " does not support subreg index " << SubIdx << "\n";
 921            return;
 922          }
 923          if (RC != SRC) {
 924            report("Invalid register class for subregister index", MO, MONum);
 925            *OS << "Register class " << RC->getName()
 926                << " does not fully support subreg index " << SubIdx << "\n";
 927            return;
 928          }
 929        }
 930        if (const TargetRegisterClass *DRC =
 931              TII->getRegClass(MCID, MONum, TRI, *MF)) {
 932          if (SubIdx) {
 933            const TargetRegisterClass *SuperRC =
 934              TRI->getLargestLegalSuperClass(RC);
 935            if (!SuperRC) {
 936              report("No largest legal super class exists.", MO, MONum);
 937              return;
 938            }
 939            DRC = TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx);
 940            if (!DRC) {
 941              report("No matching super-reg register class.", MO, MONum);
 942              return;
 943            }
 944          }
 945          if (!RC->hasSuperClassEq(DRC)) {
 946            report("Illegal virtual register for instruction", MO, MONum);
 947            *OS << "Expected a " << DRC->getName() << " register, but got a "
 948                << RC->getName() << " register\n";
 949          }
 950        }
 951      }
 952    }
 953    break;
 954  }
 955
 956  case MachineOperand::MO_RegisterMask:
 957    regMasks.push_back(MO->getRegMask());
 958    break;
 959
 960  case MachineOperand::MO_MachineBasicBlock:
 961    if (MI->isPHI() && !MO->getMBB()->isSuccessor(MI->getParent()))
 962      report("PHI operand is not in the CFG", MO, MONum);
 963    break;
 964
 965  case MachineOperand::MO_FrameIndex:
 966    if (LiveStks && LiveStks->hasInterval(MO->getIndex()) &&
 967        LiveInts && !LiveInts->isNotInMIMap(MI)) {
 968      LiveInterval &LI = LiveStks->getInterval(MO->getIndex());
 969      SlotIndex Idx = LiveInts->getInstructionIndex(MI);
 970      if (MI->mayLoad() && !LI.liveAt(Idx.getRegSlot(true))) {
 971        report("Instruction loads from dead spill slot", MO, MONum);
 972        *OS << "Live stack: " << LI << '\n';
 973      }
 974      if (MI->mayStore() && !LI.liveAt(Idx.getRegSlot())) {
 975        report("Instruction stores to dead spill slot", MO, MONum);
 976        *OS << "Live stack: " << LI << '\n';
 977      }
 978    }
 979    break;
 980
 981  default:
 982    break;
 983  }
 984}
 985
 986void MachineVerifier::checkLiveness(const MachineOperand *MO, unsigned MONum) {
 987  const MachineInstr *MI = MO->getParent();
 988  const unsigned Reg = MO->getReg();
 989
 990  // Both use and def operands can read a register.
 991  if (MO->readsReg()) {
 992    regsLiveInButUnused.erase(Reg);
 993
 994    if (MO->isKill())
 995      addRegWithSubRegs(regsKilled, Reg);
 996
 997    // Check that LiveVars knows this kill.
 998    if (LiveVars && TargetRegisterInfo::isVirtualRegister(Reg) &&
 999        MO->isKill()) {
1000      LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
1001      if (std::find(VI.Kills.begin(), VI.Kills.end(), MI) == VI.Kills.end())
1002        report("Kill missing from LiveVariables", MO, MONum);
1003    }
1004
1005    // Check LiveInts liveness and kill.
1006    if (LiveInts && !LiveInts->isNotInMIMap(MI)) {
1007      SlotIndex UseIdx = LiveInts->getInstructionIndex(MI);
1008      // Check the cached regunit intervals.
1009      if (TargetRegisterInfo::isPhysicalRegister(Reg) && !isReserved(Reg)) {
1010        for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units) {
1011          if (const LiveRange *LR = LiveInts->getCachedRegUnit(*Units)) {
1012            LiveQueryResult LRQ = LR->Query(UseIdx);
1013            if (!LRQ.valueIn()) {
1014              report("No live segment at use", MO, MONum);
1015              *OS << UseIdx << " is not live in " << PrintRegUnit(*Units, TRI)
1016                  << ' ' << *LR << '\n';
1017            }
1018            if (MO->isKill() && !LRQ.isKill()) {
1019              report("Live range continues after kill flag", MO, MONum);
1020              *OS << PrintRegUnit(*Units, TRI) << ' ' << *LR << '\n';
1021            }
1022          }
1023        }
1024      }
1025
1026      if (TargetRegisterInfo::isVirtualRegister(Reg)) {
1027        if (LiveInts->hasInterval(Reg)) {
1028          // This is a virtual register interval.
1029          const LiveInterval &LI = LiveInts->getInterval(Reg);
1030          LiveQueryResult LRQ = LI.Query(UseIdx);
1031          if (!LRQ.valueIn()) {
1032            report("No live segment at use", MO, MONum);
1033            *OS << UseIdx << " is not live in " << LI << '\n';
1034          }
1035          // Check for extra kill flags.
1036          // Note that we allow missing kill flags for now.
1037          if (MO->isKill() && !LRQ.isKill()) {
1038            report("Live range continues after kill flag", MO, MONum);
1039            *OS << "Live range: " << LI << '\n';
1040          }
1041        } else {
1042          report("Virtual register has no live interval", MO, MONum);
1043        }
1044      }
1045    }
1046
1047    // Use of a dead register.
1048    if (!regsLive.count(Reg)) {
1049      if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
1050        // Reserved registers may be used even when 'dead'.
1051        if (!isReserved(Reg))
1052          report("Using an undefined physical register", MO, MONum);
1053      } else if (MRI->def_empty(Reg)) {
1054        report("Reading virtual register without a def", MO, MONum);
1055      } else {
1056        BBInfo &MInfo = MBBInfoMap[MI->getParent()];
1057        // We don't know which virtual registers are live in, so only complain
1058        // if vreg was killed in this MBB. Otherwise keep track of vregs that
1059        // must be live in. PHI instructions are handled separately.
1060        if (MInfo.regsKilled.count(Reg))
1061          report("Using a killed virtual register", MO, MONum);
1062        else if (!MI->isPHI())
1063          MInfo.vregsLiveIn.insert(std::make_pair(Reg, MI));
1064      }
1065    }
1066  }
1067
1068  if (MO->isDef()) {
1069    // Register defined.
1070    // TODO: verify that earlyclobber ops are not used.
1071    if (MO->isDead())
1072      addRegWithSubRegs(regsDead, Reg);
1073    else
1074      addRegWithSubRegs(regsDefined, Reg);
1075
1076    // Verify SSA form.
1077    if (MRI->isSSA() && TargetRegisterInfo::isVirtualRegister(Reg) &&
1078        llvm::next(MRI->def_begin(Reg)) != MRI->def_end())
1079      report("Multiple virtual register defs in SSA form", MO, MONum);
1080
1081    // Check LiveInts for a live segment, but only for virtual registers.
1082    if (LiveInts && TargetRegisterInfo::isVirtualRegister(Reg) &&
1083        !LiveInts->isNotInMIMap(MI)) {
1084      SlotIndex DefIdx = LiveInts->getInstructionIndex(MI);
1085      DefIdx = DefIdx.getRegSlot(MO->isEarlyClobber());
1086      if (LiveInts->hasInterval(Reg)) {
1087        const LiveInterval &LI = LiveInts->getInterval(Reg);
1088        if (const VNInfo *VNI = LI.getVNInfoAt(DefIdx)) {
1089          assert(VNI && "NULL valno is not allowed");
1090          if (VNI->def != DefIdx) {
1091            report("Inconsistent valno->def", MO, MONum);
1092            *OS << "Valno " << VNI->id << " is not defined at "
1093              << DefIdx << " in " << LI << '\n';
1094          }
1095        } else {
1096          report("No live segment at def", MO, MONum);
1097          *OS << DefIdx << " is not live in " << LI << '\n';
1098        }
1099        // Check that, if the dead def flag is present, LiveInts agree.
1100        if (MO->isDead()) {
1101          LiveQueryResult LRQ = LI.Query(DefIdx);
1102          if (!LRQ.isDeadDef()) {
1103            report("Live range continues after dead def flag", MO, MONum);
1104            *OS << "Live range: " << LI << '\n';
1105          }
1106        }
1107      } else {
1108        report("Virtual register has no Live interval", MO, MONum);
1109      }
1110    }
1111  }
1112}
1113
1114void MachineVerifier::visitMachineInstrAfter(const MachineInstr *MI) {
1115}
1116
1117// This function gets called after visiting all instructions in a bundle. The
1118// argument points to the bundle header.
1119// Normal stand-alone instructions are also considered 'bundles', and this
1120// function is called for all of them.
1121void MachineVerifier::visitMachineBundleAfter(const MachineInstr *MI) {
1122  BBInfo &MInfo = MBBInfoMap[MI->getParent()];
1123  set_union(MInfo.regsKilled, regsKilled);
1124  set_subtract(regsLive, regsKilled); regsKilled.clear();
1125  // Kill any masked registers.
1126  while (!regMasks.empty()) {
1127    const uint32_t *Mask = regMasks.pop_back_val();
1128    for (RegSet::iterator I = regsLive.begin(), E = regsLive.end(); I != E; ++I)
1129      if (TargetRegisterInfo::isPhysicalRegister(*I) &&
1130          MachineOperand::clobbersPhysReg(Mask, *I))
1131        regsDead.push_back(*I);
1132  }
1133  set_subtract(regsLive, regsDead);   regsDead.clear();
1134  set_union(regsLive, regsDefined);   regsDefined.clear();
1135}
1136
1137void
1138MachineVerifier::visitMachineBasicBlockAfter(const MachineBasicBlock *MBB) {
1139  MBBInfoMap[MBB].regsLiveOut = regsLive;
1140  regsLive.clear();
1141
1142  if (Indexes) {
1143    SlotIndex stop = Indexes->getMBBEndIdx(MBB);
1144    if (!(stop > lastIndex)) {
1145      report("Block ends before last instruction index", MBB);
1146      *OS << "Block ends at " << stop
1147          << " last instruction was at " << lastIndex << '\n';
1148    }
1149    lastIndex = stop;
1150  }
1151}
1152
1153// Calculate the largest possible vregsPassed sets. These are the registers that
1154// can pass through an MBB live, but may not be live every time. It is assumed
1155// that all vregsPassed sets are empty before the call.
1156void MachineVerifier::calcRegsPassed() {
1157  // First push live-out regs to successors' vregsPassed. Remember the MBBs that
1158  // have any vregsPassed.
1159  SmallPtrSet<const MachineBasicBlock*, 8> todo;
1160  for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
1161       MFI != MFE; ++MFI) {
1162    const MachineBasicBlock &MBB(*MFI);
1163    BBInfo &MInfo = MBBInfoMap[&MBB];
1164    if (!MInfo.reachable)
1165      continue;
1166    for (MachineBasicBlock::const_succ_iterator SuI = MBB.succ_begin(),
1167           SuE = MBB.succ_end(); SuI != SuE; ++SuI) {
1168      BBInfo &SInfo = MBBInfoMap[*SuI];
1169      if (SInfo.addPassed(MInfo.regsLiveOut))
1170        todo.insert(*SuI);
1171    }
1172  }
1173
1174  // Iteratively push vregsPassed to successors. This will converge to the same
1175  // final state regardless of DenseSet iteration order.
1176  while (!todo.empty()) {
1177    const MachineBasicBlock *MBB = *todo.begin();
1178    todo.erase(MBB);
1179    BBInfo &MInfo = MBBInfoMap[MBB];
1180    for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
1181           SuE = MBB->succ_end(); SuI != SuE; ++SuI) {
1182      if (*SuI == MBB)
1183        continue;
1184      BBInfo &SInfo = MBBInfoMap[*SuI];
1185      if (SInfo.addPassed(MInfo.vregsPassed))
1186        todo.insert(*SuI);
1187    }
1188  }
1189}
1190
1191// Calculate the set of virtual registers that must be passed through each basic
1192// block in order to satisfy the requirements of successor blocks. This is very
1193// similar to calcRegsPassed, only backwards.
1194void MachineVerifier::calcRegsRequired() {
1195  // First push live-in regs to predecessors' vregsRequired.
1196  SmallPtrSet<const MachineBasicBlock*, 8> todo;
1197  for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
1198       MFI != MFE; ++MFI) {
1199    const MachineBasicBlock &MBB(*MFI);
1200    BBInfo &MInfo = MBBInfoMap[&MBB];
1201    for (MachineBasicBlock::const_pred_iterator PrI = MBB.pred_begin(),
1202           PrE = MBB.pred_end(); PrI != PrE; ++PrI) {
1203      BBInfo &PInfo = MBBInfoMap[*PrI];
1204      if (PInfo.addRequired(MInfo.vregsLiveIn))
1205        todo.insert(*PrI);
1206    }
1207  }
1208
1209  // Iteratively push vregsRequired to predecessors. This will converge to the
1210  // same final state regardless of DenseSet iteration order.
1211  while (!todo.empty()) {
1212    const MachineBasicBlock *MBB = *todo.begin();
1213    todo.erase(MBB);
1214    BBInfo &MInfo = MBBInfoMap[MBB];
1215    for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
1216           PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
1217      if (*PrI == MBB)
1218        continue;
1219      BBInfo &SInfo = MBBInfoMap[*PrI];
1220      if (SInfo.addRequired(MInfo.vregsRequired))
1221        todo.insert(*PrI);
1222    }
1223  }
1224}
1225
1226// Check PHI instructions at the beginning of MBB. It is assumed that
1227// calcRegsPassed has been run so BBInfo::isLiveOut is valid.
1228void MachineVerifier::checkPHIOps(const MachineBasicBlock *MBB) {
1229  SmallPtrSet<const MachineBasicBlock*, 8> seen;
1230  for (MachineBasicBlock::const_iterator BBI = MBB->begin(), BBE = MBB->end();
1231       BBI != BBE && BBI->isPHI(); ++BBI) {
1232    seen.clear();
1233
1234    for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) {
1235      unsigned Reg = BBI->getOperand(i).getReg();
1236      const MachineBasicBlock *Pre = BBI->getOperand(i + 1).getMBB();
1237      if (!Pre->isSuccessor(MBB))
1238        continue;
1239      seen.insert(Pre);
1240      BBInfo &PrInfo = MBBInfoMap[Pre];
1241      if (PrInfo.reachable && !PrInfo.isLiveOut(Reg))
1242        report("PHI operand is not live-out from predecessor",
1243               &BBI->getOperand(i), i);
1244    }
1245
1246    // Did we see all predecessors?
1247    for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
1248           PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
1249      if (!seen.count(*PrI)) {
1250        report("Missing PHI operand", BBI);
1251        *OS << "BB#" << (*PrI)->getNumber()
1252            << " is a predecessor according to the CFG.\n";
1253      }
1254    }
1255  }
1256}
1257
1258void MachineVerifier::visitMachineFunctionAfter() {
1259  calcRegsPassed();
1260
1261  for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
1262       MFI != MFE; ++MFI) {
1263    BBInfo &MInfo = MBBInfoMap[MFI];
1264
1265    // Skip unreachable MBBs.
1266    if (!MInfo.reachable)
1267      continue;
1268
1269    checkPHIOps(MFI);
1270  }
1271
1272  // Now check liveness info if available
1273  calcRegsRequired();
1274
1275  // Check for killed virtual registers that should be live out.
1276  for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
1277       MFI != MFE; ++MFI) {
1278    BBInfo &MInfo = MBBInfoMap[MFI];
1279    for (RegSet::iterator
1280         I = MInfo.vregsRequired.begin(), E = MInfo.vregsRequired.end(); I != E;
1281         ++I)
1282      if (MInfo.regsKilled.count(*I)) {
1283        report("Virtual register killed in block, but needed live out.", MFI);
1284        *OS << "Virtual register " << PrintReg(*I)
1285            << " is used after the block.\n";
1286      }
1287  }
1288
1289  if (!MF->empty()) {
1290    BBInfo &MInfo = MBBInfoMap[&MF->front()];
1291    for (RegSet::iterator
1292         I = MInfo.vregsRequired.begin(), E = MInfo.vregsRequired.end(); I != E;
1293         ++I)
1294      report("Virtual register def doesn't dominate all uses.",
1295             MRI->getVRegDef(*I));
1296  }
1297
1298  if (LiveVars)
1299    verifyLiveVariables();
1300  if (LiveInts)
1301    verifyLiveIntervals();
1302}
1303
1304void MachineVerifier::verifyLiveVariables() {
1305  assert(LiveVars && "Don't call verifyLiveVariables without LiveVars");
1306  for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
1307    unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
1308    LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
1309    for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
1310         MFI != MFE; ++MFI) {
1311      BBInfo &MInfo = MBBInfoMap[MFI];
1312
1313      // Our vregsRequired should be identical to LiveVariables' AliveBlocks
1314      if (MInfo.vregsRequired.count(Reg)) {
1315        if (!VI.AliveBlocks.test(MFI->getNumber())) {
1316          report("LiveVariables: Block missing from AliveBlocks", MFI);
1317          *OS << "Virtual register " << PrintReg(Reg)
1318              << " must be live through the block.\n";
1319        }
1320      } else {
1321        if (VI.AliveBlocks.test(MFI->getNumber())) {
1322          report("LiveVariables: Block should not be in AliveBlocks", MFI);
1323          *OS << "Virtual register " << PrintReg(Reg)
1324              << " is not needed live through the block.\n";
1325        }
1326      }
1327    }
1328  }
1329}
1330
1331void MachineVerifier::verifyLiveIntervals() {
1332  assert(LiveInts && "Don't call verifyLiveIntervals without LiveInts");
1333  for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
1334    unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
1335
1336    // Spilling and splitting may leave unused registers around. Skip them.
1337    if (MRI->reg_nodbg_empty(Reg))
1338      continue;
1339
1340    if (!LiveInts->hasInterval(Reg)) {
1341      report("Missing live interval for virtual register", MF);
1342      *OS << PrintReg(Reg, TRI) << " still has defs or uses\n";
1343      continue;
1344    }
1345
1346    const LiveInterval &LI = LiveInts->getInterval(Reg);
1347    assert(Reg == LI.reg && "Invalid reg to interval mapping");
1348    verifyLiveInterval(LI);
1349  }
1350
1351  // Verify all the cached regunit intervals.
1352  for (unsigned i = 0, e = TRI->getNumRegUnits(); i != e; ++i)
1353    if (const LiveRange *LR = LiveInts->getCachedRegUnit(i))
1354      verifyLiveRange(*LR, i);
1355}
1356
1357void MachineVerifier::verifyLiveRangeValue(const LiveRange &LR,
1358                 

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