/3rd_party/llvm/lib/Target/Alpha/AlphaInstrInfo.h

https://code.google.com/p/softart/ · C++ Header · 85 lines · 47 code · 14 blank · 24 comment · 0 complexity · d78fbe541080cc69597278c31e5e978d MD5 · raw file

  1. //===- AlphaInstrInfo.h - Alpha Instruction Information ---------*- C++ -*-===//
  2. //
  3. // The LLVM Compiler Infrastructure
  4. //
  5. // This file is distributed under the University of Illinois Open Source
  6. // License. See LICENSE.TXT for details.
  7. //
  8. //===----------------------------------------------------------------------===//
  9. //
  10. // This file contains the Alpha implementation of the TargetInstrInfo class.
  11. //
  12. //===----------------------------------------------------------------------===//
  13. #ifndef ALPHAINSTRUCTIONINFO_H
  14. #define ALPHAINSTRUCTIONINFO_H
  15. #include "llvm/Target/TargetInstrInfo.h"
  16. #include "AlphaRegisterInfo.h"
  17. #define GET_INSTRINFO_HEADER
  18. #include "AlphaGenInstrInfo.inc"
  19. namespace llvm {
  20. class AlphaInstrInfo : public AlphaGenInstrInfo {
  21. const AlphaRegisterInfo RI;
  22. public:
  23. AlphaInstrInfo();
  24. /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
  25. /// such, whenever a client has an instance of instruction info, it should
  26. /// always be able to get register info as well (through this method).
  27. ///
  28. virtual const AlphaRegisterInfo &getRegisterInfo() const { return RI; }
  29. virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
  30. int &FrameIndex) const;
  31. virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
  32. int &FrameIndex) const;
  33. virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
  34. MachineBasicBlock *FBB,
  35. const SmallVectorImpl<MachineOperand> &Cond,
  36. DebugLoc DL) const;
  37. virtual void copyPhysReg(MachineBasicBlock &MBB,
  38. MachineBasicBlock::iterator MI, DebugLoc DL,
  39. unsigned DestReg, unsigned SrcReg,
  40. bool KillSrc) const;
  41. virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
  42. MachineBasicBlock::iterator MBBI,
  43. unsigned SrcReg, bool isKill, int FrameIndex,
  44. const TargetRegisterClass *RC,
  45. const TargetRegisterInfo *TRI) const;
  46. virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
  47. MachineBasicBlock::iterator MBBI,
  48. unsigned DestReg, int FrameIndex,
  49. const TargetRegisterClass *RC,
  50. const TargetRegisterInfo *TRI) const;
  51. bool AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
  52. MachineBasicBlock *&FBB,
  53. SmallVectorImpl<MachineOperand> &Cond,
  54. bool AllowModify) const;
  55. unsigned RemoveBranch(MachineBasicBlock &MBB) const;
  56. void insertNoop(MachineBasicBlock &MBB,
  57. MachineBasicBlock::iterator MI) const;
  58. bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
  59. /// getGlobalBaseReg - Return a virtual register initialized with the
  60. /// the global base register value. Output instructions required to
  61. /// initialize the register in the function entry block, if necessary.
  62. ///
  63. unsigned getGlobalBaseReg(MachineFunction *MF) const;
  64. /// getGlobalRetAddr - Return a virtual register initialized with the
  65. /// the global return address register value. Output instructions required to
  66. /// initialize the register in the function entry block, if necessary.
  67. ///
  68. unsigned getGlobalRetAddr(MachineFunction *MF) const;
  69. };
  70. }
  71. #endif