/3rd_party/llvm/lib/Target/ARM/Thumb2InstrInfo.h

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  1. //===-- Thumb2InstrInfo.h - Thumb-2 Instruction Information -----*- C++ -*-===//
  2. //
  3. // The LLVM Compiler Infrastructure
  4. //
  5. // This file is distributed under the University of Illinois Open Source
  6. // License. See LICENSE.TXT for details.
  7. //
  8. //===----------------------------------------------------------------------===//
  9. //
  10. // This file contains the Thumb-2 implementation of the TargetInstrInfo class.
  11. //
  12. //===----------------------------------------------------------------------===//
  13. #ifndef THUMB2INSTRUCTIONINFO_H
  14. #define THUMB2INSTRUCTIONINFO_H
  15. #include "ARM.h"
  16. #include "ARMBaseInstrInfo.h"
  17. #include "Thumb2RegisterInfo.h"
  18. namespace llvm {
  19. class ARMSubtarget;
  20. class ScheduleHazardRecognizer;
  21. class Thumb2InstrInfo : public ARMBaseInstrInfo {
  22. Thumb2RegisterInfo RI;
  23. public:
  24. explicit Thumb2InstrInfo(const ARMSubtarget &STI);
  25. /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
  26. void getNoopForMachoTarget(MCInst &NopInst) const;
  27. // Return the non-pre/post incrementing version of 'Opc'. Return 0
  28. // if there is not such an opcode.
  29. unsigned getUnindexedOpcode(unsigned Opc) const;
  30. void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
  31. MachineBasicBlock *NewDest) const;
  32. bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,
  33. MachineBasicBlock::iterator MBBI) const;
  34. void copyPhysReg(MachineBasicBlock &MBB,
  35. MachineBasicBlock::iterator I, DebugLoc DL,
  36. unsigned DestReg, unsigned SrcReg,
  37. bool KillSrc) const;
  38. void storeRegToStackSlot(MachineBasicBlock &MBB,
  39. MachineBasicBlock::iterator MBBI,
  40. unsigned SrcReg, bool isKill, int FrameIndex,
  41. const TargetRegisterClass *RC,
  42. const TargetRegisterInfo *TRI) const;
  43. void loadRegFromStackSlot(MachineBasicBlock &MBB,
  44. MachineBasicBlock::iterator MBBI,
  45. unsigned DestReg, int FrameIndex,
  46. const TargetRegisterClass *RC,
  47. const TargetRegisterInfo *TRI) const;
  48. /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
  49. /// such, whenever a client has an instance of instruction info, it should
  50. /// always be able to get register info as well (through this method).
  51. ///
  52. const Thumb2RegisterInfo &getRegisterInfo() const { return RI; }
  53. };
  54. /// getITInstrPredicate - Valid only in Thumb2 mode. This function is identical
  55. /// to llvm::getInstrPredicate except it returns AL for conditional branch
  56. /// instructions which are "predicated", but are not in IT blocks.
  57. ARMCC::CondCodes getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
  58. }
  59. #endif // THUMB2INSTRUCTIONINFO_H