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/3rd_party/llvm/lib/Target/ARM/Thumb2InstrInfo.h

https://code.google.com/p/softart/
C++ Header | 75 lines | 37 code | 16 blank | 22 comment | 0 complexity | 8e46a98ea41e8f0ad2e6f4a45d1f07d8 MD5 | raw file
Possible License(s): LGPL-2.1, BSD-3-Clause, JSON, MPL-2.0-no-copyleft-exception, GPL-2.0, GPL-3.0, LGPL-3.0, BSD-2-Clause
 1//===-- Thumb2InstrInfo.h - Thumb-2 Instruction Information -----*- C++ -*-===//
 2//
 3//                     The LLVM Compiler Infrastructure
 4//
 5// This file is distributed under the University of Illinois Open Source
 6// License. See LICENSE.TXT for details.
 7//
 8//===----------------------------------------------------------------------===//
 9//
10// This file contains the Thumb-2 implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef THUMB2INSTRUCTIONINFO_H
15#define THUMB2INSTRUCTIONINFO_H
16
17#include "ARM.h"
18#include "ARMBaseInstrInfo.h"
19#include "Thumb2RegisterInfo.h"
20
21namespace llvm {
22class ARMSubtarget;
23class ScheduleHazardRecognizer;
24
25class Thumb2InstrInfo : public ARMBaseInstrInfo {
26  Thumb2RegisterInfo RI;
27public:
28  explicit Thumb2InstrInfo(const ARMSubtarget &STI);
29
30  /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
31  void getNoopForMachoTarget(MCInst &NopInst) const;
32
33  // Return the non-pre/post incrementing version of 'Opc'. Return 0
34  // if there is not such an opcode.
35  unsigned getUnindexedOpcode(unsigned Opc) const;
36
37  void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
38                               MachineBasicBlock *NewDest) const;
39
40  bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,
41                           MachineBasicBlock::iterator MBBI) const;
42
43  void copyPhysReg(MachineBasicBlock &MBB,
44                   MachineBasicBlock::iterator I, DebugLoc DL,
45                   unsigned DestReg, unsigned SrcReg,
46                   bool KillSrc) const;
47
48  void storeRegToStackSlot(MachineBasicBlock &MBB,
49                           MachineBasicBlock::iterator MBBI,
50                           unsigned SrcReg, bool isKill, int FrameIndex,
51                           const TargetRegisterClass *RC,
52                           const TargetRegisterInfo *TRI) const;
53
54  void loadRegFromStackSlot(MachineBasicBlock &MBB,
55                            MachineBasicBlock::iterator MBBI,
56                            unsigned DestReg, int FrameIndex,
57                            const TargetRegisterClass *RC,
58                            const TargetRegisterInfo *TRI) const;
59
60  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
61  /// such, whenever a client has an instance of instruction info, it should
62  /// always be able to get register info as well (through this method).
63  ///
64  const Thumb2RegisterInfo &getRegisterInfo() const { return RI; }
65};
66
67/// getITInstrPredicate - Valid only in Thumb2 mode. This function is identical
68/// to llvm::getInstrPredicate except it returns AL for conditional branch
69/// instructions which are "predicated", but are not in IT blocks.
70ARMCC::CondCodes getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
71
72
73}
74
75#endif // THUMB2INSTRUCTIONINFO_H