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/3rd_party/llvm/lib/Target/ARM/ARMTargetMachine.h

https://code.google.com/p/softart/
C++ Header | 146 lines | 100 code | 20 blank | 26 comment | 0 complexity | 21a7aa452d4e3a851dfde49cf3eda45b MD5 | raw file
Possible License(s): LGPL-2.1, BSD-3-Clause, JSON, MPL-2.0-no-copyleft-exception, GPL-2.0, GPL-3.0, LGPL-3.0, BSD-2-Clause
  1//===-- ARMTargetMachine.h - Define TargetMachine for ARM -------*- C++ -*-===//
  2//
  3//                     The LLVM Compiler Infrastructure
  4//
  5// This file is distributed under the University of Illinois Open Source
  6// License. See LICENSE.TXT for details.
  7//
  8//===----------------------------------------------------------------------===//
  9//
 10// This file declares the ARM specific subclass of TargetMachine.
 11//
 12//===----------------------------------------------------------------------===//
 13
 14#ifndef ARMTARGETMACHINE_H
 15#define ARMTARGETMACHINE_H
 16
 17#include "ARMFrameLowering.h"
 18#include "ARMISelLowering.h"
 19#include "ARMInstrInfo.h"
 20#include "ARMJITInfo.h"
 21#include "ARMSelectionDAGInfo.h"
 22#include "ARMSubtarget.h"
 23#include "Thumb1FrameLowering.h"
 24#include "Thumb1InstrInfo.h"
 25#include "Thumb2InstrInfo.h"
 26#include "llvm/ADT/OwningPtr.h"
 27#include "llvm/IR/DataLayout.h"
 28#include "llvm/MC/MCStreamer.h"
 29#include "llvm/Target/TargetMachine.h"
 30
 31namespace llvm {
 32
 33class ARMBaseTargetMachine : public LLVMTargetMachine {
 34protected:
 35  ARMSubtarget        Subtarget;
 36private:
 37  ARMJITInfo          JITInfo;
 38  InstrItineraryData  InstrItins;
 39
 40public:
 41  ARMBaseTargetMachine(const Target &T, StringRef TT,
 42                       StringRef CPU, StringRef FS,
 43                       const TargetOptions &Options,
 44                       Reloc::Model RM, CodeModel::Model CM,
 45                       CodeGenOpt::Level OL);
 46
 47  virtual       ARMJITInfo       *getJITInfo()         { return &JITInfo; }
 48  virtual const ARMSubtarget  *getSubtargetImpl() const { return &Subtarget; }
 49  virtual const ARMTargetLowering *getTargetLowering() const {
 50    // Implemented by derived classes
 51    llvm_unreachable("getTargetLowering not implemented");
 52  }
 53  virtual const InstrItineraryData *getInstrItineraryData() const {
 54    return &InstrItins;
 55  }
 56
 57  /// \brief Register ARM analysis passes with a pass manager.
 58  virtual void addAnalysisPasses(PassManagerBase &PM);
 59
 60  // Pass Pipeline Configuration
 61  virtual TargetPassConfig *createPassConfig(PassManagerBase &PM);
 62
 63  virtual bool addCodeEmitter(PassManagerBase &PM, JITCodeEmitter &MCE);
 64};
 65
 66/// ARMTargetMachine - ARM target machine.
 67///
 68class ARMTargetMachine : public ARMBaseTargetMachine {
 69  virtual void anchor();
 70  ARMInstrInfo        InstrInfo;
 71  const DataLayout    DL;       // Calculates type size & alignment
 72  ARMTargetLowering   TLInfo;
 73  ARMSelectionDAGInfo TSInfo;
 74  ARMFrameLowering    FrameLowering;
 75 public:
 76  ARMTargetMachine(const Target &T, StringRef TT,
 77                   StringRef CPU, StringRef FS,
 78                   const TargetOptions &Options,
 79                   Reloc::Model RM, CodeModel::Model CM,
 80                   CodeGenOpt::Level OL);
 81
 82  virtual const ARMRegisterInfo  *getRegisterInfo() const {
 83    return &InstrInfo.getRegisterInfo();
 84  }
 85
 86  virtual const ARMTargetLowering *getTargetLowering() const {
 87    return &TLInfo;
 88  }
 89
 90  virtual const ARMSelectionDAGInfo* getSelectionDAGInfo() const {
 91    return &TSInfo;
 92  }
 93  virtual const ARMFrameLowering *getFrameLowering() const {
 94    return &FrameLowering;
 95  }
 96  virtual const ARMInstrInfo     *getInstrInfo() const { return &InstrInfo; }
 97  virtual const DataLayout       *getDataLayout() const { return &DL; }
 98};
 99
100/// ThumbTargetMachine - Thumb target machine.
101/// Due to the way architectures are handled, this represents both
102///   Thumb-1 and Thumb-2.
103///
104class ThumbTargetMachine : public ARMBaseTargetMachine {
105  virtual void anchor();
106  // Either Thumb1InstrInfo or Thumb2InstrInfo.
107  OwningPtr<ARMBaseInstrInfo> InstrInfo;
108  const DataLayout    DL;   // Calculates type size & alignment
109  ARMTargetLowering   TLInfo;
110  ARMSelectionDAGInfo TSInfo;
111  // Either Thumb1FrameLowering or ARMFrameLowering.
112  OwningPtr<ARMFrameLowering> FrameLowering;
113public:
114  ThumbTargetMachine(const Target &T, StringRef TT,
115                     StringRef CPU, StringRef FS,
116                     const TargetOptions &Options,
117                     Reloc::Model RM, CodeModel::Model CM,
118                     CodeGenOpt::Level OL);
119
120  /// returns either Thumb1RegisterInfo or Thumb2RegisterInfo
121  virtual const ARMBaseRegisterInfo *getRegisterInfo() const {
122    return &InstrInfo->getRegisterInfo();
123  }
124
125  virtual const ARMTargetLowering *getTargetLowering() const {
126    return &TLInfo;
127  }
128
129  virtual const ARMSelectionDAGInfo *getSelectionDAGInfo() const {
130    return &TSInfo;
131  }
132
133  /// returns either Thumb1InstrInfo or Thumb2InstrInfo
134  virtual const ARMBaseInstrInfo *getInstrInfo() const {
135    return InstrInfo.get();
136  }
137  /// returns either Thumb1FrameLowering or ARMFrameLowering
138  virtual const ARMFrameLowering *getFrameLowering() const {
139    return FrameLowering.get();
140  }
141  virtual const DataLayout       *getDataLayout() const { return &DL; }
142};
143
144} // end namespace llvm
145
146#endif