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/3rd_party/llvm/lib/Target/X86/X86InstrFormats.td

https://code.google.com/p/softart/
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  1//===-- X86InstrFormats.td - X86 Instruction Formats -------*- tablegen -*-===//
  2//
  3//                     The LLVM Compiler Infrastructure
  4//
  5// This file is distributed under the University of Illinois Open Source
  6// License. See LICENSE.TXT for details.
  7//
  8//===----------------------------------------------------------------------===//
  9
 10//===----------------------------------------------------------------------===//
 11// X86 Instruction Format Definitions.
 12//
 13
 14// Format specifies the encoding used by the instruction.  This is part of the
 15// ad-hoc solution used to emit machine instruction encodings by our machine
 16// code emitter.
 17class Format<bits<6> val> {
 18  bits<6> Value = val;
 19}
 20
 21def Pseudo     : Format<0>; def RawFrm     : Format<1>;
 22def AddRegFrm  : Format<2>; def MRMDestReg : Format<3>;
 23def MRMDestMem : Format<4>; def MRMSrcReg  : Format<5>;
 24def MRMSrcMem  : Format<6>;
 25def MRM0r  : Format<16>; def MRM1r  : Format<17>; def MRM2r  : Format<18>;
 26def MRM3r  : Format<19>; def MRM4r  : Format<20>; def MRM5r  : Format<21>;
 27def MRM6r  : Format<22>; def MRM7r  : Format<23>;
 28def MRM0m  : Format<24>; def MRM1m  : Format<25>; def MRM2m  : Format<26>;
 29def MRM3m  : Format<27>; def MRM4m  : Format<28>; def MRM5m  : Format<29>;
 30def MRM6m  : Format<30>; def MRM7m  : Format<31>;
 31def MRMInitReg : Format<32>;
 32def MRM_C1 : Format<33>;
 33def MRM_C2 : Format<34>;
 34def MRM_C3 : Format<35>;
 35def MRM_C4 : Format<36>;
 36def MRM_C8 : Format<37>;
 37def MRM_C9 : Format<38>;
 38def MRM_CA : Format<39>;
 39def MRM_CB : Format<40>;
 40def MRM_E8 : Format<41>;
 41def MRM_F0 : Format<42>;
 42def RawFrmImm8 : Format<43>;
 43def RawFrmImm16 : Format<44>;
 44def MRM_F8 : Format<45>;
 45def MRM_F9 : Format<46>;
 46def MRM_D0 : Format<47>;
 47def MRM_D1 : Format<48>;
 48def MRM_D4 : Format<49>;
 49def MRM_D5 : Format<50>;
 50def MRM_D6 : Format<51>;
 51def MRM_D8 : Format<52>;
 52def MRM_D9 : Format<53>;
 53def MRM_DA : Format<54>;
 54def MRM_DB : Format<55>;
 55def MRM_DC : Format<56>;
 56def MRM_DD : Format<57>;
 57def MRM_DE : Format<58>;
 58def MRM_DF : Format<59>;
 59
 60// ImmType - This specifies the immediate type used by an instruction. This is
 61// part of the ad-hoc solution used to emit machine instruction encodings by our
 62// machine code emitter.
 63class ImmType<bits<3> val> {
 64  bits<3> Value = val;
 65}
 66def NoImm      : ImmType<0>;
 67def Imm8       : ImmType<1>;
 68def Imm8PCRel  : ImmType<2>;
 69def Imm16      : ImmType<3>;
 70def Imm16PCRel : ImmType<4>;
 71def Imm32      : ImmType<5>;
 72def Imm32PCRel : ImmType<6>;
 73def Imm64      : ImmType<7>;
 74
 75// FPFormat - This specifies what form this FP instruction has.  This is used by
 76// the Floating-Point stackifier pass.
 77class FPFormat<bits<3> val> {
 78  bits<3> Value = val;
 79}
 80def NotFP      : FPFormat<0>;
 81def ZeroArgFP  : FPFormat<1>;
 82def OneArgFP   : FPFormat<2>;
 83def OneArgFPRW : FPFormat<3>;
 84def TwoArgFP   : FPFormat<4>;
 85def CompareFP  : FPFormat<5>;
 86def CondMovFP  : FPFormat<6>;
 87def SpecialFP  : FPFormat<7>;
 88
 89// Class specifying the SSE execution domain, used by the SSEDomainFix pass.
 90// Keep in sync with tables in X86InstrInfo.cpp.
 91class Domain<bits<2> val> {
 92  bits<2> Value = val;
 93}
 94def GenericDomain   : Domain<0>;
 95def SSEPackedSingle : Domain<1>;
 96def SSEPackedDouble : Domain<2>;
 97def SSEPackedInt    : Domain<3>;
 98
 99// Class specifying the vector form of the decompressed
100// displacement of 8-bit.
101class CD8VForm<bits<3> val> {
102  bits<3> Value = val;
103}
104def CD8VF  : CD8VForm<0>;  // v := VL
105def CD8VH  : CD8VForm<1>;  // v := VL/2
106def CD8VQ  : CD8VForm<2>;  // v := VL/4
107def CD8VO  : CD8VForm<3>;  // v := VL/8
108def CD8VT1 : CD8VForm<4>;  // v := 1
109def CD8VT2 : CD8VForm<5>;  // v := 2
110def CD8VT4 : CD8VForm<6>;  // v := 4
111def CD8VT8 : CD8VForm<7>;  // v := 8
112
113// Prefix byte classes which are used to indicate to the ad-hoc machine code
114// emitter that various prefix bytes are required.
115class OpSize { bit hasOpSizePrefix = 1; }
116class AdSize { bit hasAdSizePrefix = 1; }
117class REX_W  { bit hasREX_WPrefix = 1; }
118class LOCK   { bit hasLockPrefix = 1; }
119class SegFS  { bits<2> SegOvrBits = 1; }
120class SegGS  { bits<2> SegOvrBits = 2; }
121class TB     { bits<5> Prefix = 1; }
122class REP    { bits<5> Prefix = 2; }
123class D8     { bits<5> Prefix = 3; }
124class D9     { bits<5> Prefix = 4; }
125class DA     { bits<5> Prefix = 5; }
126class DB     { bits<5> Prefix = 6; }
127class DC     { bits<5> Prefix = 7; }
128class DD     { bits<5> Prefix = 8; }
129class DE     { bits<5> Prefix = 9; }
130class DF     { bits<5> Prefix = 10; }
131class XD     { bits<5> Prefix = 11; }
132class XS     { bits<5> Prefix = 12; }
133class T8     { bits<5> Prefix = 13; }
134class TA     { bits<5> Prefix = 14; }
135class A6     { bits<5> Prefix = 15; }
136class A7     { bits<5> Prefix = 16; }
137class T8XD   { bits<5> Prefix = 17; }
138class T8XS   { bits<5> Prefix = 18; }
139class TAXD   { bits<5> Prefix = 19; }
140class XOP8   { bits<5> Prefix = 20; }
141class XOP9   { bits<5> Prefix = 21; }
142class XOPA   { bits<5> Prefix = 22; }
143class VEX    { bit hasVEXPrefix = 1; }
144class VEX_W  { bit hasVEX_WPrefix = 1; }
145class VEX_4V : VEX { bit hasVEX_4VPrefix = 1; }
146class VEX_4VOp3 : VEX { bit hasVEX_4VOp3Prefix = 1; }
147class VEX_I8IMM { bit hasVEX_i8ImmReg = 1; }
148class VEX_L  { bit hasVEX_L = 1; }
149class VEX_LIG { bit ignoresVEX_L = 1; }
150class EVEX : VEX { bit hasEVEXPrefix = 1; }
151class EVEX_4V : VEX_4V { bit hasEVEXPrefix = 1; }
152class EVEX_K { bit hasEVEX_K = 1; }
153class EVEX_KZ : EVEX_K { bit hasEVEX_Z = 1; }
154class EVEX_B { bit hasEVEX_B = 1; }
155class EVEX_V512 { bit hasEVEX_L2 = 1; bit hasVEX_L = 0; }
156class EVEX_CD8<int esize, CD8VForm form> {
157  bits<2> EVEX_CD8E = !if(!eq(esize, 8),  0b00,
158                      !if(!eq(esize, 16), 0b01,
159                      !if(!eq(esize, 32), 0b10,
160                      !if(!eq(esize, 64), 0b11, ?))));
161  bits<3> EVEX_CD8V = form.Value;
162}
163class Has3DNow0F0FOpcode  { bit has3DNow0F0FOpcode = 1; }
164class MemOp4 { bit hasMemOp4Prefix = 1; }
165class XOP { bit hasXOP_Prefix = 1; }
166class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins,
167              string AsmStr,
168              InstrItinClass itin,
169              Domain d = GenericDomain>
170  : Instruction {
171  let Namespace = "X86";
172
173  bits<8> Opcode = opcod;
174  Format Form = f;
175  bits<6> FormBits = Form.Value;
176  ImmType ImmT = i;
177
178  dag OutOperandList = outs;
179  dag InOperandList = ins;
180  string AsmString = AsmStr;
181
182  // If this is a pseudo instruction, mark it isCodeGenOnly.
183  let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo");
184
185  let Itinerary = itin;
186
187  //
188  // Attributes specific to X86 instructions...
189  //
190  bit hasOpSizePrefix = 0;  // Does this inst have a 0x66 prefix?
191  bit hasAdSizePrefix = 0;  // Does this inst have a 0x67 prefix?
192
193  bits<5> Prefix = 0;       // Which prefix byte does this inst have?
194  bit hasREX_WPrefix  = 0;  // Does this inst require the REX.W prefix?
195  FPFormat FPForm = NotFP;  // What flavor of FP instruction is this?
196  bit hasLockPrefix = 0;    // Does this inst have a 0xF0 prefix?
197  bits<2> SegOvrBits = 0;   // Segment override prefix.
198  Domain ExeDomain = d;
199  bit hasVEXPrefix = 0;     // Does this inst require a VEX prefix?
200  bit hasVEX_WPrefix = 0;   // Does this inst set the VEX_W field?
201  bit hasVEX_4VPrefix = 0;  // Does this inst require the VEX.VVVV field?
202  bit hasVEX_4VOp3Prefix = 0;  // Does this inst require the VEX.VVVV field to
203                               // encode the third operand?
204  bit hasVEX_i8ImmReg = 0;  // Does this inst require the last source register
205                            // to be encoded in a immediate field?
206  bit hasVEX_L = 0;         // Does this inst use large (256-bit) registers?
207  bit ignoresVEX_L = 0;     // Does this instruction ignore the L-bit
208  bit hasEVEXPrefix = 0;    // Does this inst require EVEX form?
209  bit hasEVEX_K = 0;        // Does this inst require masking?
210  bit hasEVEX_Z = 0;        // Does this inst set the EVEX_Z field?
211  bit hasEVEX_L2 = 0;       // Does this inst set the EVEX_L2 field?
212  bit hasEVEX_B = 0;        // Does this inst set the EVEX_B field?
213  bits<2> EVEX_CD8E = 0;    // Compressed disp8 form - element-size.
214  bits<3> EVEX_CD8V = 0;    // Compressed disp8 form - vector-width.
215  bit has3DNow0F0FOpcode =0;// Wacky 3dNow! encoding?
216  bit hasMemOp4Prefix = 0;  // Same bit as VEX_W, but used for swapping operands
217  bit hasXOP_Prefix = 0;    // Does this inst require an XOP prefix?
218
219  // TSFlags layout should be kept in sync with X86InstrInfo.h.
220  let TSFlags{5-0}   = FormBits;
221  let TSFlags{6}     = hasOpSizePrefix;
222  let TSFlags{7}     = hasAdSizePrefix;
223  let TSFlags{12-8}  = Prefix;
224  let TSFlags{13}    = hasREX_WPrefix;
225  let TSFlags{16-14} = ImmT.Value;
226  let TSFlags{19-17} = FPForm.Value;
227  let TSFlags{20}    = hasLockPrefix;
228  let TSFlags{22-21} = SegOvrBits;
229  let TSFlags{24-23} = ExeDomain.Value;
230  let TSFlags{32-25} = Opcode;
231  let TSFlags{33}    = hasVEXPrefix;
232  let TSFlags{34}    = hasVEX_WPrefix;
233  let TSFlags{35}    = hasVEX_4VPrefix;
234  let TSFlags{36}    = hasVEX_4VOp3Prefix;
235  let TSFlags{37}    = hasVEX_i8ImmReg;
236  let TSFlags{38}    = hasVEX_L;
237  let TSFlags{39}    = ignoresVEX_L;
238  let TSFlags{40}    = hasEVEXPrefix;
239  let TSFlags{41}    = hasEVEX_K;
240  let TSFlags{42}    = hasEVEX_Z;
241  let TSFlags{43}    = hasEVEX_L2;
242  let TSFlags{44}    = hasEVEX_B;
243  let TSFlags{46-45} = EVEX_CD8E;
244  let TSFlags{49-47} = EVEX_CD8V;
245  let TSFlags{50}    = has3DNow0F0FOpcode;
246  let TSFlags{51}    = hasMemOp4Prefix;
247  let TSFlags{52}    = hasXOP_Prefix;
248}
249
250class PseudoI<dag oops, dag iops, list<dag> pattern>
251  : X86Inst<0, Pseudo, NoImm, oops, iops, "", NoItinerary> {
252  let Pattern = pattern;
253}
254
255class I<bits<8> o, Format f, dag outs, dag ins, string asm,
256        list<dag> pattern, InstrItinClass itin = NoItinerary,
257        Domain d = GenericDomain>
258  : X86Inst<o, f, NoImm, outs, ins, asm, itin, d> {
259  let Pattern = pattern;
260  let CodeSize = 3;
261}
262class Ii8 <bits<8> o, Format f, dag outs, dag ins, string asm, 
263           list<dag> pattern, InstrItinClass itin = NoItinerary,
264           Domain d = GenericDomain>
265  : X86Inst<o, f, Imm8, outs, ins, asm, itin, d> {
266  let Pattern = pattern;
267  let CodeSize = 3;
268}
269class Ii8PCRel<bits<8> o, Format f, dag outs, dag ins, string asm, 
270               list<dag> pattern, InstrItinClass itin = NoItinerary>
271  : X86Inst<o, f, Imm8PCRel, outs, ins, asm, itin> {
272  let Pattern = pattern;
273  let CodeSize = 3;
274}
275class Ii16<bits<8> o, Format f, dag outs, dag ins, string asm, 
276           list<dag> pattern, InstrItinClass itin = NoItinerary>
277  : X86Inst<o, f, Imm16, outs, ins, asm, itin> {
278  let Pattern = pattern;
279  let CodeSize = 3;
280}
281class Ii32<bits<8> o, Format f, dag outs, dag ins, string asm, 
282           list<dag> pattern, InstrItinClass itin = NoItinerary>
283  : X86Inst<o, f, Imm32, outs, ins, asm, itin> {
284  let Pattern = pattern;
285  let CodeSize = 3;
286}
287
288class Ii16PCRel<bits<8> o, Format f, dag outs, dag ins, string asm, 
289           list<dag> pattern, InstrItinClass itin = NoItinerary>
290           : X86Inst<o, f, Imm16PCRel, outs, ins, asm, itin> {
291  let Pattern = pattern;
292  let CodeSize = 3;
293}
294
295class Ii32PCRel<bits<8> o, Format f, dag outs, dag ins, string asm, 
296           list<dag> pattern, InstrItinClass itin = NoItinerary>
297  : X86Inst<o, f, Imm32PCRel, outs, ins, asm, itin> {
298  let Pattern = pattern;
299  let CodeSize = 3;
300}
301
302// FPStack Instruction Templates:
303// FPI - Floating Point Instruction template.
304class FPI<bits<8> o, Format F, dag outs, dag ins, string asm,
305          InstrItinClass itin = NoItinerary>
306  : I<o, F, outs, ins, asm, [], itin> {}
307
308// FpI_ - Floating Point Pseudo Instruction template. Not Predicated.
309class FpI_<dag outs, dag ins, FPFormat fp, list<dag> pattern,
310           InstrItinClass itin = NoItinerary>
311  : X86Inst<0, Pseudo, NoImm, outs, ins, "", itin> {
312  let FPForm = fp;
313  let Pattern = pattern;
314}
315
316// Templates for instructions that use a 16- or 32-bit segmented address as
317//  their only operand: lcall (FAR CALL) and ljmp (FAR JMP)
318//
319//   Iseg16 - 16-bit segment selector, 16-bit offset
320//   Iseg32 - 16-bit segment selector, 32-bit offset
321
322class Iseg16 <bits<8> o, Format f, dag outs, dag ins, string asm, 
323              list<dag> pattern, InstrItinClass itin = NoItinerary>
324      : X86Inst<o, f, Imm16, outs, ins, asm, itin> {
325  let Pattern = pattern;
326  let CodeSize = 3;
327}
328
329class Iseg32 <bits<8> o, Format f, dag outs, dag ins, string asm, 
330              list<dag> pattern, InstrItinClass itin = NoItinerary>
331      : X86Inst<o, f, Imm32, outs, ins, asm, itin> {
332  let Pattern = pattern;
333  let CodeSize = 3;
334}
335
336def __xs : XS;
337def __xd : XD;
338
339// SI - SSE 1 & 2 scalar instructions
340class SI<bits<8> o, Format F, dag outs, dag ins, string asm,
341         list<dag> pattern, InstrItinClass itin = NoItinerary>
342      : I<o, F, outs, ins, asm, pattern, itin> {
343  let Predicates = !if(hasEVEXPrefix /* EVEX */, [HasAVX512],
344                   !if(hasVEXPrefix /* VEX */, [UseAVX],
345                   !if(!eq(Prefix, __xs.Prefix), [UseSSE1],
346                   !if(!eq(Prefix, __xd.Prefix), [UseSSE2],
347                   !if(hasOpSizePrefix, [UseSSE2], [UseSSE1])))));
348
349  // AVX instructions have a 'v' prefix in the mnemonic
350  let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm);
351}
352
353// SIi8 - SSE 1 & 2 scalar instructions
354class SIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
355           list<dag> pattern, InstrItinClass itin = NoItinerary>
356      : Ii8<o, F, outs, ins, asm, pattern, itin> {
357  let Predicates = !if(hasEVEXPrefix /* EVEX */, [HasAVX512],
358                   !if(hasVEXPrefix /* VEX */, [UseAVX],
359                   !if(!eq(Prefix, __xs.Prefix), [UseSSE1], [UseSSE2])));
360
361  // AVX instructions have a 'v' prefix in the mnemonic
362  let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm);
363}
364
365// PI - SSE 1 & 2 packed instructions
366class PI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern,
367         InstrItinClass itin, Domain d>
368      : I<o, F, outs, ins, asm, pattern, itin, d> {
369  let Predicates = !if(hasEVEXPrefix /* EVEX */, [HasAVX512],
370                   !if(hasVEXPrefix /* VEX */, [HasAVX],
371                   !if(hasOpSizePrefix /* OpSize */, [UseSSE2], [UseSSE1])));
372
373  // AVX instructions have a 'v' prefix in the mnemonic
374  let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm);
375}
376
377// MMXPI - SSE 1 & 2 packed instructions with MMX operands
378class MMXPI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern,
379            InstrItinClass itin, Domain d>
380      : I<o, F, outs, ins, asm, pattern, itin, d> {
381  let Predicates = !if(hasOpSizePrefix /* OpSize */, [HasSSE2], [HasSSE1]);
382}
383
384// PIi8 - SSE 1 & 2 packed instructions with immediate
385class PIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
386           list<dag> pattern, InstrItinClass itin, Domain d>
387      : Ii8<o, F, outs, ins, asm, pattern, itin, d> {
388  let Predicates = !if(hasEVEXPrefix /* EVEX */, [HasAVX512],
389                   !if(hasVEXPrefix /* VEX */, [HasAVX],
390                   !if(hasOpSizePrefix /* OpSize */, [UseSSE2], [UseSSE1])));
391
392  // AVX instructions have a 'v' prefix in the mnemonic
393  let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm);
394}
395
396// SSE1 Instruction Templates:
397// 
398//   SSI   - SSE1 instructions with XS prefix.
399//   PSI   - SSE1 instructions with TB prefix.
400//   PSIi8 - SSE1 instructions with ImmT == Imm8 and TB prefix.
401//   VSSI  - SSE1 instructions with XS prefix in AVX form.
402//   VPSI  - SSE1 instructions with TB prefix in AVX form, packed single.
403
404class SSI<bits<8> o, Format F, dag outs, dag ins, string asm,
405          list<dag> pattern, InstrItinClass itin = NoItinerary>
406      : I<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[UseSSE1]>;
407class SSIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
408            list<dag> pattern, InstrItinClass itin = NoItinerary>
409      : Ii8<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[UseSSE1]>;
410class PSI<bits<8> o, Format F, dag outs, dag ins, string asm,
411          list<dag> pattern, InstrItinClass itin = NoItinerary>
412      : I<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, TB,
413        Requires<[UseSSE1]>;
414class PSIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
415            list<dag> pattern, InstrItinClass itin = NoItinerary>
416      : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, TB,
417        Requires<[UseSSE1]>;
418class VSSI<bits<8> o, Format F, dag outs, dag ins, string asm,
419           list<dag> pattern, InstrItinClass itin = NoItinerary>
420      : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, XS,
421        Requires<[HasAVX]>;
422class VPSI<bits<8> o, Format F, dag outs, dag ins, string asm,
423           list<dag> pattern, InstrItinClass itin = NoItinerary>
424      : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin, SSEPackedSingle>, TB,
425        Requires<[HasAVX]>;
426
427// SSE2 Instruction Templates:
428// 
429//   SDI    - SSE2 instructions with XD prefix.
430//   SDIi8  - SSE2 instructions with ImmT == Imm8 and XD prefix.
431//   S2SI   - SSE2 instructions with XS prefix.
432//   SSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix.
433//   PDI    - SSE2 instructions with TB and OpSize prefixes, packed double domain.
434//   PDIi8  - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes.
435//   VSDI   - SSE2 scalar instructions with XD prefix in AVX form.
436//   VPDI   - SSE2 vector instructions with TB and OpSize prefixes in AVX form,
437//                 packed double domain.
438//   VS2I   - SSE2 scalar instructions with TB and OpSize prefixes in AVX form.
439//   S2I    - SSE2 scalar instructions with TB and OpSize prefixes.
440//   MMXSDIi8  - SSE2 instructions with ImmT == Imm8 and XD prefix as well as
441//               MMX operands.
442//   MMXSSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix as well as
443//               MMX operands.
444
445class SDI<bits<8> o, Format F, dag outs, dag ins, string asm,
446          list<dag> pattern, InstrItinClass itin = NoItinerary>
447      : I<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[UseSSE2]>;
448class SDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
449            list<dag> pattern, InstrItinClass itin = NoItinerary>
450      : Ii8<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[UseSSE2]>;
451class S2SI<bits<8> o, Format F, dag outs, dag ins, string asm,
452           list<dag> pattern, InstrItinClass itin = NoItinerary>
453      : I<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[UseSSE2]>;
454class S2SIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
455             list<dag> pattern, InstrItinClass itin = NoItinerary>
456      : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[UseSSE2]>;
457class PDI<bits<8> o, Format F, dag outs, dag ins, string asm,
458          list<dag> pattern, InstrItinClass itin = NoItinerary>
459      : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, TB, OpSize,
460        Requires<[UseSSE2]>;
461class PDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
462            list<dag> pattern, InstrItinClass itin = NoItinerary>
463      : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, TB, OpSize,
464        Requires<[UseSSE2]>;
465class VSDI<bits<8> o, Format F, dag outs, dag ins, string asm,
466           list<dag> pattern, InstrItinClass itin = NoItinerary>
467      : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, XD,
468        Requires<[UseAVX]>;
469class VS2SI<bits<8> o, Format F, dag outs, dag ins, string asm,
470            list<dag> pattern, InstrItinClass itin = NoItinerary>
471      : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, XS,
472        Requires<[HasAVX]>;
473class VPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
474           list<dag> pattern, InstrItinClass itin = NoItinerary>
475      : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin, SSEPackedDouble>, TB,
476        OpSize, Requires<[HasAVX]>;
477class VS2I<bits<8> o, Format F, dag outs, dag ins, string asm,
478           list<dag> pattern, InstrItinClass itin = NoItinerary>
479      : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, TB,
480        OpSize, Requires<[UseAVX]>;
481class S2I<bits<8> o, Format F, dag outs, dag ins, string asm,
482           list<dag> pattern, InstrItinClass itin = NoItinerary>
483      : I<o, F, outs, ins, asm, pattern, itin>, TB,
484        OpSize, Requires<[UseSSE2]>;
485class MMXSDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
486               list<dag> pattern, InstrItinClass itin = NoItinerary>
487      : Ii8<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[HasSSE2]>;
488class MMXS2SIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
489                list<dag> pattern, InstrItinClass itin = NoItinerary>
490      : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE2]>;
491
492// SSE3 Instruction Templates:
493// 
494//   S3I   - SSE3 instructions with TB and OpSize prefixes.
495//   S3SI  - SSE3 instructions with XS prefix.
496//   S3DI  - SSE3 instructions with XD prefix.
497
498class S3SI<bits<8> o, Format F, dag outs, dag ins, string asm, 
499           list<dag> pattern, InstrItinClass itin = NoItinerary>
500      : I<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, XS,
501        Requires<[UseSSE3]>;
502class S3DI<bits<8> o, Format F, dag outs, dag ins, string asm, 
503           list<dag> pattern, InstrItinClass itin = NoItinerary>
504      : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, XD,
505        Requires<[UseSSE3]>;
506class S3I<bits<8> o, Format F, dag outs, dag ins, string asm,
507          list<dag> pattern, InstrItinClass itin = NoItinerary>
508      : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, TB, OpSize,
509        Requires<[UseSSE3]>;
510
511
512// SSSE3 Instruction Templates:
513// 
514//   SS38I - SSSE3 instructions with T8 prefix.
515//   SS3AI - SSSE3 instructions with TA prefix.
516//   MMXSS38I - SSSE3 instructions with T8 prefix and MMX operands.
517//   MMXSS3AI - SSSE3 instructions with TA prefix and MMX operands.
518//
519// Note: SSSE3 instructions have 64-bit and 128-bit versions. The 64-bit version
520// uses the MMX registers. The 64-bit versions are grouped with the MMX
521// classes. They need to be enabled even if AVX is enabled.
522
523class SS38I<bits<8> o, Format F, dag outs, dag ins, string asm,
524            list<dag> pattern, InstrItinClass itin = NoItinerary>
525      : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8,
526        Requires<[UseSSSE3]>;
527class SS3AI<bits<8> o, Format F, dag outs, dag ins, string asm,
528            list<dag> pattern, InstrItinClass itin = NoItinerary>
529      : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
530        Requires<[UseSSSE3]>;
531class MMXSS38I<bits<8> o, Format F, dag outs, dag ins, string asm,
532               list<dag> pattern, InstrItinClass itin = NoItinerary>
533      : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8,
534        Requires<[HasSSSE3]>;
535class MMXSS3AI<bits<8> o, Format F, dag outs, dag ins, string asm,
536               list<dag> pattern, InstrItinClass itin = NoItinerary>
537      : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
538        Requires<[HasSSSE3]>;
539
540// SSE4.1 Instruction Templates:
541// 
542//   SS48I - SSE 4.1 instructions with T8 prefix.
543//   SS41AIi8 - SSE 4.1 instructions with TA prefix and ImmT == Imm8.
544//
545class SS48I<bits<8> o, Format F, dag outs, dag ins, string asm,
546            list<dag> pattern, InstrItinClass itin = NoItinerary>
547      : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8,
548        Requires<[UseSSE41]>;
549class SS4AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
550            list<dag> pattern, InstrItinClass itin = NoItinerary>
551      : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
552        Requires<[UseSSE41]>;
553
554// SSE4.2 Instruction Templates:
555// 
556//   SS428I - SSE 4.2 instructions with T8 prefix.
557class SS428I<bits<8> o, Format F, dag outs, dag ins, string asm,
558             list<dag> pattern, InstrItinClass itin = NoItinerary>
559      : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8,
560        Requires<[UseSSE42]>;
561
562//   SS42FI - SSE 4.2 instructions with T8XD prefix.
563// NOTE: 'HasSSE42' is used as SS42FI is only used for CRC32 insns.
564class SS42FI<bits<8> o, Format F, dag outs, dag ins, string asm,
565             list<dag> pattern, InstrItinClass itin = NoItinerary>
566      : I<o, F, outs, ins, asm, pattern, itin>, T8XD, Requires<[HasSSE42]>;
567
568//   SS42AI = SSE 4.2 instructions with TA prefix
569class SS42AI<bits<8> o, Format F, dag outs, dag ins, string asm,
570             list<dag> pattern, InstrItinClass itin = NoItinerary>
571      : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
572        Requires<[UseSSE42]>;
573
574// AVX Instruction Templates:
575//   Instructions introduced in AVX (no SSE equivalent forms)
576//
577//   AVX8I - AVX instructions with T8 and OpSize prefix.
578//   AVXAIi8 - AVX instructions with TA, OpSize prefix and ImmT = Imm8.
579class AVX8I<bits<8> o, Format F, dag outs, dag ins, string asm,
580            list<dag> pattern, InstrItinClass itin = NoItinerary>
581      : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8, OpSize,
582        Requires<[HasAVX]>;
583class AVXAIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
584              list<dag> pattern, InstrItinClass itin = NoItinerary>
585      : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA, OpSize,
586        Requires<[HasAVX]>;
587
588// AVX2 Instruction Templates:
589//   Instructions introduced in AVX2 (no SSE equivalent forms)
590//
591//   AVX28I - AVX2 instructions with T8 and OpSize prefix.
592//   AVX2AIi8 - AVX2 instructions with TA, OpSize prefix and ImmT = Imm8.
593class AVX28I<bits<8> o, Format F, dag outs, dag ins, string asm,
594            list<dag> pattern, InstrItinClass itin = NoItinerary>
595      : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8, OpSize,
596        Requires<[HasAVX2]>;
597class AVX2AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
598              list<dag> pattern, InstrItinClass itin = NoItinerary>
599      : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA, OpSize,
600        Requires<[HasAVX2]>;
601
602
603// AVX-512 Instruction Templates:
604//   Instructions introduced in AVX-512 (no SSE equivalent forms)
605//
606//   AVX5128I - AVX-512 instructions with T8 and OpSize prefix.
607//   AVX512AIi8 - AVX-512 instructions with TA, OpSize prefix and ImmT = Imm8.
608//   AVX512PDI  - AVX-512 instructions with TB, OpSize, double packed.
609//   AVX512PSI  - AVX-512 instructions with TB, single packed.
610//   AVX512XS8I - AVX-512 instructions with T8 and XS prefixes.
611//   AVX512XSI  - AVX-512 instructions with XS prefix, generic domain.
612//   AVX512BI   - AVX-512 instructions with TB, OpSize, int packed domain.
613//   AVX512SI   - AVX-512 scalar instructions with TB and OpSize prefixes.
614
615class AVX5128I<bits<8> o, Format F, dag outs, dag ins, string asm,
616            list<dag> pattern, InstrItinClass itin = NoItinerary>
617      : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8, OpSize,
618        Requires<[HasAVX512]>;
619class AVX512XS8I<bits<8> o, Format F, dag outs, dag ins, string asm,
620            list<dag> pattern, InstrItinClass itin = NoItinerary>
621      : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8XS,
622        Requires<[HasAVX512]>;
623class AVX512XSI<bits<8> o, Format F, dag outs, dag ins, string asm,
624            list<dag> pattern, InstrItinClass itin = NoItinerary>
625      : I<o, F, outs, ins, asm, pattern, itin>, XS,
626        Requires<[HasAVX512]>;
627class AVX512XDI<bits<8> o, Format F, dag outs, dag ins, string asm,
628            list<dag> pattern, InstrItinClass itin = NoItinerary>
629      : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, XD,
630        Requires<[HasAVX512]>;
631class AVX512BI<bits<8> o, Format F, dag outs, dag ins, string asm,
632            list<dag> pattern, InstrItinClass itin = NoItinerary>
633      : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TB, OpSize,
634        Requires<[HasAVX512]>;
635class AVX512BIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
636              list<dag> pattern, InstrItinClass itin = NoItinerary>
637      : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TB, OpSize,
638        Requires<[HasAVX512]>;
639class AVX512SI<bits<8> o, Format F, dag outs, dag ins, string asm,
640            list<dag> pattern, InstrItinClass itin = NoItinerary>
641      : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TB, OpSize,
642        Requires<[HasAVX512]>;
643class AVX512AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
644              list<dag> pattern, InstrItinClass itin = NoItinerary>
645      : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA, OpSize,
646        Requires<[HasAVX512]>;
647class AVX512Ii8<bits<8> o, Format F, dag outs, dag ins, string asm,
648              list<dag> pattern, InstrItinClass itin = NoItinerary>
649      : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TB,
650      Requires<[HasAVX512]>;
651class AVX512PDI<bits<8> o, Format F, dag outs, dag ins, string asm,
652           list<dag> pattern, InstrItinClass itin = NoItinerary>
653      : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, TB,
654        OpSize, Requires<[HasAVX512]>;
655class AVX512PSI<bits<8> o, Format F, dag outs, dag ins, string asm,
656           list<dag> pattern, InstrItinClass itin = NoItinerary>
657      : I<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, TB,
658        Requires<[HasAVX512]>;
659class AVX512PIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
660              list<dag> pattern, Domain d, InstrItinClass itin = NoItinerary>
661      : Ii8<o, F, outs, ins, asm, pattern, itin, d>, TB, Requires<[HasAVX512]>;
662class AVX512PI<bits<8> o, Format F, dag outs, dag ins, string asm,
663              list<dag> pattern, Domain d, InstrItinClass itin = NoItinerary>
664      : I<o, F, outs, ins, asm, pattern, itin, d>, TB, Requires<[HasAVX512]>;
665class AVX512FMA3<bits<8> o, Format F, dag outs, dag ins, string asm,
666           list<dag>pattern, InstrItinClass itin = NoItinerary>
667      : I<o, F, outs, ins, asm, pattern, itin>, T8,
668        OpSize, EVEX_4V, Requires<[HasAVX512]>;
669
670// AES Instruction Templates:
671//
672// AES8I
673// These use the same encoding as the SSE4.2 T8 and TA encodings.
674class AES8I<bits<8> o, Format F, dag outs, dag ins, string asm,
675            list<dag>pattern, InstrItinClass itin = IIC_AES>
676      : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8,
677        Requires<[HasAES]>;
678
679class AESAI<bits<8> o, Format F, dag outs, dag ins, string asm,
680            list<dag> pattern, InstrItinClass itin = NoItinerary>
681      : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
682        Requires<[HasAES]>;
683
684// PCLMUL Instruction Templates
685class PCLMULIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
686               list<dag>pattern, InstrItinClass itin = NoItinerary>
687      : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
688        OpSize, Requires<[HasPCLMUL]>;
689
690class AVXPCLMULIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
691                  list<dag>pattern, InstrItinClass itin = NoItinerary>
692      : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
693        OpSize, VEX_4V, Requires<[HasAVX, HasPCLMUL]>;
694
695// FMA3 Instruction Templates
696class FMA3<bits<8> o, Format F, dag outs, dag ins, string asm,
697           list<dag>pattern, InstrItinClass itin = NoItinerary>
698      : I<o, F, outs, ins, asm, pattern, itin>, T8,
699        OpSize, VEX_4V, FMASC, Requires<[HasFMA]>;
700
701// FMA4 Instruction Templates
702class FMA4<bits<8> o, Format F, dag outs, dag ins, string asm,
703           list<dag>pattern, InstrItinClass itin = NoItinerary>
704      : Ii8<o, F, outs, ins, asm, pattern, itin>, TA,
705        OpSize, VEX_4V, VEX_I8IMM, FMASC, Requires<[HasFMA4]>;
706
707// XOP 2, 3 and 4 Operand Instruction Template
708class IXOP<bits<8> o, Format F, dag outs, dag ins, string asm,
709           list<dag> pattern, InstrItinClass itin = NoItinerary>
710      : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>,
711         XOP, XOP9, Requires<[HasXOP]>;
712
713// XOP 2, 3 and 4 Operand Instruction Templates with imm byte
714class IXOPi8<bits<8> o, Format F, dag outs, dag ins, string asm,
715           list<dag> pattern, InstrItinClass itin = NoItinerary>
716      : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>,
717         XOP, XOP8, Requires<[HasXOP]>;
718
719//  XOP 5 operand instruction (VEX encoding!)
720class IXOP5<bits<8> o, Format F, dag outs, dag ins, string asm,
721           list<dag>pattern, InstrItinClass itin = NoItinerary>
722      : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
723        OpSize, VEX_4V, VEX_I8IMM, Requires<[HasXOP]>;
724
725// X86-64 Instruction templates...
726//
727
728class RI<bits<8> o, Format F, dag outs, dag ins, string asm,
729         list<dag> pattern, InstrItinClass itin = NoItinerary>
730      : I<o, F, outs, ins, asm, pattern, itin>, REX_W;
731class RIi8 <bits<8> o, Format F, dag outs, dag ins, string asm,
732            list<dag> pattern, InstrItinClass itin = NoItinerary>
733      : Ii8<o, F, outs, ins, asm, pattern, itin>, REX_W;
734class RIi32 <bits<8> o, Format F, dag outs, dag ins, string asm,
735             list<dag> pattern, InstrItinClass itin = NoItinerary>
736      : Ii32<o, F, outs, ins, asm, pattern, itin>, REX_W;
737
738class RIi64<bits<8> o, Format f, dag outs, dag ins, string asm,
739            list<dag> pattern, InstrItinClass itin = NoItinerary>
740  : X86Inst<o, f, Imm64, outs, ins, asm, itin>, REX_W {
741  let Pattern = pattern;
742  let CodeSize = 3;
743}
744
745class RIi64_NOREX<bits<8> o, Format f, dag outs, dag ins, string asm,
746            list<dag> pattern, InstrItinClass itin = NoItinerary>
747  : X86Inst<o, f, Imm64, outs, ins, asm, itin> {
748  let Pattern = pattern;
749  let CodeSize = 3;
750}
751
752class RSSI<bits<8> o, Format F, dag outs, dag ins, string asm,
753           list<dag> pattern, InstrItinClass itin = NoItinerary>
754      : SSI<o, F, outs, ins, asm, pattern, itin>, REX_W;
755class RSDI<bits<8> o, Format F, dag outs, dag ins, string asm,
756           list<dag> pattern, InstrItinClass itin = NoItinerary>
757      : SDI<o, F, outs, ins, asm, pattern, itin>, REX_W;
758class RPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
759           list<dag> pattern, InstrItinClass itin = NoItinerary>
760      : PDI<o, F, outs, ins, asm, pattern, itin>, REX_W;
761class VRPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
762           list<dag> pattern, InstrItinClass itin = NoItinerary>
763      : VPDI<o, F, outs, ins, asm, pattern, itin>, VEX_W;
764class RS2I<bits<8> o, Format F, dag outs, dag ins, string asm,
765           list<dag> pattern, InstrItinClass itin = NoItinerary>
766      : S2I<o, F, outs, ins, asm, pattern, itin>, REX_W;
767class VRS2I<bits<8> o, Format F, dag outs, dag ins, string asm,
768           list<dag> pattern, InstrItinClass itin = NoItinerary>
769      : VS2I<o, F, outs, ins, asm, pattern, itin>, VEX_W;
770
771// MMX Instruction templates
772//
773
774// MMXI   - MMX instructions with TB prefix.
775// MMXI32 - MMX instructions with TB prefix valid only in 32 bit mode.
776// MMXI64 - MMX instructions with TB prefix valid only in 64 bit mode.
777// MMX2I  - MMX / SSE2 instructions with TB and OpSize prefixes.
778// MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
779// MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
780// MMXID  - MMX instructions with XD prefix.
781// MMXIS  - MMX instructions with XS prefix.
782class MMXI<bits<8> o, Format F, dag outs, dag ins, string asm, 
783           list<dag> pattern, InstrItinClass itin = NoItinerary>
784      : I<o, F, outs, ins, asm, pattern, itin>, TB, Requires<[HasMMX]>;
785class MMXI32<bits<8> o, Format F, dag outs, dag ins, string asm, 
786             list<dag> pattern, InstrItinClass itin = NoItinerary>
787      : I<o, F, outs, ins, asm, pattern, itin>, TB, Requires<[HasMMX,In32BitMode]>;
788class MMXI64<bits<8> o, Format F, dag outs, dag ins, string asm, 
789             list<dag> pattern, InstrItinClass itin = NoItinerary>
790      : I<o, F, outs, ins, asm, pattern, itin>, TB, Requires<[HasMMX,In64BitMode]>;
791class MMXRI<bits<8> o, Format F, dag outs, dag ins, string asm, 
792            list<dag> pattern, InstrItinClass itin = NoItinerary>
793      : I<o, F, outs, ins, asm, pattern, itin>, TB, REX_W, Requires<[HasMMX]>;
794class MMX2I<bits<8> o, Format F, dag outs, dag ins, string asm, 
795            list<dag> pattern, InstrItinClass itin = NoItinerary>
796      : I<o, F, outs, ins, asm, pattern, itin>, TB, OpSize, Requires<[HasMMX]>;
797class MMXIi8<bits<8> o, Format F, dag outs, dag ins, string asm, 
798             list<dag> pattern, InstrItinClass itin = NoItinerary>
799      : Ii8<o, F, outs, ins, asm, pattern, itin>, TB, Requires<[HasMMX]>;
800class MMXID<bits<8> o, Format F, dag outs, dag ins, string asm, 
801            list<dag> pattern, InstrItinClass itin = NoItinerary>
802      : Ii8<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[HasMMX]>;
803class MMXIS<bits<8> o, Format F, dag outs, dag ins, string asm, 
804            list<dag> pattern, InstrItinClass itin = NoItinerary>
805      : Ii8<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[HasMMX]>;