/3rd_party/llvm/lib/Target/X86/X86InstrFormats.td

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  1. //===-- X86InstrFormats.td - X86 Instruction Formats -------*- tablegen -*-===//
  2. //
  3. // The LLVM Compiler Infrastructure
  4. //
  5. // This file is distributed under the University of Illinois Open Source
  6. // License. See LICENSE.TXT for details.
  7. //
  8. //===----------------------------------------------------------------------===//
  9. //===----------------------------------------------------------------------===//
  10. // X86 Instruction Format Definitions.
  11. //
  12. // Format specifies the encoding used by the instruction. This is part of the
  13. // ad-hoc solution used to emit machine instruction encodings by our machine
  14. // code emitter.
  15. class Format<bits<6> val> {
  16. bits<6> Value = val;
  17. }
  18. def Pseudo : Format<0>; def RawFrm : Format<1>;
  19. def AddRegFrm : Format<2>; def MRMDestReg : Format<3>;
  20. def MRMDestMem : Format<4>; def MRMSrcReg : Format<5>;
  21. def MRMSrcMem : Format<6>;
  22. def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>;
  23. def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>;
  24. def MRM6r : Format<22>; def MRM7r : Format<23>;
  25. def MRM0m : Format<24>; def MRM1m : Format<25>; def MRM2m : Format<26>;
  26. def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>;
  27. def MRM6m : Format<30>; def MRM7m : Format<31>;
  28. def MRMInitReg : Format<32>;
  29. def MRM_C1 : Format<33>;
  30. def MRM_C2 : Format<34>;
  31. def MRM_C3 : Format<35>;
  32. def MRM_C4 : Format<36>;
  33. def MRM_C8 : Format<37>;
  34. def MRM_C9 : Format<38>;
  35. def MRM_CA : Format<39>;
  36. def MRM_CB : Format<40>;
  37. def MRM_E8 : Format<41>;
  38. def MRM_F0 : Format<42>;
  39. def RawFrmImm8 : Format<43>;
  40. def RawFrmImm16 : Format<44>;
  41. def MRM_F8 : Format<45>;
  42. def MRM_F9 : Format<46>;
  43. def MRM_D0 : Format<47>;
  44. def MRM_D1 : Format<48>;
  45. def MRM_D4 : Format<49>;
  46. def MRM_D5 : Format<50>;
  47. def MRM_D6 : Format<51>;
  48. def MRM_D8 : Format<52>;
  49. def MRM_D9 : Format<53>;
  50. def MRM_DA : Format<54>;
  51. def MRM_DB : Format<55>;
  52. def MRM_DC : Format<56>;
  53. def MRM_DD : Format<57>;
  54. def MRM_DE : Format<58>;
  55. def MRM_DF : Format<59>;
  56. // ImmType - This specifies the immediate type used by an instruction. This is
  57. // part of the ad-hoc solution used to emit machine instruction encodings by our
  58. // machine code emitter.
  59. class ImmType<bits<3> val> {
  60. bits<3> Value = val;
  61. }
  62. def NoImm : ImmType<0>;
  63. def Imm8 : ImmType<1>;
  64. def Imm8PCRel : ImmType<2>;
  65. def Imm16 : ImmType<3>;
  66. def Imm16PCRel : ImmType<4>;
  67. def Imm32 : ImmType<5>;
  68. def Imm32PCRel : ImmType<6>;
  69. def Imm64 : ImmType<7>;
  70. // FPFormat - This specifies what form this FP instruction has. This is used by
  71. // the Floating-Point stackifier pass.
  72. class FPFormat<bits<3> val> {
  73. bits<3> Value = val;
  74. }
  75. def NotFP : FPFormat<0>;
  76. def ZeroArgFP : FPFormat<1>;
  77. def OneArgFP : FPFormat<2>;
  78. def OneArgFPRW : FPFormat<3>;
  79. def TwoArgFP : FPFormat<4>;
  80. def CompareFP : FPFormat<5>;
  81. def CondMovFP : FPFormat<6>;
  82. def SpecialFP : FPFormat<7>;
  83. // Class specifying the SSE execution domain, used by the SSEDomainFix pass.
  84. // Keep in sync with tables in X86InstrInfo.cpp.
  85. class Domain<bits<2> val> {
  86. bits<2> Value = val;
  87. }
  88. def GenericDomain : Domain<0>;
  89. def SSEPackedSingle : Domain<1>;
  90. def SSEPackedDouble : Domain<2>;
  91. def SSEPackedInt : Domain<3>;
  92. // Class specifying the vector form of the decompressed
  93. // displacement of 8-bit.
  94. class CD8VForm<bits<3> val> {
  95. bits<3> Value = val;
  96. }
  97. def CD8VF : CD8VForm<0>; // v := VL
  98. def CD8VH : CD8VForm<1>; // v := VL/2
  99. def CD8VQ : CD8VForm<2>; // v := VL/4
  100. def CD8VO : CD8VForm<3>; // v := VL/8
  101. def CD8VT1 : CD8VForm<4>; // v := 1
  102. def CD8VT2 : CD8VForm<5>; // v := 2
  103. def CD8VT4 : CD8VForm<6>; // v := 4
  104. def CD8VT8 : CD8VForm<7>; // v := 8
  105. // Prefix byte classes which are used to indicate to the ad-hoc machine code
  106. // emitter that various prefix bytes are required.
  107. class OpSize { bit hasOpSizePrefix = 1; }
  108. class AdSize { bit hasAdSizePrefix = 1; }
  109. class REX_W { bit hasREX_WPrefix = 1; }
  110. class LOCK { bit hasLockPrefix = 1; }
  111. class SegFS { bits<2> SegOvrBits = 1; }
  112. class SegGS { bits<2> SegOvrBits = 2; }
  113. class TB { bits<5> Prefix = 1; }
  114. class REP { bits<5> Prefix = 2; }
  115. class D8 { bits<5> Prefix = 3; }
  116. class D9 { bits<5> Prefix = 4; }
  117. class DA { bits<5> Prefix = 5; }
  118. class DB { bits<5> Prefix = 6; }
  119. class DC { bits<5> Prefix = 7; }
  120. class DD { bits<5> Prefix = 8; }
  121. class DE { bits<5> Prefix = 9; }
  122. class DF { bits<5> Prefix = 10; }
  123. class XD { bits<5> Prefix = 11; }
  124. class XS { bits<5> Prefix = 12; }
  125. class T8 { bits<5> Prefix = 13; }
  126. class TA { bits<5> Prefix = 14; }
  127. class A6 { bits<5> Prefix = 15; }
  128. class A7 { bits<5> Prefix = 16; }
  129. class T8XD { bits<5> Prefix = 17; }
  130. class T8XS { bits<5> Prefix = 18; }
  131. class TAXD { bits<5> Prefix = 19; }
  132. class XOP8 { bits<5> Prefix = 20; }
  133. class XOP9 { bits<5> Prefix = 21; }
  134. class XOPA { bits<5> Prefix = 22; }
  135. class VEX { bit hasVEXPrefix = 1; }
  136. class VEX_W { bit hasVEX_WPrefix = 1; }
  137. class VEX_4V : VEX { bit hasVEX_4VPrefix = 1; }
  138. class VEX_4VOp3 : VEX { bit hasVEX_4VOp3Prefix = 1; }
  139. class VEX_I8IMM { bit hasVEX_i8ImmReg = 1; }
  140. class VEX_L { bit hasVEX_L = 1; }
  141. class VEX_LIG { bit ignoresVEX_L = 1; }
  142. class EVEX : VEX { bit hasEVEXPrefix = 1; }
  143. class EVEX_4V : VEX_4V { bit hasEVEXPrefix = 1; }
  144. class EVEX_K { bit hasEVEX_K = 1; }
  145. class EVEX_KZ : EVEX_K { bit hasEVEX_Z = 1; }
  146. class EVEX_B { bit hasEVEX_B = 1; }
  147. class EVEX_V512 { bit hasEVEX_L2 = 1; bit hasVEX_L = 0; }
  148. class EVEX_CD8<int esize, CD8VForm form> {
  149. bits<2> EVEX_CD8E = !if(!eq(esize, 8), 0b00,
  150. !if(!eq(esize, 16), 0b01,
  151. !if(!eq(esize, 32), 0b10,
  152. !if(!eq(esize, 64), 0b11, ?))));
  153. bits<3> EVEX_CD8V = form.Value;
  154. }
  155. class Has3DNow0F0FOpcode { bit has3DNow0F0FOpcode = 1; }
  156. class MemOp4 { bit hasMemOp4Prefix = 1; }
  157. class XOP { bit hasXOP_Prefix = 1; }
  158. class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins,
  159. string AsmStr,
  160. InstrItinClass itin,
  161. Domain d = GenericDomain>
  162. : Instruction {
  163. let Namespace = "X86";
  164. bits<8> Opcode = opcod;
  165. Format Form = f;
  166. bits<6> FormBits = Form.Value;
  167. ImmType ImmT = i;
  168. dag OutOperandList = outs;
  169. dag InOperandList = ins;
  170. string AsmString = AsmStr;
  171. // If this is a pseudo instruction, mark it isCodeGenOnly.
  172. let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo");
  173. let Itinerary = itin;
  174. //
  175. // Attributes specific to X86 instructions...
  176. //
  177. bit hasOpSizePrefix = 0; // Does this inst have a 0x66 prefix?
  178. bit hasAdSizePrefix = 0; // Does this inst have a 0x67 prefix?
  179. bits<5> Prefix = 0; // Which prefix byte does this inst have?
  180. bit hasREX_WPrefix = 0; // Does this inst require the REX.W prefix?
  181. FPFormat FPForm = NotFP; // What flavor of FP instruction is this?
  182. bit hasLockPrefix = 0; // Does this inst have a 0xF0 prefix?
  183. bits<2> SegOvrBits = 0; // Segment override prefix.
  184. Domain ExeDomain = d;
  185. bit hasVEXPrefix = 0; // Does this inst require a VEX prefix?
  186. bit hasVEX_WPrefix = 0; // Does this inst set the VEX_W field?
  187. bit hasVEX_4VPrefix = 0; // Does this inst require the VEX.VVVV field?
  188. bit hasVEX_4VOp3Prefix = 0; // Does this inst require the VEX.VVVV field to
  189. // encode the third operand?
  190. bit hasVEX_i8ImmReg = 0; // Does this inst require the last source register
  191. // to be encoded in a immediate field?
  192. bit hasVEX_L = 0; // Does this inst use large (256-bit) registers?
  193. bit ignoresVEX_L = 0; // Does this instruction ignore the L-bit
  194. bit hasEVEXPrefix = 0; // Does this inst require EVEX form?
  195. bit hasEVEX_K = 0; // Does this inst require masking?
  196. bit hasEVEX_Z = 0; // Does this inst set the EVEX_Z field?
  197. bit hasEVEX_L2 = 0; // Does this inst set the EVEX_L2 field?
  198. bit hasEVEX_B = 0; // Does this inst set the EVEX_B field?
  199. bits<2> EVEX_CD8E = 0; // Compressed disp8 form - element-size.
  200. bits<3> EVEX_CD8V = 0; // Compressed disp8 form - vector-width.
  201. bit has3DNow0F0FOpcode =0;// Wacky 3dNow! encoding?
  202. bit hasMemOp4Prefix = 0; // Same bit as VEX_W, but used for swapping operands
  203. bit hasXOP_Prefix = 0; // Does this inst require an XOP prefix?
  204. // TSFlags layout should be kept in sync with X86InstrInfo.h.
  205. let TSFlags{5-0} = FormBits;
  206. let TSFlags{6} = hasOpSizePrefix;
  207. let TSFlags{7} = hasAdSizePrefix;
  208. let TSFlags{12-8} = Prefix;
  209. let TSFlags{13} = hasREX_WPrefix;
  210. let TSFlags{16-14} = ImmT.Value;
  211. let TSFlags{19-17} = FPForm.Value;
  212. let TSFlags{20} = hasLockPrefix;
  213. let TSFlags{22-21} = SegOvrBits;
  214. let TSFlags{24-23} = ExeDomain.Value;
  215. let TSFlags{32-25} = Opcode;
  216. let TSFlags{33} = hasVEXPrefix;
  217. let TSFlags{34} = hasVEX_WPrefix;
  218. let TSFlags{35} = hasVEX_4VPrefix;
  219. let TSFlags{36} = hasVEX_4VOp3Prefix;
  220. let TSFlags{37} = hasVEX_i8ImmReg;
  221. let TSFlags{38} = hasVEX_L;
  222. let TSFlags{39} = ignoresVEX_L;
  223. let TSFlags{40} = hasEVEXPrefix;
  224. let TSFlags{41} = hasEVEX_K;
  225. let TSFlags{42} = hasEVEX_Z;
  226. let TSFlags{43} = hasEVEX_L2;
  227. let TSFlags{44} = hasEVEX_B;
  228. let TSFlags{46-45} = EVEX_CD8E;
  229. let TSFlags{49-47} = EVEX_CD8V;
  230. let TSFlags{50} = has3DNow0F0FOpcode;
  231. let TSFlags{51} = hasMemOp4Prefix;
  232. let TSFlags{52} = hasXOP_Prefix;
  233. }
  234. class PseudoI<dag oops, dag iops, list<dag> pattern>
  235. : X86Inst<0, Pseudo, NoImm, oops, iops, "", NoItinerary> {
  236. let Pattern = pattern;
  237. }
  238. class I<bits<8> o, Format f, dag outs, dag ins, string asm,
  239. list<dag> pattern, InstrItinClass itin = NoItinerary,
  240. Domain d = GenericDomain>
  241. : X86Inst<o, f, NoImm, outs, ins, asm, itin, d> {
  242. let Pattern = pattern;
  243. let CodeSize = 3;
  244. }
  245. class Ii8 <bits<8> o, Format f, dag outs, dag ins, string asm,
  246. list<dag> pattern, InstrItinClass itin = NoItinerary,
  247. Domain d = GenericDomain>
  248. : X86Inst<o, f, Imm8, outs, ins, asm, itin, d> {
  249. let Pattern = pattern;
  250. let CodeSize = 3;
  251. }
  252. class Ii8PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
  253. list<dag> pattern, InstrItinClass itin = NoItinerary>
  254. : X86Inst<o, f, Imm8PCRel, outs, ins, asm, itin> {
  255. let Pattern = pattern;
  256. let CodeSize = 3;
  257. }
  258. class Ii16<bits<8> o, Format f, dag outs, dag ins, string asm,
  259. list<dag> pattern, InstrItinClass itin = NoItinerary>
  260. : X86Inst<o, f, Imm16, outs, ins, asm, itin> {
  261. let Pattern = pattern;
  262. let CodeSize = 3;
  263. }
  264. class Ii32<bits<8> o, Format f, dag outs, dag ins, string asm,
  265. list<dag> pattern, InstrItinClass itin = NoItinerary>
  266. : X86Inst<o, f, Imm32, outs, ins, asm, itin> {
  267. let Pattern = pattern;
  268. let CodeSize = 3;
  269. }
  270. class Ii16PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
  271. list<dag> pattern, InstrItinClass itin = NoItinerary>
  272. : X86Inst<o, f, Imm16PCRel, outs, ins, asm, itin> {
  273. let Pattern = pattern;
  274. let CodeSize = 3;
  275. }
  276. class Ii32PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
  277. list<dag> pattern, InstrItinClass itin = NoItinerary>
  278. : X86Inst<o, f, Imm32PCRel, outs, ins, asm, itin> {
  279. let Pattern = pattern;
  280. let CodeSize = 3;
  281. }
  282. // FPStack Instruction Templates:
  283. // FPI - Floating Point Instruction template.
  284. class FPI<bits<8> o, Format F, dag outs, dag ins, string asm,
  285. InstrItinClass itin = NoItinerary>
  286. : I<o, F, outs, ins, asm, [], itin> {}
  287. // FpI_ - Floating Point Pseudo Instruction template. Not Predicated.
  288. class FpI_<dag outs, dag ins, FPFormat fp, list<dag> pattern,
  289. InstrItinClass itin = NoItinerary>
  290. : X86Inst<0, Pseudo, NoImm, outs, ins, "", itin> {
  291. let FPForm = fp;
  292. let Pattern = pattern;
  293. }
  294. // Templates for instructions that use a 16- or 32-bit segmented address as
  295. // their only operand: lcall (FAR CALL) and ljmp (FAR JMP)
  296. //
  297. // Iseg16 - 16-bit segment selector, 16-bit offset
  298. // Iseg32 - 16-bit segment selector, 32-bit offset
  299. class Iseg16 <bits<8> o, Format f, dag outs, dag ins, string asm,
  300. list<dag> pattern, InstrItinClass itin = NoItinerary>
  301. : X86Inst<o, f, Imm16, outs, ins, asm, itin> {
  302. let Pattern = pattern;
  303. let CodeSize = 3;
  304. }
  305. class Iseg32 <bits<8> o, Format f, dag outs, dag ins, string asm,
  306. list<dag> pattern, InstrItinClass itin = NoItinerary>
  307. : X86Inst<o, f, Imm32, outs, ins, asm, itin> {
  308. let Pattern = pattern;
  309. let CodeSize = 3;
  310. }
  311. def __xs : XS;
  312. def __xd : XD;
  313. // SI - SSE 1 & 2 scalar instructions
  314. class SI<bits<8> o, Format F, dag outs, dag ins, string asm,
  315. list<dag> pattern, InstrItinClass itin = NoItinerary>
  316. : I<o, F, outs, ins, asm, pattern, itin> {
  317. let Predicates = !if(hasEVEXPrefix /* EVEX */, [HasAVX512],
  318. !if(hasVEXPrefix /* VEX */, [UseAVX],
  319. !if(!eq(Prefix, __xs.Prefix), [UseSSE1],
  320. !if(!eq(Prefix, __xd.Prefix), [UseSSE2],
  321. !if(hasOpSizePrefix, [UseSSE2], [UseSSE1])))));
  322. // AVX instructions have a 'v' prefix in the mnemonic
  323. let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm);
  324. }
  325. // SIi8 - SSE 1 & 2 scalar instructions
  326. class SIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
  327. list<dag> pattern, InstrItinClass itin = NoItinerary>
  328. : Ii8<o, F, outs, ins, asm, pattern, itin> {
  329. let Predicates = !if(hasEVEXPrefix /* EVEX */, [HasAVX512],
  330. !if(hasVEXPrefix /* VEX */, [UseAVX],
  331. !if(!eq(Prefix, __xs.Prefix), [UseSSE1], [UseSSE2])));
  332. // AVX instructions have a 'v' prefix in the mnemonic
  333. let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm);
  334. }
  335. // PI - SSE 1 & 2 packed instructions
  336. class PI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern,
  337. InstrItinClass itin, Domain d>
  338. : I<o, F, outs, ins, asm, pattern, itin, d> {
  339. let Predicates = !if(hasEVEXPrefix /* EVEX */, [HasAVX512],
  340. !if(hasVEXPrefix /* VEX */, [HasAVX],
  341. !if(hasOpSizePrefix /* OpSize */, [UseSSE2], [UseSSE1])));
  342. // AVX instructions have a 'v' prefix in the mnemonic
  343. let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm);
  344. }
  345. // MMXPI - SSE 1 & 2 packed instructions with MMX operands
  346. class MMXPI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern,
  347. InstrItinClass itin, Domain d>
  348. : I<o, F, outs, ins, asm, pattern, itin, d> {
  349. let Predicates = !if(hasOpSizePrefix /* OpSize */, [HasSSE2], [HasSSE1]);
  350. }
  351. // PIi8 - SSE 1 & 2 packed instructions with immediate
  352. class PIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
  353. list<dag> pattern, InstrItinClass itin, Domain d>
  354. : Ii8<o, F, outs, ins, asm, pattern, itin, d> {
  355. let Predicates = !if(hasEVEXPrefix /* EVEX */, [HasAVX512],
  356. !if(hasVEXPrefix /* VEX */, [HasAVX],
  357. !if(hasOpSizePrefix /* OpSize */, [UseSSE2], [UseSSE1])));
  358. // AVX instructions have a 'v' prefix in the mnemonic
  359. let AsmString = !if(hasVEXPrefix, !strconcat("v", asm), asm);
  360. }
  361. // SSE1 Instruction Templates:
  362. //
  363. // SSI - SSE1 instructions with XS prefix.
  364. // PSI - SSE1 instructions with TB prefix.
  365. // PSIi8 - SSE1 instructions with ImmT == Imm8 and TB prefix.
  366. // VSSI - SSE1 instructions with XS prefix in AVX form.
  367. // VPSI - SSE1 instructions with TB prefix in AVX form, packed single.
  368. class SSI<bits<8> o, Format F, dag outs, dag ins, string asm,
  369. list<dag> pattern, InstrItinClass itin = NoItinerary>
  370. : I<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[UseSSE1]>;
  371. class SSIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
  372. list<dag> pattern, InstrItinClass itin = NoItinerary>
  373. : Ii8<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[UseSSE1]>;
  374. class PSI<bits<8> o, Format F, dag outs, dag ins, string asm,
  375. list<dag> pattern, InstrItinClass itin = NoItinerary>
  376. : I<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, TB,
  377. Requires<[UseSSE1]>;
  378. class PSIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
  379. list<dag> pattern, InstrItinClass itin = NoItinerary>
  380. : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, TB,
  381. Requires<[UseSSE1]>;
  382. class VSSI<bits<8> o, Format F, dag outs, dag ins, string asm,
  383. list<dag> pattern, InstrItinClass itin = NoItinerary>
  384. : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, XS,
  385. Requires<[HasAVX]>;
  386. class VPSI<bits<8> o, Format F, dag outs, dag ins, string asm,
  387. list<dag> pattern, InstrItinClass itin = NoItinerary>
  388. : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin, SSEPackedSingle>, TB,
  389. Requires<[HasAVX]>;
  390. // SSE2 Instruction Templates:
  391. //
  392. // SDI - SSE2 instructions with XD prefix.
  393. // SDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix.
  394. // S2SI - SSE2 instructions with XS prefix.
  395. // SSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix.
  396. // PDI - SSE2 instructions with TB and OpSize prefixes, packed double domain.
  397. // PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes.
  398. // VSDI - SSE2 scalar instructions with XD prefix in AVX form.
  399. // VPDI - SSE2 vector instructions with TB and OpSize prefixes in AVX form,
  400. // packed double domain.
  401. // VS2I - SSE2 scalar instructions with TB and OpSize prefixes in AVX form.
  402. // S2I - SSE2 scalar instructions with TB and OpSize prefixes.
  403. // MMXSDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix as well as
  404. // MMX operands.
  405. // MMXSSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix as well as
  406. // MMX operands.
  407. class SDI<bits<8> o, Format F, dag outs, dag ins, string asm,
  408. list<dag> pattern, InstrItinClass itin = NoItinerary>
  409. : I<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[UseSSE2]>;
  410. class SDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
  411. list<dag> pattern, InstrItinClass itin = NoItinerary>
  412. : Ii8<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[UseSSE2]>;
  413. class S2SI<bits<8> o, Format F, dag outs, dag ins, string asm,
  414. list<dag> pattern, InstrItinClass itin = NoItinerary>
  415. : I<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[UseSSE2]>;
  416. class S2SIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
  417. list<dag> pattern, InstrItinClass itin = NoItinerary>
  418. : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[UseSSE2]>;
  419. class PDI<bits<8> o, Format F, dag outs, dag ins, string asm,
  420. list<dag> pattern, InstrItinClass itin = NoItinerary>
  421. : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, TB, OpSize,
  422. Requires<[UseSSE2]>;
  423. class PDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
  424. list<dag> pattern, InstrItinClass itin = NoItinerary>
  425. : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, TB, OpSize,
  426. Requires<[UseSSE2]>;
  427. class VSDI<bits<8> o, Format F, dag outs, dag ins, string asm,
  428. list<dag> pattern, InstrItinClass itin = NoItinerary>
  429. : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, XD,
  430. Requires<[UseAVX]>;
  431. class VS2SI<bits<8> o, Format F, dag outs, dag ins, string asm,
  432. list<dag> pattern, InstrItinClass itin = NoItinerary>
  433. : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, XS,
  434. Requires<[HasAVX]>;
  435. class VPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
  436. list<dag> pattern, InstrItinClass itin = NoItinerary>
  437. : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin, SSEPackedDouble>, TB,
  438. OpSize, Requires<[HasAVX]>;
  439. class VS2I<bits<8> o, Format F, dag outs, dag ins, string asm,
  440. list<dag> pattern, InstrItinClass itin = NoItinerary>
  441. : I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, TB,
  442. OpSize, Requires<[UseAVX]>;
  443. class S2I<bits<8> o, Format F, dag outs, dag ins, string asm,
  444. list<dag> pattern, InstrItinClass itin = NoItinerary>
  445. : I<o, F, outs, ins, asm, pattern, itin>, TB,
  446. OpSize, Requires<[UseSSE2]>;
  447. class MMXSDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
  448. list<dag> pattern, InstrItinClass itin = NoItinerary>
  449. : Ii8<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[HasSSE2]>;
  450. class MMXS2SIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
  451. list<dag> pattern, InstrItinClass itin = NoItinerary>
  452. : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE2]>;
  453. // SSE3 Instruction Templates:
  454. //
  455. // S3I - SSE3 instructions with TB and OpSize prefixes.
  456. // S3SI - SSE3 instructions with XS prefix.
  457. // S3DI - SSE3 instructions with XD prefix.
  458. class S3SI<bits<8> o, Format F, dag outs, dag ins, string asm,
  459. list<dag> pattern, InstrItinClass itin = NoItinerary>
  460. : I<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, XS,
  461. Requires<[UseSSE3]>;
  462. class S3DI<bits<8> o, Format F, dag outs, dag ins, string asm,
  463. list<dag> pattern, InstrItinClass itin = NoItinerary>
  464. : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, XD,
  465. Requires<[UseSSE3]>;
  466. class S3I<bits<8> o, Format F, dag outs, dag ins, string asm,
  467. list<dag> pattern, InstrItinClass itin = NoItinerary>
  468. : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, TB, OpSize,
  469. Requires<[UseSSE3]>;
  470. // SSSE3 Instruction Templates:
  471. //
  472. // SS38I - SSSE3 instructions with T8 prefix.
  473. // SS3AI - SSSE3 instructions with TA prefix.
  474. // MMXSS38I - SSSE3 instructions with T8 prefix and MMX operands.
  475. // MMXSS3AI - SSSE3 instructions with TA prefix and MMX operands.
  476. //
  477. // Note: SSSE3 instructions have 64-bit and 128-bit versions. The 64-bit version
  478. // uses the MMX registers. The 64-bit versions are grouped with the MMX
  479. // classes. They need to be enabled even if AVX is enabled.
  480. class SS38I<bits<8> o, Format F, dag outs, dag ins, string asm,
  481. list<dag> pattern, InstrItinClass itin = NoItinerary>
  482. : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8,
  483. Requires<[UseSSSE3]>;
  484. class SS3AI<bits<8> o, Format F, dag outs, dag ins, string asm,
  485. list<dag> pattern, InstrItinClass itin = NoItinerary>
  486. : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
  487. Requires<[UseSSSE3]>;
  488. class MMXSS38I<bits<8> o, Format F, dag outs, dag ins, string asm,
  489. list<dag> pattern, InstrItinClass itin = NoItinerary>
  490. : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8,
  491. Requires<[HasSSSE3]>;
  492. class MMXSS3AI<bits<8> o, Format F, dag outs, dag ins, string asm,
  493. list<dag> pattern, InstrItinClass itin = NoItinerary>
  494. : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
  495. Requires<[HasSSSE3]>;
  496. // SSE4.1 Instruction Templates:
  497. //
  498. // SS48I - SSE 4.1 instructions with T8 prefix.
  499. // SS41AIi8 - SSE 4.1 instructions with TA prefix and ImmT == Imm8.
  500. //
  501. class SS48I<bits<8> o, Format F, dag outs, dag ins, string asm,
  502. list<dag> pattern, InstrItinClass itin = NoItinerary>
  503. : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8,
  504. Requires<[UseSSE41]>;
  505. class SS4AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
  506. list<dag> pattern, InstrItinClass itin = NoItinerary>
  507. : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
  508. Requires<[UseSSE41]>;
  509. // SSE4.2 Instruction Templates:
  510. //
  511. // SS428I - SSE 4.2 instructions with T8 prefix.
  512. class SS428I<bits<8> o, Format F, dag outs, dag ins, string asm,
  513. list<dag> pattern, InstrItinClass itin = NoItinerary>
  514. : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8,
  515. Requires<[UseSSE42]>;
  516. // SS42FI - SSE 4.2 instructions with T8XD prefix.
  517. // NOTE: 'HasSSE42' is used as SS42FI is only used for CRC32 insns.
  518. class SS42FI<bits<8> o, Format F, dag outs, dag ins, string asm,
  519. list<dag> pattern, InstrItinClass itin = NoItinerary>
  520. : I<o, F, outs, ins, asm, pattern, itin>, T8XD, Requires<[HasSSE42]>;
  521. // SS42AI = SSE 4.2 instructions with TA prefix
  522. class SS42AI<bits<8> o, Format F, dag outs, dag ins, string asm,
  523. list<dag> pattern, InstrItinClass itin = NoItinerary>
  524. : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
  525. Requires<[UseSSE42]>;
  526. // AVX Instruction Templates:
  527. // Instructions introduced in AVX (no SSE equivalent forms)
  528. //
  529. // AVX8I - AVX instructions with T8 and OpSize prefix.
  530. // AVXAIi8 - AVX instructions with TA, OpSize prefix and ImmT = Imm8.
  531. class AVX8I<bits<8> o, Format F, dag outs, dag ins, string asm,
  532. list<dag> pattern, InstrItinClass itin = NoItinerary>
  533. : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8, OpSize,
  534. Requires<[HasAVX]>;
  535. class AVXAIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
  536. list<dag> pattern, InstrItinClass itin = NoItinerary>
  537. : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA, OpSize,
  538. Requires<[HasAVX]>;
  539. // AVX2 Instruction Templates:
  540. // Instructions introduced in AVX2 (no SSE equivalent forms)
  541. //
  542. // AVX28I - AVX2 instructions with T8 and OpSize prefix.
  543. // AVX2AIi8 - AVX2 instructions with TA, OpSize prefix and ImmT = Imm8.
  544. class AVX28I<bits<8> o, Format F, dag outs, dag ins, string asm,
  545. list<dag> pattern, InstrItinClass itin = NoItinerary>
  546. : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8, OpSize,
  547. Requires<[HasAVX2]>;
  548. class AVX2AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
  549. list<dag> pattern, InstrItinClass itin = NoItinerary>
  550. : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA, OpSize,
  551. Requires<[HasAVX2]>;
  552. // AVX-512 Instruction Templates:
  553. // Instructions introduced in AVX-512 (no SSE equivalent forms)
  554. //
  555. // AVX5128I - AVX-512 instructions with T8 and OpSize prefix.
  556. // AVX512AIi8 - AVX-512 instructions with TA, OpSize prefix and ImmT = Imm8.
  557. // AVX512PDI - AVX-512 instructions with TB, OpSize, double packed.
  558. // AVX512PSI - AVX-512 instructions with TB, single packed.
  559. // AVX512XS8I - AVX-512 instructions with T8 and XS prefixes.
  560. // AVX512XSI - AVX-512 instructions with XS prefix, generic domain.
  561. // AVX512BI - AVX-512 instructions with TB, OpSize, int packed domain.
  562. // AVX512SI - AVX-512 scalar instructions with TB and OpSize prefixes.
  563. class AVX5128I<bits<8> o, Format F, dag outs, dag ins, string asm,
  564. list<dag> pattern, InstrItinClass itin = NoItinerary>
  565. : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8, OpSize,
  566. Requires<[HasAVX512]>;
  567. class AVX512XS8I<bits<8> o, Format F, dag outs, dag ins, string asm,
  568. list<dag> pattern, InstrItinClass itin = NoItinerary>
  569. : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8XS,
  570. Requires<[HasAVX512]>;
  571. class AVX512XSI<bits<8> o, Format F, dag outs, dag ins, string asm,
  572. list<dag> pattern, InstrItinClass itin = NoItinerary>
  573. : I<o, F, outs, ins, asm, pattern, itin>, XS,
  574. Requires<[HasAVX512]>;
  575. class AVX512XDI<bits<8> o, Format F, dag outs, dag ins, string asm,
  576. list<dag> pattern, InstrItinClass itin = NoItinerary>
  577. : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, XD,
  578. Requires<[HasAVX512]>;
  579. class AVX512BI<bits<8> o, Format F, dag outs, dag ins, string asm,
  580. list<dag> pattern, InstrItinClass itin = NoItinerary>
  581. : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TB, OpSize,
  582. Requires<[HasAVX512]>;
  583. class AVX512BIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
  584. list<dag> pattern, InstrItinClass itin = NoItinerary>
  585. : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TB, OpSize,
  586. Requires<[HasAVX512]>;
  587. class AVX512SI<bits<8> o, Format F, dag outs, dag ins, string asm,
  588. list<dag> pattern, InstrItinClass itin = NoItinerary>
  589. : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TB, OpSize,
  590. Requires<[HasAVX512]>;
  591. class AVX512AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
  592. list<dag> pattern, InstrItinClass itin = NoItinerary>
  593. : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA, OpSize,
  594. Requires<[HasAVX512]>;
  595. class AVX512Ii8<bits<8> o, Format F, dag outs, dag ins, string asm,
  596. list<dag> pattern, InstrItinClass itin = NoItinerary>
  597. : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TB,
  598. Requires<[HasAVX512]>;
  599. class AVX512PDI<bits<8> o, Format F, dag outs, dag ins, string asm,
  600. list<dag> pattern, InstrItinClass itin = NoItinerary>
  601. : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, TB,
  602. OpSize, Requires<[HasAVX512]>;
  603. class AVX512PSI<bits<8> o, Format F, dag outs, dag ins, string asm,
  604. list<dag> pattern, InstrItinClass itin = NoItinerary>
  605. : I<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, TB,
  606. Requires<[HasAVX512]>;
  607. class AVX512PIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
  608. list<dag> pattern, Domain d, InstrItinClass itin = NoItinerary>
  609. : Ii8<o, F, outs, ins, asm, pattern, itin, d>, TB, Requires<[HasAVX512]>;
  610. class AVX512PI<bits<8> o, Format F, dag outs, dag ins, string asm,
  611. list<dag> pattern, Domain d, InstrItinClass itin = NoItinerary>
  612. : I<o, F, outs, ins, asm, pattern, itin, d>, TB, Requires<[HasAVX512]>;
  613. class AVX512FMA3<bits<8> o, Format F, dag outs, dag ins, string asm,
  614. list<dag>pattern, InstrItinClass itin = NoItinerary>
  615. : I<o, F, outs, ins, asm, pattern, itin>, T8,
  616. OpSize, EVEX_4V, Requires<[HasAVX512]>;
  617. // AES Instruction Templates:
  618. //
  619. // AES8I
  620. // These use the same encoding as the SSE4.2 T8 and TA encodings.
  621. class AES8I<bits<8> o, Format F, dag outs, dag ins, string asm,
  622. list<dag>pattern, InstrItinClass itin = IIC_AES>
  623. : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8,
  624. Requires<[HasAES]>;
  625. class AESAI<bits<8> o, Format F, dag outs, dag ins, string asm,
  626. list<dag> pattern, InstrItinClass itin = NoItinerary>
  627. : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
  628. Requires<[HasAES]>;
  629. // PCLMUL Instruction Templates
  630. class PCLMULIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
  631. list<dag>pattern, InstrItinClass itin = NoItinerary>
  632. : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
  633. OpSize, Requires<[HasPCLMUL]>;
  634. class AVXPCLMULIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
  635. list<dag>pattern, InstrItinClass itin = NoItinerary>
  636. : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
  637. OpSize, VEX_4V, Requires<[HasAVX, HasPCLMUL]>;
  638. // FMA3 Instruction Templates
  639. class FMA3<bits<8> o, Format F, dag outs, dag ins, string asm,
  640. list<dag>pattern, InstrItinClass itin = NoItinerary>
  641. : I<o, F, outs, ins, asm, pattern, itin>, T8,
  642. OpSize, VEX_4V, FMASC, Requires<[HasFMA]>;
  643. // FMA4 Instruction Templates
  644. class FMA4<bits<8> o, Format F, dag outs, dag ins, string asm,
  645. list<dag>pattern, InstrItinClass itin = NoItinerary>
  646. : Ii8<o, F, outs, ins, asm, pattern, itin>, TA,
  647. OpSize, VEX_4V, VEX_I8IMM, FMASC, Requires<[HasFMA4]>;
  648. // XOP 2, 3 and 4 Operand Instruction Template
  649. class IXOP<bits<8> o, Format F, dag outs, dag ins, string asm,
  650. list<dag> pattern, InstrItinClass itin = NoItinerary>
  651. : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>,
  652. XOP, XOP9, Requires<[HasXOP]>;
  653. // XOP 2, 3 and 4 Operand Instruction Templates with imm byte
  654. class IXOPi8<bits<8> o, Format F, dag outs, dag ins, string asm,
  655. list<dag> pattern, InstrItinClass itin = NoItinerary>
  656. : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>,
  657. XOP, XOP8, Requires<[HasXOP]>;
  658. // XOP 5 operand instruction (VEX encoding!)
  659. class IXOP5<bits<8> o, Format F, dag outs, dag ins, string asm,
  660. list<dag>pattern, InstrItinClass itin = NoItinerary>
  661. : Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
  662. OpSize, VEX_4V, VEX_I8IMM, Requires<[HasXOP]>;
  663. // X86-64 Instruction templates...
  664. //
  665. class RI<bits<8> o, Format F, dag outs, dag ins, string asm,
  666. list<dag> pattern, InstrItinClass itin = NoItinerary>
  667. : I<o, F, outs, ins, asm, pattern, itin>, REX_W;
  668. class RIi8 <bits<8> o, Format F, dag outs, dag ins, string asm,
  669. list<dag> pattern, InstrItinClass itin = NoItinerary>
  670. : Ii8<o, F, outs, ins, asm, pattern, itin>, REX_W;
  671. class RIi32 <bits<8> o, Format F, dag outs, dag ins, string asm,
  672. list<dag> pattern, InstrItinClass itin = NoItinerary>
  673. : Ii32<o, F, outs, ins, asm, pattern, itin>, REX_W;
  674. class RIi64<bits<8> o, Format f, dag outs, dag ins, string asm,
  675. list<dag> pattern, InstrItinClass itin = NoItinerary>
  676. : X86Inst<o, f, Imm64, outs, ins, asm, itin>, REX_W {
  677. let Pattern = pattern;
  678. let CodeSize = 3;
  679. }
  680. class RIi64_NOREX<bits<8> o, Format f, dag outs, dag ins, string asm,
  681. list<dag> pattern, InstrItinClass itin = NoItinerary>
  682. : X86Inst<o, f, Imm64, outs, ins, asm, itin> {
  683. let Pattern = pattern;
  684. let CodeSize = 3;
  685. }
  686. class RSSI<bits<8> o, Format F, dag outs, dag ins, string asm,
  687. list<dag> pattern, InstrItinClass itin = NoItinerary>
  688. : SSI<o, F, outs, ins, asm, pattern, itin>, REX_W;
  689. class RSDI<bits<8> o, Format F, dag outs, dag ins, string asm,
  690. list<dag> pattern, InstrItinClass itin = NoItinerary>
  691. : SDI<o, F, outs, ins, asm, pattern, itin>, REX_W;
  692. class RPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
  693. list<dag> pattern, InstrItinClass itin = NoItinerary>
  694. : PDI<o, F, outs, ins, asm, pattern, itin>, REX_W;
  695. class VRPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
  696. list<dag> pattern, InstrItinClass itin = NoItinerary>
  697. : VPDI<o, F, outs, ins, asm, pattern, itin>, VEX_W;
  698. class RS2I<bits<8> o, Format F, dag outs, dag ins, string asm,
  699. list<dag> pattern, InstrItinClass itin = NoItinerary>
  700. : S2I<o, F, outs, ins, asm, pattern, itin>, REX_W;
  701. class VRS2I<bits<8> o, Format F, dag outs, dag ins, string asm,
  702. list<dag> pattern, InstrItinClass itin = NoItinerary>
  703. : VS2I<o, F, outs, ins, asm, pattern, itin>, VEX_W;
  704. // MMX Instruction templates
  705. //
  706. // MMXI - MMX instructions with TB prefix.
  707. // MMXI32 - MMX instructions with TB prefix valid only in 32 bit mode.
  708. // MMXI64 - MMX instructions with TB prefix valid only in 64 bit mode.
  709. // MMX2I - MMX / SSE2 instructions with TB and OpSize prefixes.
  710. // MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
  711. // MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
  712. // MMXID - MMX instructions with XD prefix.
  713. // MMXIS - MMX instructions with XS prefix.
  714. class MMXI<bits<8> o, Format F, dag outs, dag ins, string asm,
  715. list<dag> pattern, InstrItinClass itin = NoItinerary>
  716. : I<o, F, outs, ins, asm, pattern, itin>, TB, Requires<[HasMMX]>;
  717. class MMXI32<bits<8> o, Format F, dag outs, dag ins, string asm,
  718. list<dag> pattern, InstrItinClass itin = NoItinerary>
  719. : I<o, F, outs, ins, asm, pattern, itin>, TB, Requires<[HasMMX,In32BitMode]>;
  720. class MMXI64<bits<8> o, Format F, dag outs, dag ins, string asm,
  721. list<dag> pattern, InstrItinClass itin = NoItinerary>
  722. : I<o, F, outs, ins, asm, pattern, itin>, TB, Requires<[HasMMX,In64BitMode]>;
  723. class MMXRI<bits<8> o, Format F, dag outs, dag ins, string asm,
  724. list<dag> pattern, InstrItinClass itin = NoItinerary>
  725. : I<o, F, outs, ins, asm, pattern, itin>, TB, REX_W, Requires<[HasMMX]>;
  726. class MMX2I<bits<8> o, Format F, dag outs, dag ins, string asm,
  727. list<dag> pattern, InstrItinClass itin = NoItinerary>
  728. : I<o, F, outs, ins, asm, pattern, itin>, TB, OpSize, Requires<[HasMMX]>;
  729. class MMXIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
  730. list<dag> pattern, InstrItinClass itin = NoItinerary>
  731. : Ii8<o, F, outs, ins, asm, pattern, itin>, TB, Requires<[HasMMX]>;
  732. class MMXID<bits<8> o, Format F, dag outs, dag ins, string asm,
  733. list<dag> pattern, InstrItinClass itin = NoItinerary>
  734. : Ii8<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[HasMMX]>;
  735. class MMXIS<bits<8> o, Format F, dag outs, dag ins, string asm,
  736. list<dag> pattern, InstrItinClass itin = NoItinerary>
  737. : Ii8<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[HasMMX]>;