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/3rd_party/llvm/lib/Target/Mips/MipsInstrInfo.td

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   1//===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
   2//
   3//                     The LLVM Compiler Infrastructure
   4//
   5// This file is distributed under the University of Illinois Open Source
   6// License. See LICENSE.TXT for details.
   7//
   8//===----------------------------------------------------------------------===//
   9//
  10// This file contains the Mips implementation of the TargetInstrInfo class.
  11//
  12//===----------------------------------------------------------------------===//
  13
  14
  15//===----------------------------------------------------------------------===//
  16// Mips profiles and nodes
  17//===----------------------------------------------------------------------===//
  18
  19def SDT_MipsJmpLink      : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
  20def SDT_MipsCMov         : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
  21                                                SDTCisSameAs<1, 2>,
  22                                                SDTCisSameAs<3, 4>,
  23                                                SDTCisInt<4>]>;
  24def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
  25def SDT_MipsCallSeqEnd   : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
  26def SDT_MFLOHI : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVT<1, untyped>]>;
  27def SDT_MTLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
  28                                      SDTCisInt<1>, SDTCisSameAs<1, 2>]>;
  29def SDT_MipsMultDiv : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, SDTCisInt<1>,
  30                                    SDTCisSameAs<1, 2>]>;
  31def SDT_MipsMAddMSub : SDTypeProfile<1, 3,
  32                                     [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,
  33                                      SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
  34def SDT_MipsDivRem16 : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
  35
  36def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
  37
  38def SDT_Sync             : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
  39
  40def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
  41                                   SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>;
  42def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
  43                                   SDTCisVT<2, i32>, SDTCisSameAs<2, 3>,
  44                                   SDTCisSameAs<0, 4>]>;
  45
  46def SDTMipsLoadLR  : SDTypeProfile<1, 2,
  47                                   [SDTCisInt<0>, SDTCisPtrTy<1>,
  48                                    SDTCisSameAs<0, 2>]>;
  49
  50// Call
  51def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
  52                         [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
  53                          SDNPVariadic]>;
  54
  55// Tail call
  56def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink,
  57                          [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
  58
  59// Hi and Lo nodes are used to handle global addresses. Used on
  60// MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
  61// static model. (nothing to do with Mips Registers Hi and Lo)
  62def MipsHi    : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
  63def MipsLo    : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
  64def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
  65
  66// TlsGd node is used to handle General Dynamic TLS
  67def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
  68
  69// TprelHi and TprelLo nodes are used to handle Local Exec TLS
  70def MipsTprelHi    : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
  71def MipsTprelLo    : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
  72
  73// Thread pointer
  74def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
  75
  76// Return
  77def MipsRet : SDNode<"MipsISD::Ret", SDTNone,
  78                     [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
  79
  80// These are target-independent nodes, but have target-specific formats.
  81def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
  82                           [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
  83def callseq_end   : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
  84                           [SDNPHasChain, SDNPSideEffect,
  85                            SDNPOptInGlue, SDNPOutGlue]>;
  86
  87// Nodes used to extract LO/HI registers.
  88def MipsMFHI : SDNode<"MipsISD::MFHI", SDT_MFLOHI>;
  89def MipsMFLO : SDNode<"MipsISD::MFLO", SDT_MFLOHI>;
  90
  91// Node used to insert 32-bit integers to LOHI register pair.
  92def MipsMTLOHI : SDNode<"MipsISD::MTLOHI", SDT_MTLOHI>;
  93
  94// Mult nodes.
  95def MipsMult  : SDNode<"MipsISD::Mult", SDT_MipsMultDiv>;
  96def MipsMultu : SDNode<"MipsISD::Multu", SDT_MipsMultDiv>;
  97
  98// MAdd*/MSub* nodes
  99def MipsMAdd  : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub>;
 100def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub>;
 101def MipsMSub  : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub>;
 102def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub>;
 103
 104// DivRem(u) nodes
 105def MipsDivRem    : SDNode<"MipsISD::DivRem", SDT_MipsMultDiv>;
 106def MipsDivRemU   : SDNode<"MipsISD::DivRemU", SDT_MipsMultDiv>;
 107def MipsDivRem16  : SDNode<"MipsISD::DivRem16", SDT_MipsDivRem16,
 108                           [SDNPOutGlue]>;
 109def MipsDivRemU16 : SDNode<"MipsISD::DivRemU16", SDT_MipsDivRem16,
 110                           [SDNPOutGlue]>;
 111
 112// Target constant nodes that are not part of any isel patterns and remain
 113// unchanged can cause instructions with illegal operands to be emitted.
 114// Wrapper node patterns give the instruction selector a chance to replace
 115// target constant nodes that would otherwise remain unchanged with ADDiu
 116// nodes. Without these wrapper node patterns, the following conditional move
 117// instruction is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
 118// compiled:
 119//  movn  %got(d)($gp), %got(c)($gp), $4
 120// This instruction is illegal since movn can take only register operands.
 121
 122def MipsWrapper    : SDNode<"MipsISD::Wrapper", SDTIntBinOp>;
 123
 124def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>;
 125
 126def MipsExt :  SDNode<"MipsISD::Ext", SDT_Ext>;
 127def MipsIns :  SDNode<"MipsISD::Ins", SDT_Ins>;
 128
 129def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR,
 130                     [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
 131def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR,
 132                     [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
 133def MipsSWL : SDNode<"MipsISD::SWL", SDTStore,
 134                     [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
 135def MipsSWR : SDNode<"MipsISD::SWR", SDTStore,
 136                     [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
 137def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR,
 138                     [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
 139def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR,
 140                     [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
 141def MipsSDL : SDNode<"MipsISD::SDL", SDTStore,
 142                     [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
 143def MipsSDR : SDNode<"MipsISD::SDR", SDTStore,
 144                     [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
 145
 146//===----------------------------------------------------------------------===//
 147// Mips Instruction Predicate Definitions.
 148//===----------------------------------------------------------------------===//
 149def HasSEInReg  :     Predicate<"Subtarget.hasSEInReg()">,
 150                      AssemblerPredicate<"FeatureSEInReg">;
 151def HasBitCount :     Predicate<"Subtarget.hasBitCount()">,
 152                      AssemblerPredicate<"FeatureBitCount">;
 153def HasSwap     :     Predicate<"Subtarget.hasSwap()">,
 154                      AssemblerPredicate<"FeatureSwap">;
 155def HasCondMov  :     Predicate<"Subtarget.hasCondMov()">,
 156                      AssemblerPredicate<"FeatureCondMov">;
 157def HasFPIdx    :     Predicate<"Subtarget.hasFPIdx()">,
 158                      AssemblerPredicate<"FeatureFPIdx">;
 159def HasMips32    :    Predicate<"Subtarget.hasMips32()">,
 160                      AssemblerPredicate<"FeatureMips32">;
 161def HasMips32r2  :    Predicate<"Subtarget.hasMips32r2()">,
 162                      AssemblerPredicate<"FeatureMips32r2">;
 163def HasMips64    :    Predicate<"Subtarget.hasMips64()">,
 164                      AssemblerPredicate<"FeatureMips64">;
 165def NotMips64    :    Predicate<"!Subtarget.hasMips64()">,
 166                      AssemblerPredicate<"!FeatureMips64">;
 167def HasMips64r2  :    Predicate<"Subtarget.hasMips64r2()">,
 168                      AssemblerPredicate<"FeatureMips64r2">;
 169def IsN64       :     Predicate<"Subtarget.isABI_N64()">,
 170                      AssemblerPredicate<"FeatureN64">;
 171def NotN64      :     Predicate<"!Subtarget.isABI_N64()">,
 172                      AssemblerPredicate<"!FeatureN64">;
 173def InMips16Mode :    Predicate<"Subtarget.inMips16Mode()">,
 174                      AssemblerPredicate<"FeatureMips16">;
 175def RelocStatic :     Predicate<"TM.getRelocationModel() == Reloc::Static">,
 176                      AssemblerPredicate<"FeatureMips32">;
 177def RelocPIC    :     Predicate<"TM.getRelocationModel() == Reloc::PIC_">,
 178                      AssemblerPredicate<"FeatureMips32">;
 179def NoNaNsFPMath :    Predicate<"TM.Options.NoNaNsFPMath">,
 180                      AssemblerPredicate<"FeatureMips32">;
 181def HasStdEnc :       Predicate<"Subtarget.hasStandardEncoding()">,
 182                      AssemblerPredicate<"!FeatureMips16">;
 183def NotDSP :          Predicate<"!Subtarget.hasDSP()">;
 184def InMicroMips    :  Predicate<"Subtarget.inMicroMipsMode()">,
 185                      AssemblerPredicate<"FeatureMicroMips">;
 186def NotInMicroMips :  Predicate<"!Subtarget.inMicroMipsMode()">,
 187                      AssemblerPredicate<"!FeatureMicroMips">;
 188def IsLE           :  Predicate<"Subtarget.isLittle()">;
 189def IsBE           :  Predicate<"!Subtarget.isLittle()">;
 190
 191class MipsPat<dag pattern, dag result> : Pat<pattern, result> {
 192  let Predicates = [HasStdEnc];
 193}
 194
 195class IsCommutable {
 196  bit isCommutable = 1;
 197}
 198
 199class IsBranch {
 200  bit isBranch = 1;
 201}
 202
 203class IsReturn {
 204  bit isReturn = 1;
 205}
 206
 207class IsCall {
 208  bit isCall = 1;
 209}
 210
 211class IsTailCall {
 212  bit isCall = 1;
 213  bit isTerminator = 1;
 214  bit isReturn = 1;
 215  bit isBarrier = 1;
 216  bit hasExtraSrcRegAllocReq = 1;
 217  bit isCodeGenOnly = 1;
 218}
 219
 220class IsAsCheapAsAMove {
 221  bit isAsCheapAsAMove = 1;
 222}
 223
 224class NeverHasSideEffects {
 225  bit neverHasSideEffects = 1;
 226}
 227
 228//===----------------------------------------------------------------------===//
 229// Instruction format superclass
 230//===----------------------------------------------------------------------===//
 231
 232include "MipsInstrFormats.td"
 233
 234//===----------------------------------------------------------------------===//
 235// Mips Operand, Complex Patterns and Transformations Definitions.
 236//===----------------------------------------------------------------------===//
 237
 238// Instruction operand types
 239def jmptarget   : Operand<OtherVT> {
 240  let EncoderMethod = "getJumpTargetOpValue";
 241}
 242def brtarget    : Operand<OtherVT> {
 243  let EncoderMethod = "getBranchTargetOpValue";
 244  let OperandType = "OPERAND_PCREL";
 245  let DecoderMethod = "DecodeBranchTarget";
 246}
 247def calltarget  : Operand<iPTR> {
 248  let EncoderMethod = "getJumpTargetOpValue";
 249}
 250
 251def simm16      : Operand<i32> {
 252  let DecoderMethod= "DecodeSimm16";
 253}
 254
 255def simm20      : Operand<i32> {
 256}
 257
 258def uimm20      : Operand<i32> {
 259}
 260
 261def uimm10      : Operand<i32> {
 262}
 263
 264def simm16_64   : Operand<i64> {
 265  let DecoderMethod = "DecodeSimm16";
 266}
 267
 268// Unsigned Operand
 269def uimm5       : Operand<i32> {
 270  let PrintMethod = "printUnsignedImm";
 271}
 272
 273def uimm6 : Operand<i32> {
 274  let PrintMethod = "printUnsignedImm";
 275}
 276
 277def uimm16      : Operand<i32> {
 278  let PrintMethod = "printUnsignedImm";
 279}
 280
 281def pcrel16      : Operand<i32> {
 282}
 283
 284def MipsMemAsmOperand : AsmOperandClass {
 285  let Name = "Mem";
 286  let ParserMethod = "parseMemOperand";
 287}
 288
 289def MipsInvertedImmoperand : AsmOperandClass {
 290  let Name = "InvNum";
 291  let RenderMethod = "addImmOperands";
 292  let ParserMethod = "parseInvNum";
 293}
 294
 295def PtrRegAsmOperand : AsmOperandClass {
 296  let Name = "PtrReg";
 297  let ParserMethod = "parsePtrReg";
 298}
 299
 300
 301def InvertedImOperand : Operand<i32> {
 302  let ParserMatchClass = MipsInvertedImmoperand;
 303}
 304
 305// Address operand
 306def mem : Operand<iPTR> {
 307  let PrintMethod = "printMemOperand";
 308  let MIOperandInfo = (ops ptr_rc, simm16);
 309  let EncoderMethod = "getMemEncoding";
 310  let ParserMatchClass = MipsMemAsmOperand;
 311  let OperandType = "OPERAND_MEMORY";
 312}
 313
 314def mem_ea : Operand<iPTR> {
 315  let PrintMethod = "printMemOperandEA";
 316  let MIOperandInfo = (ops ptr_rc, simm16);
 317  let EncoderMethod = "getMemEncoding";
 318  let OperandType = "OPERAND_MEMORY";
 319}
 320
 321def PtrRC : Operand<iPTR> {
 322  let MIOperandInfo = (ops ptr_rc);
 323  let DecoderMethod = "DecodePtrRegisterClass";
 324  let ParserMatchClass = PtrRegAsmOperand;
 325}
 326
 327// size operand of ext instruction
 328def size_ext : Operand<i32> {
 329  let EncoderMethod = "getSizeExtEncoding";
 330  let DecoderMethod = "DecodeExtSize";
 331}
 332
 333// size operand of ins instruction
 334def size_ins : Operand<i32> {
 335  let EncoderMethod = "getSizeInsEncoding";
 336  let DecoderMethod = "DecodeInsSize";
 337}
 338
 339// Transformation Function - get the lower 16 bits.
 340def LO16 : SDNodeXForm<imm, [{
 341  return getImm(N, N->getZExtValue() & 0xFFFF);
 342}]>;
 343
 344// Transformation Function - get the higher 16 bits.
 345def HI16 : SDNodeXForm<imm, [{
 346  return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);
 347}]>;
 348
 349// Plus 1.
 350def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>;
 351
 352// Node immediate fits as 16-bit sign extended on target immediate.
 353// e.g. addi, andi
 354def immSExt8  : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>;
 355
 356// Node immediate fits as 16-bit sign extended on target immediate.
 357// e.g. addi, andi
 358def immSExt16  : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
 359
 360// Node immediate fits as 15-bit sign extended on target immediate.
 361// e.g. addi, andi
 362def immSExt15  : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>;
 363
 364// Node immediate fits as 16-bit zero extended on target immediate.
 365// The LO16 param means that only the lower 16 bits of the node
 366// immediate are caught.
 367// e.g. addiu, sltiu
 368def immZExt16  : PatLeaf<(imm), [{
 369  if (N->getValueType(0) == MVT::i32)
 370    return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
 371  else
 372    return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
 373}], LO16>;
 374
 375// Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared).
 376def immLow16Zero : PatLeaf<(imm), [{
 377  int64_t Val = N->getSExtValue();
 378  return isInt<32>(Val) && !(Val & 0xffff);
 379}]>;
 380
 381// shamt field must fit in 5 bits.
 382def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
 383
 384// True if (N + 1) fits in 16-bit field.
 385def immSExt16Plus1 : PatLeaf<(imm), [{
 386  return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1);
 387}]>;
 388
 389// Mips Address Mode! SDNode frameindex could possibily be a match
 390// since load and store instructions from stack used it.
 391def addr :
 392  ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>;
 393
 394def addrRegImm :
 395  ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>;
 396
 397def addrRegReg :
 398  ComplexPattern<iPTR, 2, "selectAddrRegReg", [frameindex]>;
 399
 400def addrDefault :
 401  ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>;
 402
 403//===----------------------------------------------------------------------===//
 404// Instructions specific format
 405//===----------------------------------------------------------------------===//
 406
 407// Arithmetic and logical instructions with 3 register operands.
 408class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0,
 409                  InstrItinClass Itin = NoItinerary,
 410                  SDPatternOperator OpNode = null_frag>:
 411  InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
 412         !strconcat(opstr, "\t$rd, $rs, $rt"),
 413         [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
 414  let isCommutable = isComm;
 415  let isReMaterializable = 1;
 416}
 417
 418// Arithmetic and logical instructions with 2 register operands.
 419class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
 420                  InstrItinClass Itin = NoItinerary,
 421                  SDPatternOperator imm_type = null_frag,
 422                  SDPatternOperator OpNode = null_frag> :
 423  InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16),
 424         !strconcat(opstr, "\t$rt, $rs, $imm16"),
 425         [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
 426         Itin, FrmI, opstr> {
 427  let isReMaterializable = 1;
 428  let TwoOperandAliasConstraint = "$rs = $rt";
 429}
 430
 431// Arithmetic Multiply ADD/SUB
 432class MArithR<string opstr, bit isComm = 0> :
 433  InstSE<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
 434         !strconcat(opstr, "\t$rs, $rt"), [], IIImult, FrmR, opstr> {
 435  let Defs = [HI0, LO0];
 436  let Uses = [HI0, LO0];
 437  let isCommutable = isComm;
 438}
 439
 440//  Logical
 441class LogicNOR<string opstr, RegisterOperand RO>:
 442  InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
 443         !strconcat(opstr, "\t$rd, $rs, $rt"),
 444         [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], IIArith, FrmR, opstr> {
 445  let isCommutable = 1;
 446}
 447
 448// Shifts
 449class shift_rotate_imm<string opstr, Operand ImmOpnd,
 450                       RegisterOperand RO, SDPatternOperator OpNode = null_frag,
 451                       SDPatternOperator PF = null_frag> :
 452  InstSE<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
 453         !strconcat(opstr, "\t$rd, $rt, $shamt"),
 454         [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], IIArith, FrmR, opstr>;
 455
 456class shift_rotate_reg<string opstr, RegisterOperand RO,
 457                       SDPatternOperator OpNode = null_frag>:
 458  InstSE<(outs RO:$rd), (ins RO:$rt, GPR32Opnd:$rs),
 459         !strconcat(opstr, "\t$rd, $rt, $rs"),
 460         [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], IIArith, FrmR, opstr>;
 461
 462// Load Upper Imediate
 463class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>:
 464  InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"),
 465         [], IIArith, FrmI, opstr>, IsAsCheapAsAMove {
 466  let neverHasSideEffects = 1;
 467  let isReMaterializable = 1;
 468}
 469
 470// Memory Load/Store
 471class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
 472           InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
 473  InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
 474         [(set RO:$rt, (OpNode Addr:$addr))], Itin, FrmI, opstr> {
 475  let DecoderMethod = "DecodeMem";
 476  let canFoldAsLoad = 1;
 477  let mayLoad = 1;
 478}
 479
 480class Store<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
 481            InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
 482  InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
 483         [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
 484  let DecoderMethod = "DecodeMem";
 485  let mayStore = 1;
 486}
 487
 488// Load/Store Left/Right
 489let canFoldAsLoad = 1 in
 490class LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
 491                    InstrItinClass Itin> :
 492  InstSE<(outs RO:$rt), (ins mem:$addr, RO:$src),
 493         !strconcat(opstr, "\t$rt, $addr"),
 494         [(set RO:$rt, (OpNode addr:$addr, RO:$src))], Itin, FrmI> {
 495  let DecoderMethod = "DecodeMem";
 496  string Constraints = "$src = $rt";
 497}
 498
 499class StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
 500                     InstrItinClass Itin> :
 501  InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
 502         [(OpNode RO:$rt, addr:$addr)], Itin, FrmI> {
 503  let DecoderMethod = "DecodeMem";
 504}
 505
 506// Conditional Branch
 507class CBranch<string opstr, DAGOperand opnd, PatFrag cond_op,
 508              RegisterOperand RO> :
 509  InstSE<(outs), (ins RO:$rs, RO:$rt, opnd:$offset),
 510         !strconcat(opstr, "\t$rs, $rt, $offset"),
 511         [(brcond (i32 (cond_op RO:$rs, RO:$rt)), bb:$offset)], IIBranch,
 512         FrmI, opstr> {
 513  let isBranch = 1;
 514  let isTerminator = 1;
 515  let hasDelaySlot = 1;
 516  let Defs = [AT];
 517}
 518
 519class CBranchZero<string opstr, DAGOperand opnd, PatFrag cond_op,
 520                  RegisterOperand RO> :
 521  InstSE<(outs), (ins RO:$rs, opnd:$offset),
 522         !strconcat(opstr, "\t$rs, $offset"),
 523         [(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)], IIBranch,
 524         FrmI, opstr> {
 525  let isBranch = 1;
 526  let isTerminator = 1;
 527  let hasDelaySlot = 1;
 528  let Defs = [AT];
 529}
 530
 531// SetCC
 532class SetCC_R<string opstr, PatFrag cond_op, RegisterOperand RO> :
 533  InstSE<(outs GPR32Opnd:$rd), (ins RO:$rs, RO:$rt),
 534         !strconcat(opstr, "\t$rd, $rs, $rt"),
 535         [(set GPR32Opnd:$rd, (cond_op RO:$rs, RO:$rt))],
 536         IIslt, FrmR, opstr>;
 537
 538class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type,
 539              RegisterOperand RO>:
 540  InstSE<(outs GPR32Opnd:$rt), (ins RO:$rs, Od:$imm16),
 541         !strconcat(opstr, "\t$rt, $rs, $imm16"),
 542         [(set GPR32Opnd:$rt, (cond_op RO:$rs, imm_type:$imm16))],
 543         IIslt, FrmI, opstr>;
 544
 545// Jump
 546class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator,
 547             SDPatternOperator targetoperator, string bopstr> :
 548  InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
 549         [(operator targetoperator:$target)], IIBranch, FrmJ, bopstr> {
 550  let isTerminator=1;
 551  let isBarrier=1;
 552  let hasDelaySlot = 1;
 553  let DecoderMethod = "DecodeJumpTarget";
 554  let Defs = [AT];
 555}
 556
 557// Unconditional branch
 558class UncondBranch<Instruction BEQInst> :
 559  PseudoSE<(outs), (ins brtarget:$offset), [(br bb:$offset)], IIBranch>,
 560  PseudoInstExpansion<(BEQInst ZERO, ZERO, brtarget:$offset)> {
 561  let isBranch = 1;
 562  let isTerminator = 1;
 563  let isBarrier = 1;
 564  let hasDelaySlot = 1;
 565  let Predicates = [RelocPIC, HasStdEnc];
 566  let Defs = [AT];
 567}
 568
 569// Base class for indirect branch and return instruction classes.
 570let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
 571class JumpFR<string opstr, RegisterOperand RO,
 572             SDPatternOperator operator = null_frag>:
 573  InstSE<(outs), (ins RO:$rs), "jr\t$rs", [(operator RO:$rs)], IIBranch,
 574         FrmR, opstr>;
 575
 576// Indirect branch
 577class IndirectBranch<string opstr, RegisterOperand RO> :
 578      JumpFR<opstr, RO, brind> {
 579  let isBranch = 1;
 580  let isIndirectBranch = 1;
 581}
 582
 583// Return instruction
 584class RetBase<string opstr, RegisterOperand RO>: JumpFR<opstr, RO> {
 585  let isReturn = 1;
 586  let isCodeGenOnly = 1;
 587  let hasCtrlDep = 1;
 588  let hasExtraSrcRegAllocReq = 1;
 589}
 590
 591// Jump and Link (Call)
 592let isCall=1, hasDelaySlot=1, Defs = [RA] in {
 593  class JumpLink<string opstr, DAGOperand opnd> :
 594    InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
 595           [(MipsJmpLink imm:$target)], IIBranch, FrmJ, opstr> {
 596    let DecoderMethod = "DecodeJumpTarget";
 597  }
 598
 599  class JumpLinkRegPseudo<RegisterOperand RO, Instruction JALRInst,
 600                          Register RetReg, RegisterOperand ResRO = RO>:
 601    PseudoSE<(outs), (ins RO:$rs), [(MipsJmpLink RO:$rs)], IIBranch>,
 602    PseudoInstExpansion<(JALRInst RetReg, ResRO:$rs)>;
 603
 604  class JumpLinkReg<string opstr, RegisterOperand RO>:
 605    InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
 606           [], IIBranch, FrmR, opstr>;
 607
 608  class BGEZAL_FT<string opstr, DAGOperand opnd, RegisterOperand RO> :
 609    InstSE<(outs), (ins RO:$rs, opnd:$offset),
 610           !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI, opstr>;
 611
 612}
 613
 614class BAL_BR_Pseudo<Instruction RealInst> :
 615  PseudoSE<(outs), (ins brtarget:$offset), [], IIBranch>,
 616  PseudoInstExpansion<(RealInst ZERO, brtarget:$offset)> {
 617  let isBranch = 1;
 618  let isTerminator = 1;
 619  let isBarrier = 1;
 620  let hasDelaySlot = 1;
 621  let Defs = [RA];
 622}
 623
 624// Syscall
 625class SYS_FT<string opstr> :
 626  InstSE<(outs), (ins uimm20:$code_),
 627         !strconcat(opstr, "\t$code_"), [], NoItinerary, FrmI>;
 628// Break
 629class BRK_FT<string opstr> :
 630  InstSE<(outs), (ins uimm10:$code_1, uimm10:$code_2),
 631         !strconcat(opstr, "\t$code_1, $code_2"), [], NoItinerary, FrmOther>;
 632
 633// (D)Eret
 634class ER_FT<string opstr> :
 635  InstSE<(outs), (ins),
 636         opstr, [], NoItinerary, FrmOther>;
 637
 638// Interrupts
 639class DEI_FT<string opstr, RegisterOperand RO> :
 640  InstSE<(outs RO:$rt), (ins),
 641         !strconcat(opstr, "\t$rt"), [], NoItinerary, FrmOther>;
 642
 643// Wait
 644class WAIT_FT<string opstr> :
 645  InstSE<(outs), (ins), opstr, [], NoItinerary, FrmOther> {
 646  let Inst{31-26} = 0x10;
 647  let Inst{25}    = 1;
 648  let Inst{24-6}  = 0;
 649  let Inst{5-0}   = 0x20;
 650}
 651
 652// Sync
 653let hasSideEffects = 1 in
 654class SYNC_FT :
 655  InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)],
 656         NoItinerary, FrmOther>;
 657
 658let hasSideEffects = 1 in
 659class TEQ_FT<string opstr, RegisterOperand RO> :
 660  InstSE<(outs), (ins RO:$rs, RO:$rt, uimm16:$code_),
 661         !strconcat(opstr, "\t$rs, $rt, $code_"), [], NoItinerary,
 662         FrmI, opstr>;
 663
 664class TEQI_FT<string opstr, RegisterOperand RO> :
 665  InstSE<(outs), (ins RO:$rs, uimm16:$imm16),
 666         !strconcat(opstr, "\t$rs, $imm16"), [], NoItinerary, FrmOther, opstr>;
 667// Mul, Div
 668class Mult<string opstr, InstrItinClass itin, RegisterOperand RO,
 669           list<Register> DefRegs> :
 670  InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [],
 671         itin, FrmR, opstr> {
 672  let isCommutable = 1;
 673  let Defs = DefRegs;
 674  let neverHasSideEffects = 1;
 675}
 676
 677// Pseudo multiply/divide instruction with explicit accumulator register
 678// operands.
 679class MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1,
 680                    SDPatternOperator OpNode, InstrItinClass Itin,
 681                    bit IsComm = 1, bit HasSideEffects = 0,
 682                    bit UsesCustomInserter = 0> :
 683  PseudoSE<(outs R0:$ac), (ins R1:$rs, R1:$rt),
 684           [(set R0:$ac, (OpNode R1:$rs, R1:$rt))], Itin>,
 685  PseudoInstExpansion<(RealInst R1:$rs, R1:$rt)> {
 686  let isCommutable = IsComm;
 687  let hasSideEffects = HasSideEffects;
 688  let usesCustomInserter = UsesCustomInserter;
 689}
 690
 691// Pseudo multiply add/sub instruction with explicit accumulator register
 692// operands.
 693class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode>
 694  : PseudoSE<(outs ACC64:$ac),
 695             (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin),
 696             [(set ACC64:$ac,
 697              (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin))],
 698             IIImult>,
 699    PseudoInstExpansion<(RealInst GPR32Opnd:$rs, GPR32Opnd:$rt)> {
 700  string Constraints = "$acin = $ac";
 701}
 702
 703class Div<string opstr, InstrItinClass itin, RegisterOperand RO,
 704          list<Register> DefRegs> :
 705  InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"),
 706         [], itin, FrmR, opstr> {
 707  let Defs = DefRegs;
 708}
 709
 710// Move from Hi/Lo
 711class PseudoMFLOHI<RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode>
 712  : PseudoSE<(outs DstRC:$rd), (ins SrcRC:$hilo),
 713             [(set DstRC:$rd, (OpNode SrcRC:$hilo))], IIHiLo>;
 714
 715class MoveFromLOHI<string opstr, RegisterOperand RO, Register UseReg>:
 716  InstSE<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), [], IIHiLo, FrmR,
 717         opstr> {
 718  let Uses = [UseReg];
 719  let neverHasSideEffects = 1;
 720}
 721
 722class PseudoMTLOHI<RegisterClass DstRC, RegisterClass SrcRC>
 723  : PseudoSE<(outs DstRC:$lohi), (ins SrcRC:$lo, SrcRC:$hi),
 724             [(set DstRC:$lohi, (MipsMTLOHI SrcRC:$lo, SrcRC:$hi))], IIHiLo>;
 725
 726class MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>:
 727  InstSE<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), [], IIHiLo,
 728  FrmR, opstr> {
 729  let Defs = DefRegs;
 730  let neverHasSideEffects = 1;
 731}
 732
 733class EffectiveAddress<string opstr, RegisterOperand RO> :
 734  InstSE<(outs RO:$rt), (ins mem_ea:$addr), !strconcat(opstr, "\t$rt, $addr"),
 735         [(set RO:$rt, addr:$addr)], NoItinerary, FrmI> {
 736  let isCodeGenOnly = 1;
 737  let DecoderMethod = "DecodeMem";
 738}
 739
 740// Count Leading Ones/Zeros in Word
 741class CountLeading0<string opstr, RegisterOperand RO>:
 742  InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
 743         [(set RO:$rd, (ctlz RO:$rs))], IIArith, FrmR, opstr>,
 744  Requires<[HasBitCount, HasStdEnc]>;
 745
 746class CountLeading1<string opstr, RegisterOperand RO>:
 747  InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
 748         [(set RO:$rd, (ctlz (not RO:$rs)))], IIArith, FrmR, opstr>,
 749  Requires<[HasBitCount, HasStdEnc]>;
 750
 751
 752// Sign Extend in Register.
 753class SignExtInReg<string opstr, ValueType vt, RegisterOperand RO> :
 754  InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"),
 755         [(set RO:$rd, (sext_inreg RO:$rt, vt))], IIseb, FrmR, opstr> {
 756  let Predicates = [HasSEInReg, HasStdEnc];
 757}
 758
 759// Subword Swap
 760class SubwordSwap<string opstr, RegisterOperand RO>:
 761  InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [],
 762         NoItinerary, FrmR, opstr> {
 763  let Predicates = [HasSwap, HasStdEnc];
 764  let neverHasSideEffects = 1;
 765}
 766
 767// Read Hardware
 768class ReadHardware<RegisterOperand CPURegOperand, RegisterOperand RO> :
 769  InstSE<(outs CPURegOperand:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [],
 770         IIArith, FrmR>;
 771
 772// Ext and Ins
 773class ExtBase<string opstr, RegisterOperand RO, Operand PosOpnd,
 774              SDPatternOperator Op = null_frag>:
 775  InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ext:$size),
 776         !strconcat(opstr, " $rt, $rs, $pos, $size"),
 777         [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))], NoItinerary,
 778         FrmR, opstr> {
 779  let Predicates = [HasMips32r2, HasStdEnc];
 780}
 781
 782class InsBase<string opstr, RegisterOperand RO, Operand PosOpnd,
 783              SDPatternOperator Op = null_frag>:
 784  InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ins:$size, RO:$src),
 785         !strconcat(opstr, " $rt, $rs, $pos, $size"),
 786         [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size, RO:$src))],
 787         NoItinerary, FrmR, opstr> {
 788  let Predicates = [HasMips32r2, HasStdEnc];
 789  let Constraints = "$src = $rt";
 790}
 791
 792// Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
 793class Atomic2Ops<PatFrag Op, RegisterClass DRC> :
 794  PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$incr),
 795           [(set DRC:$dst, (Op iPTR:$ptr, DRC:$incr))]>;
 796
 797// Atomic Compare & Swap.
 798class AtomicCmpSwap<PatFrag Op, RegisterClass DRC> :
 799  PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$cmp, DRC:$swap),
 800           [(set DRC:$dst, (Op iPTR:$ptr, DRC:$cmp, DRC:$swap))]>;
 801
 802class LLBase<string opstr, RegisterOperand RO> :
 803  InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
 804         [], NoItinerary, FrmI> {
 805  let DecoderMethod = "DecodeMem";
 806  let mayLoad = 1;
 807}
 808
 809class SCBase<string opstr, RegisterOperand RO> :
 810  InstSE<(outs RO:$dst), (ins RO:$rt, mem:$addr),
 811         !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
 812  let DecoderMethod = "DecodeMem";
 813  let mayStore = 1;
 814  let Constraints = "$rt = $dst";
 815}
 816
 817class MFC3OP<string asmstr, RegisterOperand RO> :
 818  InstSE<(outs RO:$rt, RO:$rd, uimm16:$sel), (ins),
 819         !strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>;
 820
 821class TrapBase<Instruction RealInst>
 822  : PseudoSE<(outs), (ins), [(trap)], NoItinerary>,
 823    PseudoInstExpansion<(RealInst 0, 0)> {
 824  let isBarrier = 1;
 825  let isTerminator = 1;
 826  let isCodeGenOnly = 1;
 827}
 828
 829//===----------------------------------------------------------------------===//
 830// Pseudo instructions
 831//===----------------------------------------------------------------------===//
 832
 833// Return RA.
 834let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in
 835def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>;
 836
 837let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
 838def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt),
 839                                  [(callseq_start timm:$amt)]>;
 840def ADJCALLSTACKUP   : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
 841                                  [(callseq_end timm:$amt1, timm:$amt2)]>;
 842}
 843
 844let usesCustomInserter = 1 in {
 845  def ATOMIC_LOAD_ADD_I8   : Atomic2Ops<atomic_load_add_8, GPR32>;
 846  def ATOMIC_LOAD_ADD_I16  : Atomic2Ops<atomic_load_add_16, GPR32>;
 847  def ATOMIC_LOAD_ADD_I32  : Atomic2Ops<atomic_load_add_32, GPR32>;
 848  def ATOMIC_LOAD_SUB_I8   : Atomic2Ops<atomic_load_sub_8, GPR32>;
 849  def ATOMIC_LOAD_SUB_I16  : Atomic2Ops<atomic_load_sub_16, GPR32>;
 850  def ATOMIC_LOAD_SUB_I32  : Atomic2Ops<atomic_load_sub_32, GPR32>;
 851  def ATOMIC_LOAD_AND_I8   : Atomic2Ops<atomic_load_and_8, GPR32>;
 852  def ATOMIC_LOAD_AND_I16  : Atomic2Ops<atomic_load_and_16, GPR32>;
 853  def ATOMIC_LOAD_AND_I32  : Atomic2Ops<atomic_load_and_32, GPR32>;
 854  def ATOMIC_LOAD_OR_I8    : Atomic2Ops<atomic_load_or_8, GPR32>;
 855  def ATOMIC_LOAD_OR_I16   : Atomic2Ops<atomic_load_or_16, GPR32>;
 856  def ATOMIC_LOAD_OR_I32   : Atomic2Ops<atomic_load_or_32, GPR32>;
 857  def ATOMIC_LOAD_XOR_I8   : Atomic2Ops<atomic_load_xor_8, GPR32>;
 858  def ATOMIC_LOAD_XOR_I16  : Atomic2Ops<atomic_load_xor_16, GPR32>;
 859  def ATOMIC_LOAD_XOR_I32  : Atomic2Ops<atomic_load_xor_32, GPR32>;
 860  def ATOMIC_LOAD_NAND_I8  : Atomic2Ops<atomic_load_nand_8, GPR32>;
 861  def ATOMIC_LOAD_NAND_I16 : Atomic2Ops<atomic_load_nand_16, GPR32>;
 862  def ATOMIC_LOAD_NAND_I32 : Atomic2Ops<atomic_load_nand_32, GPR32>;
 863
 864  def ATOMIC_SWAP_I8       : Atomic2Ops<atomic_swap_8, GPR32>;
 865  def ATOMIC_SWAP_I16      : Atomic2Ops<atomic_swap_16, GPR32>;
 866  def ATOMIC_SWAP_I32      : Atomic2Ops<atomic_swap_32, GPR32>;
 867
 868  def ATOMIC_CMP_SWAP_I8   : AtomicCmpSwap<atomic_cmp_swap_8, GPR32>;
 869  def ATOMIC_CMP_SWAP_I16  : AtomicCmpSwap<atomic_cmp_swap_16, GPR32>;
 870  def ATOMIC_CMP_SWAP_I32  : AtomicCmpSwap<atomic_cmp_swap_32, GPR32>;
 871}
 872
 873/// Pseudo instructions for loading and storing accumulator registers.
 874let isPseudo = 1, isCodeGenOnly = 1 in {
 875  def LOAD_ACC64  : Load<"", ACC64>;
 876  def STORE_ACC64 : Store<"", ACC64>;
 877}
 878
 879//===----------------------------------------------------------------------===//
 880// Instruction definition
 881//===----------------------------------------------------------------------===//
 882//===----------------------------------------------------------------------===//
 883// MipsI Instructions
 884//===----------------------------------------------------------------------===//
 885
 886/// Arithmetic Instructions (ALU Immediate)
 887def ADDiu : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd, IIArith, immSExt16,
 888                               add>,
 889            ADDI_FM<0x9>, IsAsCheapAsAMove;
 890def ADDi  : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>, ADDI_FM<0x8>;
 891def SLTi  : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
 892            SLTI_FM<0xa>;
 893def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
 894            SLTI_FM<0xb>;
 895def ANDi  : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd, IILogic, immZExt16,
 896                               and>,
 897            ADDI_FM<0xc>;
 898def ORi   : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd, IILogic, immZExt16,
 899                               or>,
 900            ADDI_FM<0xd>;
 901def XORi  : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd, IILogic, immZExt16,
 902                               xor>,
 903            ADDI_FM<0xe>;
 904def LUi   : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM;
 905
 906/// Arithmetic Instructions (3-Operand, R-Type)
 907def ADDu  : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, IIArith, add>,
 908            ADD_FM<0, 0x21>;
 909def SUBu  : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, IIArith, sub>,
 910            ADD_FM<0, 0x23>;
 911let Defs = [HI0, LO0] in
 912def MUL   : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, IIImul, mul>,
 913            ADD_FM<0x1c, 2>;
 914def ADD   : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>;
 915def SUB   : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>;
 916def SLT   : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>;
 917def SLTu  : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>;
 918def AND   : MMRel, ArithLogicR<"and", GPR32Opnd, 1, IILogic, and>,
 919            ADD_FM<0, 0x24>;
 920def OR    : MMRel, ArithLogicR<"or", GPR32Opnd, 1, IILogic, or>,
 921            ADD_FM<0, 0x25>;
 922def XOR   : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, IILogic, xor>,
 923            ADD_FM<0, 0x26>;
 924def NOR   : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>;
 925
 926/// Shift Instructions
 927def SLL  : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, shl, immZExt5>,
 928           SRA_FM<0, 0>;
 929def SRL  : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, srl, immZExt5>,
 930           SRA_FM<2, 0>;
 931def SRA  : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, sra, immZExt5>,
 932           SRA_FM<3, 0>;
 933def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, shl>, SRLV_FM<4, 0>;
 934def SRLV : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, srl>, SRLV_FM<6, 0>;
 935def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, sra>, SRLV_FM<7, 0>;
 936
 937// Rotate Instructions
 938let Predicates = [HasMips32r2, HasStdEnc] in {
 939  def ROTR  : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, rotr,
 940                                      immZExt5>,
 941              SRA_FM<2, 1>;
 942  def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, rotr>,
 943              SRLV_FM<6, 1>;
 944}
 945
 946/// Load and Store Instructions
 947///  aligned
 948def LB  : Load<"lb", GPR32Opnd, sextloadi8, IILoad>, MMRel, LW_FM<0x20>;
 949def LBu : Load<"lbu", GPR32Opnd, zextloadi8, IILoad, addrDefault>, MMRel,
 950          LW_FM<0x24>;
 951def LH  : Load<"lh", GPR32Opnd, sextloadi16, IILoad, addrDefault>, MMRel,
 952          LW_FM<0x21>;
 953def LHu : Load<"lhu", GPR32Opnd, zextloadi16, IILoad>, MMRel, LW_FM<0x25>;
 954def LW  : Load<"lw", GPR32Opnd, load, IILoad, addrDefault>, MMRel,
 955          LW_FM<0x23>;
 956def SB  : Store<"sb", GPR32Opnd, truncstorei8, IIStore>, MMRel, LW_FM<0x28>;
 957def SH  : Store<"sh", GPR32Opnd, truncstorei16, IIStore>, MMRel, LW_FM<0x29>;
 958def SW  : Store<"sw", GPR32Opnd, store, IIStore>, MMRel, LW_FM<0x2b>;
 959
 960/// load/store left/right
 961let Predicates = [NotInMicroMips] in {
 962def LWL : LoadLeftRight<"lwl", MipsLWL, GPR32Opnd, IILoad>, LW_FM<0x22>;
 963def LWR : LoadLeftRight<"lwr", MipsLWR, GPR32Opnd, IILoad>, LW_FM<0x26>;
 964def SWL : StoreLeftRight<"swl", MipsSWL, GPR32Opnd, IIStore>, LW_FM<0x2a>;
 965def SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd, IIStore>, LW_FM<0x2e>;
 966}
 967
 968def SYNC : SYNC_FT, SYNC_FM;
 969def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>;
 970def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>;
 971def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>;
 972def TLT : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM<0x32>;
 973def TLTU : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM<0x33>;
 974def TNE : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM<0x36>;
 975
 976def TEQI : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM<0xc>;
 977def TGEI : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM<0x8>;
 978def TGEIU : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM<0x9>;
 979def TLTI : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM<0xa>;
 980def TTLTIU : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM<0xb>;
 981def TNEI : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM<0xe>;
 982
 983def BREAK : BRK_FT<"break">, BRK_FM<0xd>;
 984def SYSCALL : SYS_FT<"syscall">, SYS_FM<0xc>;
 985def TRAP : TrapBase<BREAK>;
 986
 987def ERET : ER_FT<"eret">, ER_FM<0x18>;
 988def DERET : ER_FT<"deret">, ER_FM<0x1f>;
 989
 990def EI : DEI_FT<"ei", GPR32Opnd>, EI_FM<1>;
 991def DI : DEI_FT<"di", GPR32Opnd>, EI_FM<0>;
 992
 993def WAIT : WAIT_FT<"wait">;
 994
 995/// Load-linked, Store-conditional
 996def LL : LLBase<"ll", GPR32Opnd>, LW_FM<0x30>;
 997def SC : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>;
 998
 999/// Jump and Branch Instructions
1000def J       : MMRel, JumpFJ<jmptarget, "j", br, bb, "j">, FJ<2>,
1001              Requires<[RelocStatic, HasStdEnc]>, IsBranch;
1002def JR      : MMRel, IndirectBranch<"jr", GPR32Opnd>, MTLO_FM<8>;
1003def BEQ     : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>;
1004def BNE     : MMRel, CBranch<"bne", brtarget, setne, GPR32Opnd>, BEQ_FM<5>;
1005def BGEZ    : MMRel, CBranchZero<"bgez", brtarget, setge, GPR32Opnd>,
1006              BGEZ_FM<1, 1>;
1007def BGTZ    : MMRel, CBranchZero<"bgtz", brtarget, setgt, GPR32Opnd>,
1008              BGEZ_FM<7, 0>;
1009def BLEZ    : MMRel, CBranchZero<"blez", brtarget, setle, GPR32Opnd>,
1010              BGEZ_FM<6, 0>;
1011def BLTZ    : MMRel, CBranchZero<"bltz", brtarget, setlt, GPR32Opnd>,
1012              BGEZ_FM<1, 0>;
1013def B       : UncondBranch<BEQ>;
1014
1015def JAL  : MMRel, JumpLink<"jal", calltarget>, FJ<3>;
1016def JALR : MMRel, JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM;
1017def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>;
1018def BGEZAL : MMRel, BGEZAL_FT<"bgezal", brtarget, GPR32Opnd>, BGEZAL_FM<0x11>;
1019def BLTZAL : MMRel, BGEZAL_FT<"bltzal", brtarget, GPR32Opnd>, BGEZAL_FM<0x10>;
1020def BAL_BR : BAL_BR_Pseudo<BGEZAL>;
1021def TAILCALL : MMRel, JumpFJ<calltarget, "j", MipsTailCall, imm, "tcall">,
1022               FJ<2>, IsTailCall;
1023def TAILCALL_R : MMRel, JumpFR<"tcallr", GPR32Opnd, MipsTailCall>, MTLO_FM<8>,
1024                 IsTailCall;
1025
1026def RET : MMRel, RetBase<"ret", GPR32Opnd>, MTLO_FM<8>;
1027
1028// Exception handling related node and instructions.
1029// The conversion sequence is:
1030// ISD::EH_RETURN -> MipsISD::EH_RETURN ->
1031// MIPSeh_return -> (stack change + indirect branch)
1032//
1033// MIPSeh_return takes the place of regular return instruction
1034// but takes two arguments (V1, V0) which are used for storing
1035// the offset and return address respectively.
1036def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
1037
1038def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET,
1039                      [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
1040
1041let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1042  def MIPSeh_return32 : MipsPseudo<(outs), (ins GPR32:$spoff, GPR32:$dst),
1043                                [(MIPSehret GPR32:$spoff, GPR32:$dst)]>;
1044  def MIPSeh_return64 : MipsPseudo<(outs), (ins GPR64:$spoff,
1045                                                GPR64:$dst),
1046                                [(MIPSehret GPR64:$spoff, GPR64:$dst)]>;
1047}
1048
1049/// Multiply and Divide Instructions.
1050def MULT  : MMRel, Mult<"mult", IIImult, GPR32Opnd, [HI0, LO0]>,
1051            MULT_FM<0, 0x18>;
1052def MULTu : MMRel, Mult<"multu", IIImult, GPR32Opnd, [HI0, LO0]>,
1053            MULT_FM<0, 0x19>;
1054def SDIV  : MMRel, Div<"div", IIIdiv, GPR32Opnd, [HI0, LO0]>,
1055            MULT_FM<0, 0x1a>;
1056def UDIV  : MMRel, Div<"divu", IIIdiv, GPR32Opnd, [HI0, LO0]>,
1057            MULT_FM<0, 0x1b>;
1058
1059def MTHI : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>;
1060def MTLO : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>;
1061def MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>, MFLO_FM<0x10>;
1062def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>;
1063
1064/// Sign Ext In Register Instructions.
1065def SEB : MMRel, SignExtInReg<"seb", i8, GPR32Opnd>, SEB_FM<0x10, 0x20>;
1066def SEH : MMRel, SignExtInReg<"seh", i16, GPR32Opnd>, SEB_FM<0x18, 0x20>;
1067
1068/// Count Leading
1069def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM<0x20>;
1070def CLO : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM<0x21>;
1071
1072/// Word Swap Bytes Within Halfwords
1073def WSBH : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM<2, 0x20>;
1074
1075/// No operation.
1076def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>;
1077
1078// FrameIndexes are legalized when they are operands from load/store
1079// instructions. The same not happens for stack address copies, so an
1080// add op with mem ComplexPattern is used and the stack address copy
1081// can be matched. It's similar to Sparc LEA_ADDRi
1082def LEA_ADDiu : EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>;
1083
1084// MADD*/MSUB*
1085def MADD  : MMRel, MArithR<"madd", 1>, MULT_FM<0x1c, 0>;
1086def MADDU : MMRel, MArithR<"maddu", 1>, MULT_FM<0x1c, 1>;
1087def MSUB  : MMRel, MArithR<"msub">, MULT_FM<0x1c, 4>;
1088def MSUBU : MMRel, MArithR<"msubu">, MULT_FM<0x1c, 5>;
1089
1090let Predicates = [HasStdEnc, NotDSP] in {
1091def PseudoMULT  : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, IIImult>;
1092def PseudoMULTu : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu, IIImult>;
1093def PseudoMFHI : PseudoMFLOHI<GPR32, ACC64, MipsMFHI>;
1094def PseudoMFLO : PseudoMFLOHI<GPR32, ACC64, MipsMFLO>;
1095def PseudoMTLOHI : PseudoMTLOHI<ACC64, GPR32>;
1096def PseudoMADD  : MAddSubPseudo<MADD, MipsMAdd>;
1097def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu>;
1098def PseudoMSUB  : MAddSubPseudo<MSUB, MipsMSub>;
1099def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu>;
1100}
1101
1102def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, IIIdiv,
1103                               0, 1, 1>;
1104def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, IIIdiv,
1105                               0, 1, 1>;
1106
1107def RDHWR : ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM;
1108
1109def EXT : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>, EXT_FM<0>;
1110def INS : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>, EXT_FM<4>;
1111
1112/// Move Control Registers From/To CPU Registers
1113def MFC0 : MFC3OP<"mfc0", GPR32Opnd>, MFC3OP_FM<0x10, 0>;
1114def MTC0 : MFC3OP<"mtc0", GPR32Opnd>, MFC3OP_FM<0x10, 4>;
1115def MFC2 : MFC3OP<"mfc2", GPR32Opnd>, MFC3OP_FM<0x12, 0>;
1116def MTC2 : MFC3OP<"mtc2", GPR32Opnd>, MFC3OP_FM<0x12, 4>;
1117
1118//===----------------------------------------------------------------------===//
1119// Instruction aliases
1120//===----------------------------------------------------------------------===//
1121def : InstAlias<"move $dst, $src",
1122                (ADDu GPR32Opnd:$dst, GPR32Opnd:$src,ZERO), 1>,
1123      Requires<[NotMips64]>;
1124def : InstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>;
1125def : InstAlias<"addu $rs, $rt, $imm",
1126                (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1127def : InstAlias<"add $rs, $rt, $imm",
1128                (ADDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1129def : InstAlias<"and $rs, $rt, $imm",
1130                (ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1131def : InstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>;
1132def : InstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1133def : InstAlias<"jal $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1134def : InstAlias<"jal $rd,$rs", (JALR GPR32Opnd:$rd, GPR32Opnd:$rs), 0>;
1135def : InstAlias<"not $rt, $rs",
1136                (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>;
1137def : InstAlias<"neg $rt, $rs",
1138                (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1139def : InstAlias<"negu $rt, $rs",
1140                (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1141def : InstAlias<"slt $rs, $rt, $imm",
1142                (SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1143def : InstAlias<"xor $rs, $rt, $imm",
1144                (XORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1145def : InstAlias<"or $rs, $rt, $imm",
1146                (ORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1147def : InstAlias<"nop", (SLL ZERO, ZERO, 0), 1>;
1148def : InstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1149def : InstAlias<"mtc0 $rt, $rd", (MTC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1150def : InstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1151def : InstAlias<"mtc2 $rt, $rd", (MTC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1152def : InstAlias<"b $offset", (BEQ ZERO, ZERO, brtarget:$offset), 0>;
1153def : InstAlias<"bnez $rs,$offset",
1154                (BNE GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1155def : InstAlias<"beqz $rs,$offset",
1156                (BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1157def : InstAlias<"syscall", (SYSCALL 0), 1>;
1158
1159def : InstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>;
1160def : InstAlias<"break", (BREAK 0, 0), 1>;
1161def : InstAlias<"ei", (EI ZERO), 1>;
1162def : InstAlias<"di", (DI ZERO), 1>;
1163
1164def  : InstAlias<"teq $rs, $rt", (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1165def  : InstAlias<"tge $rs, $rt", (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1166def  : InstAlias<"tgeu $rs, $rt", (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1167def  : InstAlias<"tlt $rs, $rt", (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1168def  : InstAlias<"tltu $rs, $rt", (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1169def  : InstAlias<"tne $rs, $rt", (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1170def : InstAlias<"sub, $rd, $rs, $imm",
1171                (ADDi GPR32Opnd:$rd, GPR32Opnd:$rs, InvertedImOperand:$imm)>;
1172def : InstAlias<"subu, $rd, $rs, $imm",
1173                (ADDiu GPR32Opnd:$rd, GPR32Opnd:$rs, InvertedImOperand:$imm)>;
1174
1175//===----------------------------------------------------------------------===//
1176// Assembler Pseudo Instructions
1177//===----------------------------------------------------------------------===//
1178
1179class LoadImm32< string instr_asm, Operand Od, RegisterOperand RO> :
1180  MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1181                     !strconcat(instr_asm, "\t$rt, $imm32")> ;
1182def LoadImm32Reg : LoadImm32<"li", uimm5, GPR32Opnd>;
1183
1184class LoadAddress<string instr_asm, Operand MemOpnd, RegisterOperand RO> :
1185  MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr),
1186                     !strconcat(instr_asm, "\t$rt, $addr")> ;
1187def LoadAddr32Reg : LoadAddress<"la", mem, GPR32Opnd>;
1188
1189class LoadAddressImm<string instr_asm, Operand Od, RegisterOperand RO> :
1190  MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1191                     !strconcat(instr_asm, "\t$rt, $imm32")> ;
1192def LoadAddr32Imm : LoadAddressImm<"la", uimm5, GPR32Opnd>;
1193
1194//===----------------------------------------------------------------------===//
1195//  Arbitrary patterns that map to one or more instructions
1196//===----------------------------------------------------------------------===//
1197
1198// Load/store pattern templates.
1199class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> :
1200  MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>;
1201
1202class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> :
1203  MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>;
1204
1205// Small immediates
1206def : MipsPat<(i32 immSExt16:$in),
1207              (ADDiu ZERO, imm:$in)>;
1208def : MipsPat<(i32 immZExt16:$in),
1209              (ORi ZERO, imm:$in)>;
1210def : MipsPat<(i32 immLow16Zero:$in),
1211              (LUi (HI16 imm:$in))>;
1212
1213// Arbitrary immediates
1214def : MipsPat<(i32 imm:$imm),
1215          (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
1216
1217// Carry MipsPatterns
1218def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
1219              (SUBu GPR32:$lhs, GPR32:$rhs)>;
1220let Predicates = [HasStdEnc, NotDSP] in {
1221  def : MipsPat<(addc GPR32:$lhs, GPR32:$rhs),
1222                (ADDu GPR32:$lhs, GPR32:$rhs)>;
1223  def : MipsPat<(addc  GPR32:$src, immSExt16:$imm),
1224                (ADDiu GPR32:$src, imm:$imm)>;
1225}
1226
1227// Call
1228def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)),
1229              (JAL tglobaladdr:$dst)>;
1230def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
1231              (JAL texternalsym:$dst)>;
1232//def : MipsPat<(MipsJmpLink GPR32:$dst),
1233//              (JALR GPR32:$dst)>;
1234
1235// Tail call
1236def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
1237              (TAILCALL tglobaladdr:$dst)>;
1238def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
1239              (TAILCALL texternalsym:$dst)>;
1240// hi/lo relocs
1241def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
1242def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
1243def : Mi

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