/3rd_party/llvm/lib/Target/CellSPU/SPUInstrFormats.td

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  1. //===-- SPUInstrFormats.td - Cell SPU Instruction Formats --*- tablegen -*-===//
  2. //
  3. // The LLVM Compiler Infrastructure
  4. //
  5. // This file is distributed under the University of Illinois Open Source
  6. // License. See LICENSE.TXT for details.
  7. //
  8. //===----------------------------------------------------------------------===//
  9. //===----------------------------------------------------------------------===//
  10. //
  11. // Cell SPU instruction formats. Note that these are notationally similar to
  12. // PowerPC, like "A-Form". But the sizes of operands and fields differ.
  13. // This was kiped from the PPC instruction formats (seemed like a good idea...)
  14. class SPUInstr<dag OOL, dag IOL, string asmstr, InstrItinClass itin>
  15. : Instruction {
  16. field bits<32> Inst;
  17. let Namespace = "SPU";
  18. let OutOperandList = OOL;
  19. let InOperandList = IOL;
  20. let AsmString = asmstr;
  21. let Itinerary = itin;
  22. }
  23. // RR Format
  24. class RRForm<bits<11> opcode, dag OOL, dag IOL, string asmstr,
  25. InstrItinClass itin, list<dag> pattern>
  26. : SPUInstr<OOL, IOL, asmstr, itin> {
  27. bits<7> RA;
  28. bits<7> RB;
  29. bits<7> RT;
  30. let Pattern = pattern;
  31. let Inst{0-10} = opcode;
  32. let Inst{11-17} = RB;
  33. let Inst{18-24} = RA;
  34. let Inst{25-31} = RT;
  35. }
  36. let RB = 0 in {
  37. // RR Format, where RB is zeroed (dont care):
  38. class RRForm_1<bits<11> opcode, dag OOL, dag IOL, string asmstr,
  39. InstrItinClass itin, list<dag> pattern>
  40. : RRForm<opcode, OOL, IOL, asmstr, itin, pattern>
  41. { }
  42. let RA = 0 in {
  43. // RR Format, where RA and RB are zeroed (dont care):
  44. // Used for reads from status control registers (see FPSCRRr32)
  45. class RRForm_2<bits<11> opcode, dag OOL, dag IOL, string asmstr,
  46. InstrItinClass itin, list<dag> pattern>
  47. : RRForm<opcode, OOL, IOL, asmstr, itin, pattern>
  48. { }
  49. }
  50. }
  51. let RT = 0 in {
  52. // RR Format, where RT is zeroed (don't care), or as the instruction handbook
  53. // says, "RT is a false target." Used in "Halt if" instructions
  54. class RRForm_3<bits<11> opcode, dag OOL, dag IOL, string asmstr,
  55. InstrItinClass itin, list<dag> pattern>
  56. : RRForm<opcode, OOL, IOL, asmstr, itin, pattern>
  57. { }
  58. }
  59. // RRR Format
  60. class RRRForm<bits<4> opcode, dag OOL, dag IOL, string asmstr,
  61. InstrItinClass itin, list<dag> pattern>
  62. : SPUInstr<OOL, IOL, asmstr, itin>
  63. {
  64. bits<7> RA;
  65. bits<7> RB;
  66. bits<7> RC;
  67. bits<7> RT;
  68. let Pattern = pattern;
  69. let Inst{0-3} = opcode;
  70. let Inst{4-10} = RT;
  71. let Inst{11-17} = RB;
  72. let Inst{18-24} = RA;
  73. let Inst{25-31} = RC;
  74. }
  75. // RI7 Format
  76. class RI7Form<bits<11> opcode, dag OOL, dag IOL, string asmstr,
  77. InstrItinClass itin, list<dag> pattern>
  78. : SPUInstr<OOL, IOL, asmstr, itin>
  79. {
  80. bits<7> i7;
  81. bits<7> RA;
  82. bits<7> RT;
  83. let Pattern = pattern;
  84. let Inst{0-10} = opcode;
  85. let Inst{11-17} = i7;
  86. let Inst{18-24} = RA;
  87. let Inst{25-31} = RT;
  88. }
  89. // CVTIntFp Format
  90. class CVTIntFPForm<bits<10> opcode, dag OOL, dag IOL, string asmstr,
  91. InstrItinClass itin, list<dag> pattern>
  92. : SPUInstr<OOL, IOL, asmstr, itin>
  93. {
  94. bits<7> RA;
  95. bits<7> RT;
  96. let Pattern = pattern;
  97. let Inst{0-9} = opcode;
  98. let Inst{10-17} = 0;
  99. let Inst{18-24} = RA;
  100. let Inst{25-31} = RT;
  101. }
  102. let RA = 0 in {
  103. class BICondForm<bits<11> opcode, dag OOL, dag IOL, string asmstr, list<dag> pattern>
  104. : RRForm<opcode, OOL, IOL, asmstr, BranchResolv, pattern>
  105. { }
  106. let RT = 0 in {
  107. // Branch instruction format (without D/E flag settings)
  108. class BRForm<bits<11> opcode, dag OOL, dag IOL, string asmstr,
  109. InstrItinClass itin, list<dag> pattern>
  110. : RRForm<opcode, OOL, IOL, asmstr, itin, pattern>
  111. { }
  112. class BIForm<bits<11> opcode, string asmstr, list<dag> pattern>
  113. : RRForm<opcode, (outs), (ins R32C:$func), asmstr, BranchResolv,
  114. pattern>
  115. { }
  116. let RB = 0 in {
  117. // Return instruction (bi, branch indirect), RA is zero (LR):
  118. class RETForm<string asmstr, list<dag> pattern>
  119. : BRForm<0b00010101100, (outs), (ins), asmstr, BranchResolv,
  120. pattern>
  121. { }
  122. }
  123. }
  124. }
  125. // Branch indirect external data forms:
  126. class BISLEDForm<bits<2> DE_flag, string asmstr, list<dag> pattern>
  127. : SPUInstr<(outs), (ins indcalltarget:$func), asmstr, BranchResolv>
  128. {
  129. bits<7> Rcalldest;
  130. let Pattern = pattern;
  131. let Inst{0-10} = 0b11010101100;
  132. let Inst{11} = 0;
  133. let Inst{12-13} = DE_flag;
  134. let Inst{14-17} = 0b0000;
  135. let Inst{18-24} = Rcalldest;
  136. let Inst{25-31} = 0b0000000;
  137. }
  138. // RI10 Format
  139. class RI10Form<bits<8> opcode, dag OOL, dag IOL, string asmstr,
  140. InstrItinClass itin, list<dag> pattern>
  141. : SPUInstr<OOL, IOL, asmstr, itin>
  142. {
  143. bits<10> i10;
  144. bits<7> RA;
  145. bits<7> RT;
  146. let Pattern = pattern;
  147. let Inst{0-7} = opcode;
  148. let Inst{8-17} = i10;
  149. let Inst{18-24} = RA;
  150. let Inst{25-31} = RT;
  151. }
  152. // RI10 Format, where the constant is zero (or effectively ignored by the
  153. // SPU)
  154. let i10 = 0 in {
  155. class RI10Form_1<bits<8> opcode, dag OOL, dag IOL, string asmstr,
  156. InstrItinClass itin, list<dag> pattern>
  157. : RI10Form<opcode, OOL, IOL, asmstr, itin, pattern>
  158. { }
  159. }
  160. // RI10 Format, where RT is ignored.
  161. // This format is used primarily by the Halt If ... Immediate set of
  162. // instructions
  163. let RT = 0 in {
  164. class RI10Form_2<bits<8> opcode, dag OOL, dag IOL, string asmstr,
  165. InstrItinClass itin, list<dag> pattern>
  166. : RI10Form<opcode, OOL, IOL, asmstr, itin, pattern>
  167. { }
  168. }
  169. // RI16 Format
  170. class RI16Form<bits<9> opcode, dag OOL, dag IOL, string asmstr,
  171. InstrItinClass itin, list<dag> pattern>
  172. : SPUInstr<OOL, IOL, asmstr, itin>
  173. {
  174. bits<16> i16;
  175. bits<7> RT;
  176. let Pattern = pattern;
  177. let Inst{0-8} = opcode;
  178. let Inst{9-24} = i16;
  179. let Inst{25-31} = RT;
  180. }
  181. // Specialized version of the RI16 Format for unconditional branch relative and
  182. // branch absolute, branch and set link. Note that for branch and set link, the
  183. // link register doesn't have to be $lr, but this is actually hard coded into
  184. // the instruction pattern.
  185. let RT = 0 in {
  186. class UncondBranch<bits<9> opcode, dag OOL, dag IOL, string asmstr,
  187. list<dag> pattern>
  188. : RI16Form<opcode, OOL, IOL, asmstr, BranchResolv, pattern>
  189. { }
  190. class BranchSetLink<bits<9> opcode, dag OOL, dag IOL, string asmstr,
  191. list<dag> pattern>
  192. : RI16Form<opcode, OOL, IOL, asmstr, BranchResolv, pattern>
  193. { }
  194. }
  195. //===----------------------------------------------------------------------===//
  196. // Specialized versions of RI16:
  197. //===----------------------------------------------------------------------===//
  198. // RI18 Format
  199. class RI18Form<bits<7> opcode, dag OOL, dag IOL, string asmstr,
  200. InstrItinClass itin, list<dag> pattern>
  201. : SPUInstr<OOL, IOL, asmstr, itin>
  202. {
  203. bits<18> i18;
  204. bits<7> RT;
  205. let Pattern = pattern;
  206. let Inst{0-6} = opcode;
  207. let Inst{7-24} = i18;
  208. let Inst{25-31} = RT;
  209. }
  210. //===----------------------------------------------------------------------===//
  211. // Instruction formats for intrinsics:
  212. //===----------------------------------------------------------------------===//
  213. // RI10 Format for v8i16 intrinsics
  214. class RI10_Int_v8i16<bits<8> opcode, string opc, InstrItinClass itin,
  215. Intrinsic IntID> :
  216. RI10Form<opcode, (outs VECREG:$rT), (ins s10imm:$val, VECREG:$rA),
  217. !strconcat(opc, " $rT, $rA, $val"), itin,
  218. [(set (v8i16 VECREG:$rT), (IntID (v8i16 VECREG:$rA),
  219. i16ImmSExt10:$val))] >;
  220. class RI10_Int_v4i32<bits<8> opcode, string opc, InstrItinClass itin,
  221. Intrinsic IntID> :
  222. RI10Form<opcode, (outs VECREG:$rT), (ins s10imm:$val, VECREG:$rA),
  223. !strconcat(opc, " $rT, $rA, $val"), itin,
  224. [(set (v4i32 VECREG:$rT), (IntID (v4i32 VECREG:$rA),
  225. i32ImmSExt10:$val))] >;
  226. // RR Format for v8i16 intrinsics
  227. class RR_Int_v8i16<bits<11> opcode, string opc, InstrItinClass itin,
  228. Intrinsic IntID> :
  229. RRForm<opcode, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
  230. !strconcat(opc, " $rT, $rA, $rB"), itin,
  231. [(set (v8i16 VECREG:$rT), (IntID (v8i16 VECREG:$rA),
  232. (v8i16 VECREG:$rB)))] >;
  233. // RR Format for v4i32 intrinsics
  234. class RR_Int_v4i32<bits<11> opcode, string opc, InstrItinClass itin,
  235. Intrinsic IntID> :
  236. RRForm<opcode, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
  237. !strconcat(opc, " $rT, $rA, $rB"), itin,
  238. [(set (v4i32 VECREG:$rT), (IntID (v4i32 VECREG:$rA),
  239. (v4i32 VECREG:$rB)))] >;
  240. //===----------------------------------------------------------------------===//
  241. // Pseudo instructions, like call frames:
  242. //===----------------------------------------------------------------------===//
  243. class Pseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern>
  244. : SPUInstr<OOL, IOL, asmstr, NoItinerary> {
  245. let OutOperandList = OOL;
  246. let InOperandList = IOL;
  247. let AsmString = asmstr;
  248. let Pattern = pattern;
  249. let Inst{31-0} = 0;
  250. }
  251. //===----------------------------------------------------------------------===//
  252. // Branch hint formats
  253. //===----------------------------------------------------------------------===//
  254. // For hbrr and hbra
  255. class HBI16Form<bits<7> opcode, dag IOL, string asmstr>
  256. : Instruction {
  257. field bits<32> Inst;
  258. bits<16>i16;
  259. bits<9>RO;
  260. let Namespace = "SPU";
  261. let InOperandList = IOL;
  262. let OutOperandList = (outs); //no output
  263. let AsmString = asmstr;
  264. let Itinerary = BranchHints;
  265. let Inst{0-6} = opcode;
  266. let Inst{7-8} = RO{8-7};
  267. let Inst{9-24} = i16;
  268. let Inst{25-31} = RO{6-0};
  269. }