/3rd_party/llvm/lib/Target/PowerPC/PPCRegisterInfo.h

https://code.google.com/p/softart/ · C++ Header · 104 lines · 64 code · 20 blank · 20 comment · 0 complexity · a875efcef85553d57d4351c32864ac59 MD5 · raw file

  1. //===-- PPCRegisterInfo.h - PowerPC Register Information Impl ---*- C++ -*-===//
  2. //
  3. // The LLVM Compiler Infrastructure
  4. //
  5. // This file is distributed under the University of Illinois Open Source
  6. // License. See LICENSE.TXT for details.
  7. //
  8. //===----------------------------------------------------------------------===//
  9. //
  10. // This file contains the PowerPC implementation of the TargetRegisterInfo
  11. // class.
  12. //
  13. //===----------------------------------------------------------------------===//
  14. #ifndef POWERPC32_REGISTERINFO_H
  15. #define POWERPC32_REGISTERINFO_H
  16. #include "llvm/ADT/DenseMap.h"
  17. #include "PPC.h"
  18. #define GET_REGINFO_HEADER
  19. #include "PPCGenRegisterInfo.inc"
  20. namespace llvm {
  21. class PPCSubtarget;
  22. class TargetInstrInfo;
  23. class Type;
  24. class PPCRegisterInfo : public PPCGenRegisterInfo {
  25. DenseMap<unsigned, unsigned> ImmToIdxMap;
  26. const PPCSubtarget &Subtarget;
  27. public:
  28. PPCRegisterInfo(const PPCSubtarget &SubTarget);
  29. /// getPointerRegClass - Return the register class to use to hold pointers.
  30. /// This is used for addressing modes.
  31. virtual const TargetRegisterClass *
  32. getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const;
  33. unsigned getRegPressureLimit(const TargetRegisterClass *RC,
  34. MachineFunction &MF) const;
  35. /// Code Generation virtual methods...
  36. const uint16_t *getCalleeSavedRegs(const MachineFunction* MF = 0) const;
  37. const uint32_t *getCallPreservedMask(CallingConv::ID CC) const;
  38. const uint32_t *getNoPreservedMask() const;
  39. BitVector getReservedRegs(const MachineFunction &MF) const;
  40. /// We require the register scavenger.
  41. bool requiresRegisterScavenging(const MachineFunction &MF) const {
  42. return true;
  43. }
  44. bool requiresFrameIndexScavenging(const MachineFunction &MF) const {
  45. return true;
  46. }
  47. bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
  48. return true;
  49. }
  50. virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const {
  51. return true;
  52. }
  53. void lowerDynamicAlloc(MachineBasicBlock::iterator II) const;
  54. void lowerCRSpilling(MachineBasicBlock::iterator II,
  55. unsigned FrameIndex) const;
  56. void lowerCRRestore(MachineBasicBlock::iterator II,
  57. unsigned FrameIndex) const;
  58. void lowerVRSAVESpilling(MachineBasicBlock::iterator II,
  59. unsigned FrameIndex) const;
  60. void lowerVRSAVERestore(MachineBasicBlock::iterator II,
  61. unsigned FrameIndex) const;
  62. bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg,
  63. int &FrameIdx) const;
  64. void eliminateFrameIndex(MachineBasicBlock::iterator II,
  65. int SPAdj, unsigned FIOperandNum,
  66. RegScavenger *RS = NULL) const;
  67. // Support for virtual base registers.
  68. bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const;
  69. void materializeFrameBaseRegister(MachineBasicBlock *MBB,
  70. unsigned BaseReg, int FrameIdx,
  71. int64_t Offset) const;
  72. void resolveFrameIndex(MachineBasicBlock::iterator I,
  73. unsigned BaseReg, int64_t Offset) const;
  74. bool isFrameOffsetLegal(const MachineInstr *MI, int64_t Offset) const;
  75. // Debug information queries.
  76. unsigned getFrameRegister(const MachineFunction &MF) const;
  77. // Base pointer (stack realignment) support.
  78. unsigned getBaseRegister(const MachineFunction &MF) const;
  79. bool hasBasePointer(const MachineFunction &MF) const;
  80. bool canRealignStack(const MachineFunction &MF) const;
  81. bool needsStackRealignment(const MachineFunction &MF) const;
  82. };
  83. } // end namespace llvm
  84. #endif