/3rd_party/llvm/lib/Target/PowerPC/PPCRegisterInfo.h

  1//===-- PPCRegisterInfo.h - PowerPC Register Information Impl ---*- C++ -*-===//
  2//
  3//                     The LLVM Compiler Infrastructure
  4//
  5// This file is distributed under the University of Illinois Open Source
  6// License. See LICENSE.TXT for details.
  7//
  8//===----------------------------------------------------------------------===//
  9//
 10// This file contains the PowerPC implementation of the TargetRegisterInfo
 11// class.
 12//
 13//===----------------------------------------------------------------------===//
 14
 15#ifndef POWERPC32_REGISTERINFO_H
 16#define POWERPC32_REGISTERINFO_H
 17
 18#include "llvm/ADT/DenseMap.h"
 19#include "PPC.h"
 20
 21#define GET_REGINFO_HEADER
 22#include "PPCGenRegisterInfo.inc"
 23
 24namespace llvm {
 25class PPCSubtarget;
 26class TargetInstrInfo;
 27class Type;
 28
 29class PPCRegisterInfo : public PPCGenRegisterInfo {
 30  DenseMap<unsigned, unsigned> ImmToIdxMap;
 31  const PPCSubtarget &Subtarget;
 32public:
 33  PPCRegisterInfo(const PPCSubtarget &SubTarget);
 34  
 35  /// getPointerRegClass - Return the register class to use to hold pointers.
 36  /// This is used for addressing modes.
 37  virtual const TargetRegisterClass *
 38  getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const;
 39
 40  unsigned getRegPressureLimit(const TargetRegisterClass *RC,
 41                               MachineFunction &MF) const;
 42
 43  /// Code Generation virtual methods...
 44  const uint16_t *getCalleeSavedRegs(const MachineFunction* MF = 0) const;
 45  const uint32_t *getCallPreservedMask(CallingConv::ID CC) const;
 46  const uint32_t *getNoPreservedMask() const;
 47
 48  BitVector getReservedRegs(const MachineFunction &MF) const;
 49
 50  /// We require the register scavenger.
 51  bool requiresRegisterScavenging(const MachineFunction &MF) const {
 52    return true;
 53  }
 54
 55  bool requiresFrameIndexScavenging(const MachineFunction &MF) const {
 56    return true;
 57  }
 58
 59  bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
 60    return true;
 61  }
 62
 63  virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const {
 64    return true;
 65  }
 66
 67  void lowerDynamicAlloc(MachineBasicBlock::iterator II) const;
 68  void lowerCRSpilling(MachineBasicBlock::iterator II,
 69                       unsigned FrameIndex) const;
 70  void lowerCRRestore(MachineBasicBlock::iterator II,
 71                      unsigned FrameIndex) const;
 72  void lowerVRSAVESpilling(MachineBasicBlock::iterator II,
 73                           unsigned FrameIndex) const;
 74  void lowerVRSAVERestore(MachineBasicBlock::iterator II,
 75                          unsigned FrameIndex) const;
 76
 77  bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg,
 78			    int &FrameIdx) const;
 79  void eliminateFrameIndex(MachineBasicBlock::iterator II,
 80                           int SPAdj, unsigned FIOperandNum,
 81                           RegScavenger *RS = NULL) const;
 82
 83  // Support for virtual base registers.
 84  bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const;
 85  void materializeFrameBaseRegister(MachineBasicBlock *MBB,
 86                                    unsigned BaseReg, int FrameIdx,
 87                                    int64_t Offset) const;
 88  void resolveFrameIndex(MachineBasicBlock::iterator I,
 89                         unsigned BaseReg, int64_t Offset) const;
 90  bool isFrameOffsetLegal(const MachineInstr *MI, int64_t Offset) const;
 91
 92  // Debug information queries.
 93  unsigned getFrameRegister(const MachineFunction &MF) const;
 94
 95  // Base pointer (stack realignment) support.
 96  unsigned getBaseRegister(const MachineFunction &MF) const;
 97  bool hasBasePointer(const MachineFunction &MF) const;
 98  bool canRealignStack(const MachineFunction &MF) const;
 99  bool needsStackRealignment(const MachineFunction &MF) const;
100};
101
102} // end namespace llvm
103
104#endif