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/3rd_party/llvm/lib/Target/PowerPC/PPCInstrFormats.td

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   1//===- PowerPCInstrFormats.td - PowerPC Instruction Formats --*- tablegen -*-=//
   2//
   3//                     The LLVM Compiler Infrastructure
   4//
   5// This file is distributed under the University of Illinois Open Source
   6// License. See LICENSE.TXT for details.
   7//
   8//===----------------------------------------------------------------------===//
   9
  10//===----------------------------------------------------------------------===//
  11//
  12// PowerPC instruction formats
  13
  14class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin>
  15        : Instruction {
  16  field bits<32> Inst;
  17
  18  bit PPC64 = 0;  // Default value, override with isPPC64
  19
  20  let Namespace = "PPC";
  21  let Inst{0-5} = opcode;
  22  let OutOperandList = OOL;
  23  let InOperandList = IOL;
  24  let AsmString = asmstr;
  25  let Itinerary = itin;
  26
  27  bits<1> PPC970_First = 0;
  28  bits<1> PPC970_Single = 0;
  29  bits<1> PPC970_Cracked = 0;
  30  bits<3> PPC970_Unit = 0;
  31
  32  /// These fields correspond to the fields in PPCInstrInfo.h.  Any changes to
  33  /// these must be reflected there!  See comments there for what these are.
  34  let TSFlags{0}   = PPC970_First;
  35  let TSFlags{1}   = PPC970_Single;
  36  let TSFlags{2}   = PPC970_Cracked;
  37  let TSFlags{5-3} = PPC970_Unit;
  38
  39  // Fields used for relation models.
  40  string BaseName = "";
  41
  42  // For cases where multiple instruction definitions really represent the
  43  // same underlying instruction but with one definition for 64-bit arguments
  44  // and one for 32-bit arguments, this bit breaks the degeneracy between
  45  // the two forms and allows TableGen to generate mapping tables.
  46  bit Interpretation64Bit = 0;
  47}
  48
  49class PPC970_DGroup_First   { bits<1> PPC970_First = 1;  }
  50class PPC970_DGroup_Single  { bits<1> PPC970_Single = 1; }
  51class PPC970_DGroup_Cracked { bits<1> PPC970_Cracked = 1; }
  52class PPC970_MicroCode;
  53
  54class PPC970_Unit_Pseudo   { bits<3> PPC970_Unit = 0;   }
  55class PPC970_Unit_FXU      { bits<3> PPC970_Unit = 1;   }
  56class PPC970_Unit_LSU      { bits<3> PPC970_Unit = 2;   }
  57class PPC970_Unit_FPU      { bits<3> PPC970_Unit = 3;   }
  58class PPC970_Unit_CRU      { bits<3> PPC970_Unit = 4;   }
  59class PPC970_Unit_VALU     { bits<3> PPC970_Unit = 5;   }
  60class PPC970_Unit_VPERM    { bits<3> PPC970_Unit = 6;   }
  61class PPC970_Unit_BRU      { bits<3> PPC970_Unit = 7;   }
  62
  63// Two joined instructions; used to emit two adjacent instructions as one.
  64// The itinerary from the first instruction is used for scheduling and
  65// classification.
  66class I2<bits<6> opcode1, bits<6> opcode2, dag OOL, dag IOL, string asmstr,
  67         InstrItinClass itin>
  68        : Instruction {
  69  field bits<64> Inst;
  70
  71  bit PPC64 = 0;  // Default value, override with isPPC64
  72
  73  let Namespace = "PPC";
  74  let Inst{0-5} = opcode1;
  75  let Inst{32-37} = opcode2;
  76  let OutOperandList = OOL;
  77  let InOperandList = IOL;
  78  let AsmString = asmstr;
  79  let Itinerary = itin;
  80
  81  bits<1> PPC970_First = 0;
  82  bits<1> PPC970_Single = 0;
  83  bits<1> PPC970_Cracked = 0;
  84  bits<3> PPC970_Unit = 0;
  85
  86  /// These fields correspond to the fields in PPCInstrInfo.h.  Any changes to
  87  /// these must be reflected there!  See comments there for what these are.
  88  let TSFlags{0}   = PPC970_First;
  89  let TSFlags{1}   = PPC970_Single;
  90  let TSFlags{2}   = PPC970_Cracked;
  91  let TSFlags{5-3} = PPC970_Unit;
  92
  93  // Fields used for relation models.
  94  string BaseName = "";
  95  bit Interpretation64Bit = 0;
  96}
  97
  98// 1.7.1 I-Form
  99class IForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr,
 100            InstrItinClass itin, list<dag> pattern>
 101         : I<opcode, OOL, IOL, asmstr, itin> {
 102  let Pattern = pattern;
 103  bits<24> LI;
 104
 105  let Inst{6-29}  = LI;
 106  let Inst{30}    = aa;
 107  let Inst{31}    = lk;
 108}
 109
 110// 1.7.2 B-Form
 111class BForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr>
 112  : I<opcode, OOL, IOL, asmstr, BrB> {
 113  bits<7> BIBO;  // 2 bits of BI and 5 bits of BO.
 114  bits<3>  CR;
 115  bits<14> BD;
 116
 117  bits<5> BI;
 118  let BI{0-1} = BIBO{5-6};
 119  let BI{2-4} = CR{0-2};
 120
 121  let Inst{6-10}  = BIBO{4-0};
 122  let Inst{11-15} = BI;
 123  let Inst{16-29} = BD;
 124  let Inst{30}    = aa;
 125  let Inst{31}    = lk;
 126}
 127
 128class BForm_1<bits<6> opcode, bits<5> bo, bit aa, bit lk, dag OOL, dag IOL,
 129             string asmstr>
 130  : BForm<opcode, aa, lk, OOL, IOL, asmstr> {
 131  let BIBO{4-0} = bo;
 132  let BIBO{6-5} = 0;
 133  let CR = 0;
 134}
 135
 136class BForm_2<bits<6> opcode, bits<5> bo, bits<5> bi, bit aa, bit lk,
 137              dag OOL, dag IOL, string asmstr>
 138  : I<opcode, OOL, IOL, asmstr, BrB> {
 139  bits<14> BD;
 140
 141  let Inst{6-10}  = bo;
 142  let Inst{11-15} = bi;
 143  let Inst{16-29} = BD;
 144  let Inst{30}    = aa;
 145  let Inst{31}    = lk;
 146}
 147
 148class BForm_3<bits<6> opcode, bit aa, bit lk,
 149              dag OOL, dag IOL, string asmstr>
 150  : I<opcode, OOL, IOL, asmstr, BrB> {
 151  bits<5> BO;
 152  bits<5> BI;
 153  bits<14> BD;
 154
 155  let Inst{6-10}  = BO;
 156  let Inst{11-15} = BI;
 157  let Inst{16-29} = BD;
 158  let Inst{30}    = aa;
 159  let Inst{31}    = lk;
 160}
 161
 162// 1.7.3 SC-Form
 163class SCForm<bits<6> opcode, bits<1> xo,
 164                     dag OOL, dag IOL, string asmstr, InstrItinClass itin,
 165                     list<dag> pattern>
 166  : I<opcode, OOL, IOL, asmstr, itin> {
 167  bits<7>  LEV;
 168
 169  let Pattern = pattern;
 170
 171  let Inst{20-26} = LEV;
 172  let Inst{30}    = xo;
 173}
 174
 175// 1.7.4 D-Form
 176class DForm_base<bits<6> opcode, dag OOL, dag IOL, string asmstr,
 177                 InstrItinClass itin, list<dag> pattern> 
 178  : I<opcode, OOL, IOL, asmstr, itin> {
 179  bits<5>  A;
 180  bits<5>  B;
 181  bits<16> C;
 182
 183  let Pattern = pattern;
 184  
 185  let Inst{6-10}  = A;
 186  let Inst{11-15} = B;
 187  let Inst{16-31} = C;
 188}
 189
 190class DForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr,
 191              InstrItinClass itin, list<dag> pattern>
 192  : I<opcode, OOL, IOL, asmstr, itin> {
 193  bits<5>  A;
 194  bits<21> Addr;
 195
 196  let Pattern = pattern;
 197  
 198  let Inst{6-10}  = A;
 199  let Inst{11-15} = Addr{20-16}; // Base Reg
 200  let Inst{16-31} = Addr{15-0};  // Displacement
 201}
 202
 203class DForm_1a<bits<6> opcode, dag OOL, dag IOL, string asmstr,
 204               InstrItinClass itin, list<dag> pattern>
 205  : I<opcode, OOL, IOL, asmstr, itin> {
 206  bits<5>  A;
 207  bits<16> C;
 208  bits<5>  B;
 209
 210  let Pattern = pattern;
 211  
 212  let Inst{6-10}  = A;
 213  let Inst{11-15} = B;
 214  let Inst{16-31} = C;
 215}
 216
 217
 218class DForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr,
 219              InstrItinClass itin, list<dag> pattern>
 220  : DForm_base<opcode, OOL, IOL, asmstr, itin, pattern> {
 221
 222  // Even though ADDICo does not really have an RC bit, provide
 223  // the declaration of one here so that isDOT has something to set.
 224  bit RC = 0;
 225}
 226
 227class DForm_2_r0<bits<6> opcode, dag OOL, dag IOL, string asmstr,
 228                 InstrItinClass itin, list<dag> pattern>
 229  : I<opcode, OOL, IOL, asmstr, itin> {
 230  bits<5>  A;
 231  bits<16> B;
 232  
 233  let Pattern = pattern;
 234  
 235  let Inst{6-10}  = A;
 236  let Inst{11-15} = 0;
 237  let Inst{16-31} = B;
 238}
 239
 240class DForm_4<bits<6> opcode, dag OOL, dag IOL, string asmstr,
 241              InstrItinClass itin, list<dag> pattern>
 242  : I<opcode, OOL, IOL, asmstr, itin> {
 243  bits<5>  B;
 244  bits<5>  A;
 245  bits<16> C;
 246  
 247  let Pattern = pattern;
 248  
 249  let Inst{6-10}  = A;
 250  let Inst{11-15} = B;
 251  let Inst{16-31} = C;
 252}
 253              
 254class DForm_4_zero<bits<6> opcode, dag OOL, dag IOL, string asmstr,
 255                   InstrItinClass itin, list<dag> pattern>
 256  : DForm_1<opcode, OOL, IOL, asmstr, itin, pattern> {
 257  let A = 0;
 258  let Addr = 0;
 259}
 260
 261class IForm_and_DForm_1<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2,
 262            dag OOL, dag IOL, string asmstr,
 263            InstrItinClass itin, list<dag> pattern>
 264         : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> {
 265  bits<5>  A;
 266  bits<21> Addr;
 267
 268  let Pattern = pattern;
 269  bits<24> LI;
 270
 271  let Inst{6-29}  = LI;
 272  let Inst{30}    = aa;
 273  let Inst{31}    = lk;
 274
 275  let Inst{38-42}  = A;
 276  let Inst{43-47} = Addr{20-16}; // Base Reg
 277  let Inst{48-63} = Addr{15-0};  // Displacement
 278}
 279
 280// This is used to emit BL8+NOP.
 281class IForm_and_DForm_4_zero<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2,
 282            dag OOL, dag IOL, string asmstr,
 283            InstrItinClass itin, list<dag> pattern>
 284         :  IForm_and_DForm_1<opcode1, aa, lk, opcode2,
 285                              OOL, IOL, asmstr, itin, pattern> {
 286  let A = 0;
 287  let Addr = 0;
 288}
 289
 290class DForm_5<bits<6> opcode, dag OOL, dag IOL, string asmstr,
 291              InstrItinClass itin>
 292  : I<opcode, OOL, IOL, asmstr, itin> {
 293  bits<3>  BF;
 294  bits<1>  L;
 295  bits<5>  RA;
 296  bits<16> I;
 297
 298  let Inst{6-8}   = BF;
 299  let Inst{9}     = 0;
 300  let Inst{10}    = L;
 301  let Inst{11-15} = RA;
 302  let Inst{16-31} = I;
 303}
 304
 305class DForm_5_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr,
 306                  InstrItinClass itin>
 307  : DForm_5<opcode, OOL, IOL, asmstr, itin> {
 308  let L = PPC64;
 309}
 310
 311class DForm_6<bits<6> opcode, dag OOL, dag IOL, string asmstr,
 312              InstrItinClass itin> 
 313  : DForm_5<opcode, OOL, IOL, asmstr, itin>;
 314
 315class DForm_6_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr,
 316                  InstrItinClass itin>
 317  : DForm_6<opcode, OOL, IOL, asmstr, itin> {
 318  let L = PPC64;
 319}
 320
 321
 322// 1.7.5 DS-Form
 323class DSForm_1<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr,
 324               InstrItinClass itin, list<dag> pattern>
 325         : I<opcode, OOL, IOL, asmstr, itin> {
 326  bits<5>  RST;
 327  bits<19> DS_RA;
 328
 329  let Pattern = pattern;
 330  
 331  let Inst{6-10}  = RST;
 332  let Inst{11-15} = DS_RA{18-14};  // Register #
 333  let Inst{16-29} = DS_RA{13-0};   // Displacement.
 334  let Inst{30-31} = xo;
 335}
 336
 337class DSForm_1a<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr,
 338                InstrItinClass itin, list<dag> pattern>
 339         : I<opcode, OOL, IOL, asmstr, itin> {
 340   bits<5>  RST;
 341   bits<14> DS;
 342   bits<5>  RA;
 343 
 344   let Pattern = pattern;
 345   
 346   let Inst{6-10}  = RST;
 347   let Inst{11-15} = RA;
 348   let Inst{16-29} = DS;
 349   let Inst{30-31} = xo;
 350}
 351
 352// 1.7.6 X-Form
 353class XForm_base_r3xo<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 
 354                      InstrItinClass itin, list<dag> pattern>
 355  : I<opcode, OOL, IOL, asmstr, itin> {
 356  bits<5> RST;
 357  bits<5> A;
 358  bits<5> B;
 359
 360  let Pattern = pattern;
 361
 362  bit RC = 0;    // set by isDOT
 363
 364  let Inst{6-10}  = RST;
 365  let Inst{11-15} = A;
 366  let Inst{16-20} = B;
 367  let Inst{21-30} = xo;
 368  let Inst{31}    = RC;
 369}
 370
 371// This is the same as XForm_base_r3xo, but the first two operands are swapped
 372// when code is emitted.
 373class XForm_base_r3xo_swapped
 374        <bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
 375        InstrItinClass itin> 
 376  : I<opcode, OOL, IOL, asmstr, itin> {
 377  bits<5> A;
 378  bits<5> RST;
 379  bits<5> B;
 380
 381  bit RC = 0;    // set by isDOT
 382
 383  let Inst{6-10}  = RST;
 384  let Inst{11-15} = A;
 385  let Inst{16-20} = B;
 386  let Inst{21-30} = xo;
 387  let Inst{31}    = RC;
 388}
 389
 390
 391class XForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
 392              InstrItinClass itin, list<dag> pattern> 
 393  : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>;
 394
 395class XForm_1a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
 396              InstrItinClass itin, list<dag> pattern>
 397  : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
 398  let RST = 0;
 399}
 400
 401class XForm_rs<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
 402              InstrItinClass itin, list<dag> pattern>
 403  : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
 404  let A = 0;
 405  let B = 0;
 406}
 407
 408class XForm_6<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
 409              InstrItinClass itin, list<dag> pattern> 
 410  : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
 411  let Pattern = pattern;
 412}
 413
 414class XForm_8<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
 415              InstrItinClass itin, list<dag> pattern> 
 416  : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>;
 417
 418class XForm_10<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
 419               InstrItinClass itin, list<dag> pattern> 
 420  : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
 421    let Pattern = pattern;
 422}
 423
 424class XForm_11<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
 425               InstrItinClass itin, list<dag> pattern> 
 426  : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> {
 427  let B = 0;
 428  let Pattern = pattern;
 429}
 430
 431class XForm_16<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
 432               InstrItinClass itin>
 433         : I<opcode, OOL, IOL, asmstr, itin> {
 434  bits<3> BF;
 435  bits<1> L; 
 436  bits<5> RA;
 437  bits<5> RB;
 438  
 439  let Inst{6-8}   = BF;
 440  let Inst{9}     = 0;
 441  let Inst{10}    = L;
 442  let Inst{11-15} = RA;
 443  let Inst{16-20} = RB;
 444  let Inst{21-30} = xo;
 445  let Inst{31}    = 0;
 446}
 447
 448class XForm_mtmsr<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
 449                InstrItinClass itin>
 450         : I<opcode, OOL, IOL, asmstr, itin> {
 451  bits<5> RS;
 452  bits<1> L;
 453
 454  let Inst{6-10} = RS;
 455  let Inst{15} = L;
 456  let Inst{21-30} = xo;
 457}
 458
 459class XForm_16_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
 460                   InstrItinClass itin>
 461  : XForm_16<opcode, xo, OOL, IOL, asmstr, itin> {
 462  let L = PPC64;
 463}
 464
 465class XForm_17<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
 466               InstrItinClass itin>
 467         : I<opcode, OOL, IOL, asmstr, itin> {
 468  bits<3> BF;
 469  bits<5> FRA;
 470  bits<5> FRB;
 471  
 472  let Inst{6-8}   = BF;
 473  let Inst{9-10}  = 0;
 474  let Inst{11-15} = FRA;
 475  let Inst{16-20} = FRB;
 476  let Inst{21-30} = xo;
 477  let Inst{31}    = 0;
 478}
 479
 480class XForm_24<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
 481               InstrItinClass itin, list<dag> pattern> 
 482  : I<opcode, OOL, IOL, asmstr, itin> {
 483  let Pattern = pattern;
 484  let Inst{6-10}  = 31;
 485  let Inst{11-15} = 0;
 486  let Inst{16-20} = 0;
 487  let Inst{21-30} = xo;
 488  let Inst{31}    = 0;
 489}
 490
 491class XForm_24_sync<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
 492               string asmstr, InstrItinClass itin, list<dag> pattern> 
 493  : I<opcode, OOL, IOL, asmstr, itin> {
 494  bits<2> L;
 495
 496  let Pattern = pattern;
 497  let Inst{6-8}   = 0;
 498  let Inst{9-10}  = L;
 499  let Inst{11-15} = 0;
 500  let Inst{16-20} = 0;
 501  let Inst{21-30} = xo;
 502  let Inst{31}    = 0;
 503}
 504
 505class XForm_24_eieio<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
 506               string asmstr, InstrItinClass itin, list<dag> pattern> 
 507  : XForm_24_sync<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
 508  let L = 0;
 509}
 510
 511class XForm_25<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
 512               InstrItinClass itin, list<dag> pattern> 
 513  : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
 514}
 515
 516class XForm_26<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
 517               InstrItinClass itin, list<dag> pattern>
 518  : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
 519  let A = 0;
 520}
 521
 522class XForm_28<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
 523               InstrItinClass itin, list<dag> pattern> 
 524  : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
 525}
 526
 527// This is used for MFFS, MTFSB0, MTFSB1.  42 is arbitrary; this series of
 528// numbers presumably relates to some document, but I haven't found it.
 529class XForm_42<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
 530              InstrItinClass itin, list<dag> pattern>
 531  : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
 532  let Pattern = pattern;
 533
 534  bit RC = 0;    // set by isDOT
 535
 536  let Inst{6-10}  = RST;
 537  let Inst{11-20} = 0;
 538  let Inst{21-30} = xo;
 539  let Inst{31}    = RC;
 540}
 541class XForm_43<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
 542              InstrItinClass itin, list<dag> pattern>
 543  : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
 544  let Pattern = pattern;
 545  bits<5> FM;
 546
 547  bit RC = 0;    // set by isDOT
 548
 549  let Inst{6-10}  = FM;
 550  let Inst{11-20} = 0;
 551  let Inst{21-30} = xo;
 552  let Inst{31}    = RC;
 553}
 554
 555class XForm_0<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
 556              InstrItinClass itin, list<dag> pattern>
 557  : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
 558  let RST = 0;
 559  let A = 0;
 560  let B = 0;
 561}
 562
 563class XForm_16b<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
 564              InstrItinClass itin, list<dag> pattern>
 565  : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
 566  let RST = 0;
 567  let A = 0;
 568}
 569
 570// DCB_Form - Form X instruction, used for dcb* instructions.
 571class DCB_Form<bits<10> xo, bits<5> immfield, dag OOL, dag IOL, string asmstr, 
 572                      InstrItinClass itin, list<dag> pattern>
 573  : I<31, OOL, IOL, asmstr, itin> {
 574  bits<5> A;
 575  bits<5> B;
 576
 577  let Pattern = pattern;
 578
 579  let Inst{6-10}  = immfield;
 580  let Inst{11-15} = A;
 581  let Inst{16-20} = B;
 582  let Inst{21-30} = xo;
 583  let Inst{31}    = 0;
 584}
 585
 586
 587// DSS_Form - Form X instruction, used for altivec dss* instructions.
 588class DSS_Form<bits<10> xo, dag OOL, dag IOL, string asmstr, 
 589                      InstrItinClass itin, list<dag> pattern>
 590  : I<31, OOL, IOL, asmstr, itin> {
 591  bits<1> T;
 592  bits<2> STRM;
 593  bits<5> A;
 594  bits<5> B;
 595
 596  let Pattern = pattern;
 597
 598  let Inst{6}     = T;
 599  let Inst{7-8}   = 0;
 600  let Inst{9-10}  = STRM;
 601  let Inst{11-15} = A;
 602  let Inst{16-20} = B;
 603  let Inst{21-30} = xo;
 604  let Inst{31}    = 0;
 605}
 606
 607// 1.7.7 XL-Form
 608class XLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
 609               InstrItinClass itin, list<dag> pattern>
 610    : I<opcode, OOL, IOL, asmstr, itin> {
 611  bits<5> CRD;
 612  bits<5> CRA;
 613  bits<5> CRB;
 614  
 615  let Pattern = pattern;
 616  
 617  let Inst{6-10}  = CRD;
 618  let Inst{11-15} = CRA;
 619  let Inst{16-20} = CRB;
 620  let Inst{21-30} = xo;
 621  let Inst{31}    = 0;
 622}
 623
 624class XLForm_1_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
 625               InstrItinClass itin, list<dag> pattern>
 626    : I<opcode, OOL, IOL, asmstr, itin> {
 627  bits<5> CRD;
 628  
 629  let Pattern = pattern;
 630  
 631  let Inst{6-10}  = CRD;
 632  let Inst{11-15} = CRD;
 633  let Inst{16-20} = CRD;
 634  let Inst{21-30} = xo;
 635  let Inst{31}    = 0;
 636}
 637
 638class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, dag OOL, dag IOL, string asmstr, 
 639               InstrItinClass itin, list<dag> pattern>
 640    : I<opcode, OOL, IOL, asmstr, itin> {
 641  bits<5> BO;
 642  bits<5> BI;
 643  bits<2> BH;
 644  
 645  let Pattern = pattern;
 646  
 647  let Inst{6-10}  = BO;
 648  let Inst{11-15} = BI;
 649  let Inst{16-18} = 0;
 650  let Inst{19-20} = BH;
 651  let Inst{21-30} = xo;
 652  let Inst{31}    = lk;
 653}
 654
 655class XLForm_2_br<bits<6> opcode, bits<10> xo, bit lk,
 656                  dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
 657  : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> {
 658  bits<7> BIBO;  // 2 bits of BI and 5 bits of BO.
 659  bits<3>  CR;
 660  
 661  let BO = BIBO{4-0};
 662  let BI{0-1} = BIBO{5-6};
 663  let BI{2-4} = CR{0-2};
 664  let BH = 0;
 665}
 666
 667
 668class XLForm_2_ext<bits<6> opcode, bits<10> xo, bits<5> bo,  bits<5> bi, bit lk,
 669                  dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
 670  : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> {
 671  let BO = bo;
 672  let BI = bi;
 673  let BH = 0;
 674}
 675
 676class XLForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
 677               InstrItinClass itin>
 678         : I<opcode, OOL, IOL, asmstr, itin> {
 679  bits<3> BF;
 680  bits<3> BFA;
 681  
 682  let Inst{6-8}   = BF;
 683  let Inst{9-10}  = 0;
 684  let Inst{11-13} = BFA;
 685  let Inst{14-15} = 0;
 686  let Inst{16-20} = 0;
 687  let Inst{21-30} = xo;
 688  let Inst{31}    = 0;
 689}
 690
 691// 1.7.8 XFX-Form
 692class XFXForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
 693                InstrItinClass itin>
 694         : I<opcode, OOL, IOL, asmstr, itin> {
 695  bits<5>  RT;
 696  bits<10> SPR;
 697
 698  let Inst{6-10}  = RT;
 699  let Inst{11}    = SPR{4};
 700  let Inst{12}    = SPR{3};
 701  let Inst{13}    = SPR{2};
 702  let Inst{14}    = SPR{1};
 703  let Inst{15}    = SPR{0};
 704  let Inst{16}    = SPR{9};
 705  let Inst{17}    = SPR{8};
 706  let Inst{18}    = SPR{7};
 707  let Inst{19}    = SPR{6};
 708  let Inst{20}    = SPR{5};
 709  let Inst{21-30} = xo;
 710  let Inst{31}    = 0;
 711}
 712
 713class XFXForm_1_ext<bits<6> opcode, bits<10> xo, bits<10> spr, 
 714                   dag OOL, dag IOL, string asmstr, InstrItinClass itin> 
 715  : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin> {
 716  let SPR = spr;
 717}
 718
 719class XFXForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
 720                InstrItinClass itin>
 721         : I<opcode, OOL, IOL, asmstr, itin> {
 722  bits<5>  RT;
 723   
 724  let Inst{6-10}  = RT;
 725  let Inst{11-20} = 0;
 726  let Inst{21-30} = xo;
 727  let Inst{31}    = 0;
 728}
 729
 730class XFXForm_5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
 731                InstrItinClass itin> 
 732  : I<opcode, OOL, IOL, asmstr, itin> {
 733  bits<8>  FXM;
 734  bits<5>  rS;
 735   
 736  let Inst{6-10}  = rS;
 737  let Inst{11}    = 0;
 738  let Inst{12-19} = FXM;
 739  let Inst{20}    = 0;
 740  let Inst{21-30} = xo;
 741  let Inst{31}    = 0;
 742}
 743
 744class XFXForm_5a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
 745                 InstrItinClass itin> 
 746  : I<opcode, OOL, IOL, asmstr, itin> {
 747  bits<5>  ST;
 748  bits<8>  FXM;
 749   
 750  let Inst{6-10}  = ST;
 751  let Inst{11}    = 1;
 752  let Inst{12-19} = FXM;
 753  let Inst{20}    = 0;
 754  let Inst{21-30} = xo;
 755  let Inst{31}    = 0;
 756}
 757
 758class XFXForm_7<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
 759                InstrItinClass itin>
 760  : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin>;
 761
 762class XFXForm_7_ext<bits<6> opcode, bits<10> xo, bits<10> spr, 
 763                    dag OOL, dag IOL, string asmstr, InstrItinClass itin> 
 764  : XFXForm_7<opcode, xo, OOL, IOL, asmstr, itin> {
 765  let SPR = spr;
 766}
 767
 768// XFL-Form - MTFSF
 769// This is probably 1.7.9, but I don't have the reference that uses this
 770// numbering scheme...
 771class XFLForm<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 
 772              InstrItinClass itin, list<dag>pattern>
 773  : I<opcode, OOL, IOL, asmstr, itin> {
 774  bits<8> FM;
 775  bits<5> rT;
 776
 777  bit RC = 0;    // set by isDOT
 778  let Pattern = pattern;
 779
 780  let Inst{6} = 0;
 781  let Inst{7-14}  = FM;
 782  let Inst{15} = 0;
 783  let Inst{16-20} = rT;
 784  let Inst{21-30} = xo;
 785  let Inst{31}    = RC;
 786}
 787
 788// 1.7.10 XS-Form - SRADI.
 789class XSForm_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr,
 790               InstrItinClass itin, list<dag> pattern>
 791         : I<opcode, OOL, IOL, asmstr, itin> {
 792  bits<5> A;
 793  bits<5> RS;
 794  bits<6> SH;
 795
 796  bit RC = 0;    // set by isDOT
 797  let Pattern = pattern;
 798
 799  let Inst{6-10}  = RS;
 800  let Inst{11-15} = A;
 801  let Inst{16-20} = SH{4,3,2,1,0};
 802  let Inst{21-29} = xo;
 803  let Inst{30}    = SH{5};
 804  let Inst{31}    = RC;
 805}
 806
 807// 1.7.11 XO-Form
 808class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, string asmstr,
 809               InstrItinClass itin, list<dag> pattern>
 810         : I<opcode, OOL, IOL, asmstr, itin> {
 811  bits<5> RT;
 812  bits<5> RA;
 813  bits<5> RB;
 814
 815  let Pattern = pattern;
 816
 817  bit RC = 0;    // set by isDOT
 818
 819  let Inst{6-10}  = RT;
 820  let Inst{11-15} = RA;
 821  let Inst{16-20} = RB;
 822  let Inst{21}    = oe;
 823  let Inst{22-30} = xo;
 824  let Inst{31}    = RC;  
 825}
 826
 827class XOForm_3<bits<6> opcode, bits<9> xo, bit oe, 
 828               dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern>
 829  : XOForm_1<opcode, xo, oe, OOL, IOL, asmstr, itin, pattern> {
 830  let RB = 0;
 831}
 832
 833// 1.7.12 A-Form
 834class AForm_1<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 
 835              InstrItinClass itin, list<dag> pattern>
 836         : I<opcode, OOL, IOL, asmstr, itin> {
 837  bits<5> FRT;
 838  bits<5> FRA;
 839  bits<5> FRC;
 840  bits<5> FRB;
 841
 842  let Pattern = pattern;
 843
 844  bit RC = 0;    // set by isDOT
 845
 846  let Inst{6-10}  = FRT;
 847  let Inst{11-15} = FRA;
 848  let Inst{16-20} = FRB;
 849  let Inst{21-25} = FRC;
 850  let Inst{26-30} = xo;
 851  let Inst{31}    = RC;
 852}
 853
 854class AForm_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
 855              InstrItinClass itin, list<dag> pattern>
 856  : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
 857  let FRC = 0;
 858}
 859
 860class AForm_3<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
 861              InstrItinClass itin, list<dag> pattern> 
 862  : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
 863  let FRB = 0;
 864}
 865
 866class AForm_4<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 
 867              InstrItinClass itin, list<dag> pattern>
 868         : I<opcode, OOL, IOL, asmstr, itin> {
 869  bits<5> RT;
 870  bits<5> RA;
 871  bits<5> RB;
 872  bits<5> COND;
 873
 874  let Pattern = pattern;
 875
 876  let Inst{6-10}  = RT;
 877  let Inst{11-15} = RA;
 878  let Inst{16-20} = RB;
 879  let Inst{21-25} = COND;
 880  let Inst{26-30} = xo;
 881  let Inst{31}    = 0;
 882}
 883
 884// 1.7.13 M-Form
 885class MForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr,
 886              InstrItinClass itin, list<dag> pattern>
 887    : I<opcode, OOL, IOL, asmstr, itin> {
 888  bits<5> RA;
 889  bits<5> RS;
 890  bits<5> RB;
 891  bits<5> MB;
 892  bits<5> ME;
 893
 894  let Pattern = pattern;
 895
 896  bit RC = 0;    // set by isDOT
 897
 898  let Inst{6-10}  = RS;
 899  let Inst{11-15} = RA;
 900  let Inst{16-20} = RB;
 901  let Inst{21-25} = MB;
 902  let Inst{26-30} = ME;
 903  let Inst{31}    = RC;
 904}
 905
 906class MForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr,
 907              InstrItinClass itin, list<dag> pattern>
 908  : MForm_1<opcode, OOL, IOL, asmstr, itin, pattern> {
 909}
 910
 911// 1.7.14 MD-Form
 912class MDForm_1<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, string asmstr,
 913               InstrItinClass itin, list<dag> pattern>
 914    : I<opcode, OOL, IOL, asmstr, itin> {
 915  bits<5> RA;
 916  bits<5> RS;
 917  bits<6> SH;
 918  bits<6> MBE;
 919
 920  let Pattern = pattern;
 921
 922  bit RC = 0;    // set by isDOT
 923
 924  let Inst{6-10}  = RS;
 925  let Inst{11-15} = RA;
 926  let Inst{16-20} = SH{4,3,2,1,0};
 927  let Inst{21-26} = MBE{4,3,2,1,0,5};
 928  let Inst{27-29} = xo;
 929  let Inst{30}    = SH{5};
 930  let Inst{31}    = RC;
 931}
 932
 933class MDSForm_1<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, string asmstr,
 934                InstrItinClass itin, list<dag> pattern>
 935    : I<opcode, OOL, IOL, asmstr, itin> {
 936  bits<5> RA;
 937  bits<5> RS;
 938  bits<5> RB;
 939  bits<6> MBE;
 940
 941  let Pattern = pattern;
 942
 943  bit RC = 0;    // set by isDOT
 944
 945  let Inst{6-10}  = RS;
 946  let Inst{11-15} = RA;
 947  let Inst{16-20} = RB;
 948  let Inst{21-26} = MBE{4,3,2,1,0,5};
 949  let Inst{27-30} = xo;
 950  let Inst{31}    = RC;
 951}
 952
 953
 954// E-1 VA-Form
 955
 956// VAForm_1 - DACB ordering.
 957class VAForm_1<bits<6> xo, dag OOL, dag IOL, string asmstr,
 958               InstrItinClass itin, list<dag> pattern>
 959    : I<4, OOL, IOL, asmstr, itin> {
 960  bits<5> VD;
 961  bits<5> VA;
 962  bits<5> VC;
 963  bits<5> VB;
 964
 965  let Pattern = pattern;
 966  
 967  let Inst{6-10}  = VD;
 968  let Inst{11-15} = VA;
 969  let Inst{16-20} = VB;
 970  let Inst{21-25} = VC;
 971  let Inst{26-31} = xo;
 972}
 973
 974// VAForm_1a - DABC ordering.
 975class VAForm_1a<bits<6> xo, dag OOL, dag IOL, string asmstr,
 976                InstrItinClass itin, list<dag> pattern>
 977    : I<4, OOL, IOL, asmstr, itin> {
 978  bits<5> VD;
 979  bits<5> VA;
 980  bits<5> VB;
 981  bits<5> VC;
 982
 983  let Pattern = pattern;
 984  
 985  let Inst{6-10}  = VD;
 986  let Inst{11-15} = VA;
 987  let Inst{16-20} = VB;
 988  let Inst{21-25} = VC;
 989  let Inst{26-31} = xo;
 990}
 991
 992class VAForm_2<bits<6> xo, dag OOL, dag IOL, string asmstr,
 993               InstrItinClass itin, list<dag> pattern>
 994    : I<4, OOL, IOL, asmstr, itin> {
 995  bits<5> VD;
 996  bits<5> VA;
 997  bits<5> VB;
 998  bits<4> SH;
 999
1000  let Pattern = pattern;
1001  
1002  let Inst{6-10}  = VD;
1003  let Inst{11-15} = VA;
1004  let Inst{16-20} = VB;
1005  let Inst{21}    = 0;
1006  let Inst{22-25} = SH;
1007  let Inst{26-31} = xo;
1008}
1009
1010// E-2 VX-Form
1011class VXForm_1<bits<11> xo, dag OOL, dag IOL, string asmstr,
1012               InstrItinClass itin, list<dag> pattern>
1013    : I<4, OOL, IOL, asmstr, itin> {
1014  bits<5> VD;
1015  bits<5> VA;
1016  bits<5> VB;
1017  
1018  let Pattern = pattern;
1019  
1020  let Inst{6-10}  = VD;
1021  let Inst{11-15} = VA;
1022  let Inst{16-20} = VB;
1023  let Inst{21-31} = xo;
1024}
1025
1026class VXForm_setzero<bits<11> xo, dag OOL, dag IOL, string asmstr,
1027               InstrItinClass itin, list<dag> pattern>
1028    : VXForm_1<xo, OOL, IOL, asmstr, itin, pattern> {
1029  let VA = VD;
1030  let VB = VD;
1031}
1032
1033
1034class VXForm_2<bits<11> xo, dag OOL, dag IOL, string asmstr,
1035               InstrItinClass itin, list<dag> pattern>
1036    : I<4, OOL, IOL, asmstr, itin> {
1037  bits<5> VD;
1038  bits<5> VB;
1039  
1040  let Pattern = pattern;
1041  
1042  let Inst{6-10}  = VD;
1043  let Inst{11-15} = 0;
1044  let Inst{16-20} = VB;
1045  let Inst{21-31} = xo;
1046}
1047
1048class VXForm_3<bits<11> xo, dag OOL, dag IOL, string asmstr,
1049               InstrItinClass itin, list<dag> pattern>
1050    : I<4, OOL, IOL, asmstr, itin> {
1051  bits<5> VD;
1052  bits<5> IMM;
1053  
1054  let Pattern = pattern;
1055  
1056  let Inst{6-10}  = VD;
1057  let Inst{11-15} = IMM;
1058  let Inst{16-20} = 0;
1059  let Inst{21-31} = xo;
1060}
1061
1062/// VXForm_4 - VX instructions with "VD,0,0" register fields, like mfvscr.
1063class VXForm_4<bits<11> xo, dag OOL, dag IOL, string asmstr,
1064               InstrItinClass itin, list<dag> pattern>
1065    : I<4, OOL, IOL, asmstr, itin> {
1066  bits<5> VD;
1067  
1068  let Pattern = pattern;
1069  
1070  let Inst{6-10}  = VD;
1071  let Inst{11-15} = 0;
1072  let Inst{16-20} = 0;
1073  let Inst{21-31} = xo;
1074}
1075
1076/// VXForm_5 - VX instructions with "0,0,VB" register fields, like mtvscr.
1077class VXForm_5<bits<11> xo, dag OOL, dag IOL, string asmstr,
1078               InstrItinClass itin, list<dag> pattern>
1079    : I<4, OOL, IOL, asmstr, itin> {
1080  bits<5> VB;
1081  
1082  let Pattern = pattern;
1083  
1084  let Inst{6-10}  = 0;
1085  let Inst{11-15} = 0;
1086  let Inst{16-20} = VB;
1087  let Inst{21-31} = xo;
1088}
1089
1090// E-4 VXR-Form
1091class VXRForm_1<bits<10> xo, dag OOL, dag IOL, string asmstr,
1092               InstrItinClass itin, list<dag> pattern>
1093    : I<4, OOL, IOL, asmstr, itin> {
1094  bits<5> VD;
1095  bits<5> VA;
1096  bits<5> VB;
1097  bit RC = 0;
1098  
1099  let Pattern = pattern;
1100  
1101  let Inst{6-10}  = VD;
1102  let Inst{11-15} = VA;
1103  let Inst{16-20} = VB;
1104  let Inst{21}    = RC;
1105  let Inst{22-31} = xo;
1106}
1107
1108//===----------------------------------------------------------------------===//
1109class Pseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern>
1110    : I<0, OOL, IOL, asmstr, NoItinerary> {
1111  let isCodeGenOnly = 1;
1112  let PPC64 = 0;
1113  let Pattern = pattern;
1114  let Inst{31-0} = 0;
1115}