/3rd_party/llvm/lib/Target/XCore/XCoreISelLowering.h
C++ Header | 210 lines | 125 code | 42 blank | 43 comment | 0 complexity | a32b97da2b1bd80012853f7df4cb95cd MD5 | raw file
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1//===-- XCoreISelLowering.h - XCore DAG Lowering Interface ------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that XCore uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#ifndef XCOREISELLOWERING_H 16#define XCOREISELLOWERING_H 17 18#include "XCore.h" 19#include "llvm/CodeGen/SelectionDAG.h" 20#include "llvm/Target/TargetLowering.h" 21 22namespace llvm { 23 24 // Forward delcarations 25 class XCoreSubtarget; 26 class XCoreTargetMachine; 27 28 namespace XCoreISD { 29 enum NodeType { 30 // Start the numbering where the builtin ops and target ops leave off. 31 FIRST_NUMBER = ISD::BUILTIN_OP_END, 32 33 // Branch and link (call) 34 BL, 35 36 // pc relative address 37 PCRelativeWrapper, 38 39 // dp relative address 40 DPRelativeWrapper, 41 42 // cp relative address 43 CPRelativeWrapper, 44 45 // Store word to stack 46 STWSP, 47 48 // Corresponds to retsp instruction 49 RETSP, 50 51 // Corresponds to LADD instruction 52 LADD, 53 54 // Corresponds to LSUB instruction 55 LSUB, 56 57 // Corresponds to LMUL instruction 58 LMUL, 59 60 // Corresponds to MACCU instruction 61 MACCU, 62 63 // Corresponds to MACCS instruction 64 MACCS, 65 66 // Corresponds to CRC8 instruction 67 CRC8, 68 69 // Jumptable branch. 70 BR_JT, 71 72 // Jumptable branch using long branches for each entry. 73 BR_JT32, 74 75 // Memory barrier. 76 MEMBARRIER 77 }; 78 } 79 80 //===--------------------------------------------------------------------===// 81 // TargetLowering Implementation 82 //===--------------------------------------------------------------------===// 83 class XCoreTargetLowering : public TargetLowering 84 { 85 public: 86 87 explicit XCoreTargetLowering(XCoreTargetMachine &TM); 88 89 using TargetLowering::isZExtFree; 90 virtual bool isZExtFree(SDValue Val, EVT VT2) const; 91 92 93 virtual unsigned getJumpTableEncoding() const; 94 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; } 95 96 /// LowerOperation - Provide custom lowering hooks for some operations. 97 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 98 99 /// ReplaceNodeResults - Replace the results of node with an illegal result 100 /// type with new values built out of custom code. 101 /// 102 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 103 SelectionDAG &DAG) const; 104 105 /// getTargetNodeName - This method returns the name of a target specific 106 // DAG node. 107 virtual const char *getTargetNodeName(unsigned Opcode) const; 108 109 virtual MachineBasicBlock * 110 EmitInstrWithCustomInserter(MachineInstr *MI, 111 MachineBasicBlock *MBB) const; 112 113 virtual bool isLegalAddressingMode(const AddrMode &AM, 114 Type *Ty) const; 115 116 private: 117 const XCoreTargetMachine &TM; 118 const XCoreSubtarget &Subtarget; 119 120 // Lower Operand helpers 121 SDValue LowerCCCArguments(SDValue Chain, 122 CallingConv::ID CallConv, 123 bool isVarArg, 124 const SmallVectorImpl<ISD::InputArg> &Ins, 125 SDLoc dl, SelectionDAG &DAG, 126 SmallVectorImpl<SDValue> &InVals) const; 127 SDValue LowerCCCCallTo(SDValue Chain, SDValue Callee, 128 CallingConv::ID CallConv, bool isVarArg, 129 bool isTailCall, 130 const SmallVectorImpl<ISD::OutputArg> &Outs, 131 const SmallVectorImpl<SDValue> &OutVals, 132 const SmallVectorImpl<ISD::InputArg> &Ins, 133 SDLoc dl, SelectionDAG &DAG, 134 SmallVectorImpl<SDValue> &InVals) const; 135 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 136 CallingConv::ID CallConv, bool isVarArg, 137 const SmallVectorImpl<ISD::InputArg> &Ins, 138 SDLoc dl, SelectionDAG &DAG, 139 SmallVectorImpl<SDValue> &InVals) const; 140 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const; 141 SDValue getGlobalAddressWrapper(SDValue GA, const GlobalValue *GV, 142 SelectionDAG &DAG) const; 143 SDValue lowerLoadWordFromAlignedBasePlusOffset(SDLoc DL, SDValue Chain, 144 SDValue Base, int64_t Offset, 145 SelectionDAG &DAG) const; 146 147 // Lower Operand specifics 148 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const; 149 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const; 150 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 151 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 152 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 153 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 154 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const; 155 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 156 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const; 157 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const; 158 SDValue LowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const; 159 SDValue LowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const; 160 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 161 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const; 162 SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const; 163 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 164 SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const; 165 166 // Inline asm support 167 std::pair<unsigned, const TargetRegisterClass*> 168 getRegForInlineAsmConstraint(const std::string &Constraint, 169 MVT VT) const; 170 171 // Expand specifics 172 SDValue TryExpandADDWithMul(SDNode *Op, SelectionDAG &DAG) const; 173 SDValue ExpandADDSUB(SDNode *Op, SelectionDAG &DAG) const; 174 175 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 176 177 virtual void computeMaskedBitsForTargetNode(const SDValue Op, 178 APInt &KnownZero, 179 APInt &KnownOne, 180 const SelectionDAG &DAG, 181 unsigned Depth = 0) const; 182 183 virtual SDValue 184 LowerFormalArguments(SDValue Chain, 185 CallingConv::ID CallConv, 186 bool isVarArg, 187 const SmallVectorImpl<ISD::InputArg> &Ins, 188 SDLoc dl, SelectionDAG &DAG, 189 SmallVectorImpl<SDValue> &InVals) const; 190 191 virtual SDValue 192 LowerCall(TargetLowering::CallLoweringInfo &CLI, 193 SmallVectorImpl<SDValue> &InVals) const; 194 195 virtual SDValue 196 LowerReturn(SDValue Chain, 197 CallingConv::ID CallConv, bool isVarArg, 198 const SmallVectorImpl<ISD::OutputArg> &Outs, 199 const SmallVectorImpl<SDValue> &OutVals, 200 SDLoc dl, SelectionDAG &DAG) const; 201 202 virtual bool 203 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, 204 bool isVarArg, 205 const SmallVectorImpl<ISD::OutputArg> &ArgsFlags, 206 LLVMContext &Context) const; 207 }; 208} 209 210#endif // XCOREISELLOWERING_H