/3rd_party/llvm/lib/Target/XCore/XCoreISelLowering.h

https://code.google.com/p/softart/ · C++ Header · 210 lines · 125 code · 42 blank · 43 comment · 0 complexity · a32b97da2b1bd80012853f7df4cb95cd MD5 · raw file

  1. //===-- XCoreISelLowering.h - XCore DAG Lowering Interface ------*- C++ -*-===//
  2. //
  3. // The LLVM Compiler Infrastructure
  4. //
  5. // This file is distributed under the University of Illinois Open Source
  6. // License. See LICENSE.TXT for details.
  7. //
  8. //===----------------------------------------------------------------------===//
  9. //
  10. // This file defines the interfaces that XCore uses to lower LLVM code into a
  11. // selection DAG.
  12. //
  13. //===----------------------------------------------------------------------===//
  14. #ifndef XCOREISELLOWERING_H
  15. #define XCOREISELLOWERING_H
  16. #include "XCore.h"
  17. #include "llvm/CodeGen/SelectionDAG.h"
  18. #include "llvm/Target/TargetLowering.h"
  19. namespace llvm {
  20. // Forward delcarations
  21. class XCoreSubtarget;
  22. class XCoreTargetMachine;
  23. namespace XCoreISD {
  24. enum NodeType {
  25. // Start the numbering where the builtin ops and target ops leave off.
  26. FIRST_NUMBER = ISD::BUILTIN_OP_END,
  27. // Branch and link (call)
  28. BL,
  29. // pc relative address
  30. PCRelativeWrapper,
  31. // dp relative address
  32. DPRelativeWrapper,
  33. // cp relative address
  34. CPRelativeWrapper,
  35. // Store word to stack
  36. STWSP,
  37. // Corresponds to retsp instruction
  38. RETSP,
  39. // Corresponds to LADD instruction
  40. LADD,
  41. // Corresponds to LSUB instruction
  42. LSUB,
  43. // Corresponds to LMUL instruction
  44. LMUL,
  45. // Corresponds to MACCU instruction
  46. MACCU,
  47. // Corresponds to MACCS instruction
  48. MACCS,
  49. // Corresponds to CRC8 instruction
  50. CRC8,
  51. // Jumptable branch.
  52. BR_JT,
  53. // Jumptable branch using long branches for each entry.
  54. BR_JT32,
  55. // Memory barrier.
  56. MEMBARRIER
  57. };
  58. }
  59. //===--------------------------------------------------------------------===//
  60. // TargetLowering Implementation
  61. //===--------------------------------------------------------------------===//
  62. class XCoreTargetLowering : public TargetLowering
  63. {
  64. public:
  65. explicit XCoreTargetLowering(XCoreTargetMachine &TM);
  66. using TargetLowering::isZExtFree;
  67. virtual bool isZExtFree(SDValue Val, EVT VT2) const;
  68. virtual unsigned getJumpTableEncoding() const;
  69. virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
  70. /// LowerOperation - Provide custom lowering hooks for some operations.
  71. virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
  72. /// ReplaceNodeResults - Replace the results of node with an illegal result
  73. /// type with new values built out of custom code.
  74. ///
  75. virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
  76. SelectionDAG &DAG) const;
  77. /// getTargetNodeName - This method returns the name of a target specific
  78. // DAG node.
  79. virtual const char *getTargetNodeName(unsigned Opcode) const;
  80. virtual MachineBasicBlock *
  81. EmitInstrWithCustomInserter(MachineInstr *MI,
  82. MachineBasicBlock *MBB) const;
  83. virtual bool isLegalAddressingMode(const AddrMode &AM,
  84. Type *Ty) const;
  85. private:
  86. const XCoreTargetMachine &TM;
  87. const XCoreSubtarget &Subtarget;
  88. // Lower Operand helpers
  89. SDValue LowerCCCArguments(SDValue Chain,
  90. CallingConv::ID CallConv,
  91. bool isVarArg,
  92. const SmallVectorImpl<ISD::InputArg> &Ins,
  93. SDLoc dl, SelectionDAG &DAG,
  94. SmallVectorImpl<SDValue> &InVals) const;
  95. SDValue LowerCCCCallTo(SDValue Chain, SDValue Callee,
  96. CallingConv::ID CallConv, bool isVarArg,
  97. bool isTailCall,
  98. const SmallVectorImpl<ISD::OutputArg> &Outs,
  99. const SmallVectorImpl<SDValue> &OutVals,
  100. const SmallVectorImpl<ISD::InputArg> &Ins,
  101. SDLoc dl, SelectionDAG &DAG,
  102. SmallVectorImpl<SDValue> &InVals) const;
  103. SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
  104. CallingConv::ID CallConv, bool isVarArg,
  105. const SmallVectorImpl<ISD::InputArg> &Ins,
  106. SDLoc dl, SelectionDAG &DAG,
  107. SmallVectorImpl<SDValue> &InVals) const;
  108. SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
  109. SDValue getGlobalAddressWrapper(SDValue GA, const GlobalValue *GV,
  110. SelectionDAG &DAG) const;
  111. SDValue lowerLoadWordFromAlignedBasePlusOffset(SDLoc DL, SDValue Chain,
  112. SDValue Base, int64_t Offset,
  113. SelectionDAG &DAG) const;
  114. // Lower Operand specifics
  115. SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
  116. SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
  117. SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
  118. SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
  119. SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
  120. SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
  121. SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
  122. SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
  123. SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
  124. SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
  125. SDValue LowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
  126. SDValue LowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
  127. SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
  128. SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
  129. SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
  130. SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
  131. SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const;
  132. // Inline asm support
  133. std::pair<unsigned, const TargetRegisterClass*>
  134. getRegForInlineAsmConstraint(const std::string &Constraint,
  135. MVT VT) const;
  136. // Expand specifics
  137. SDValue TryExpandADDWithMul(SDNode *Op, SelectionDAG &DAG) const;
  138. SDValue ExpandADDSUB(SDNode *Op, SelectionDAG &DAG) const;
  139. virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
  140. virtual void computeMaskedBitsForTargetNode(const SDValue Op,
  141. APInt &KnownZero,
  142. APInt &KnownOne,
  143. const SelectionDAG &DAG,
  144. unsigned Depth = 0) const;
  145. virtual SDValue
  146. LowerFormalArguments(SDValue Chain,
  147. CallingConv::ID CallConv,
  148. bool isVarArg,
  149. const SmallVectorImpl<ISD::InputArg> &Ins,
  150. SDLoc dl, SelectionDAG &DAG,
  151. SmallVectorImpl<SDValue> &InVals) const;
  152. virtual SDValue
  153. LowerCall(TargetLowering::CallLoweringInfo &CLI,
  154. SmallVectorImpl<SDValue> &InVals) const;
  155. virtual SDValue
  156. LowerReturn(SDValue Chain,
  157. CallingConv::ID CallConv, bool isVarArg,
  158. const SmallVectorImpl<ISD::OutputArg> &Outs,
  159. const SmallVectorImpl<SDValue> &OutVals,
  160. SDLoc dl, SelectionDAG &DAG) const;
  161. virtual bool
  162. CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
  163. bool isVarArg,
  164. const SmallVectorImpl<ISD::OutputArg> &ArgsFlags,
  165. LLVMContext &Context) const;
  166. };
  167. }
  168. #endif // XCOREISELLOWERING_H