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/3rd_party/llvm/lib/Target/Sparc/SparcFrameLowering.cpp

https://code.google.com/p/softart/
C++ | 252 lines | 174 code | 44 blank | 34 comment | 32 complexity | 157a73f17dd2f3c4c2ab5b1f181e62b2 MD5 | raw file
Possible License(s): LGPL-2.1, BSD-3-Clause, JSON, MPL-2.0-no-copyleft-exception, GPL-2.0, GPL-3.0, LGPL-3.0, BSD-2-Clause
  1//===-- SparcFrameLowering.cpp - Sparc Frame Information ------------------===//
  2//
  3//                     The LLVM Compiler Infrastructure
  4//
  5// This file is distributed under the University of Illinois Open Source
  6// License. See LICENSE.TXT for details.
  7//
  8//===----------------------------------------------------------------------===//
  9//
 10// This file contains the Sparc implementation of TargetFrameLowering class.
 11//
 12//===----------------------------------------------------------------------===//
 13
 14#include "SparcFrameLowering.h"
 15#include "SparcInstrInfo.h"
 16#include "SparcMachineFunctionInfo.h"
 17#include "llvm/CodeGen/MachineFrameInfo.h"
 18#include "llvm/CodeGen/MachineFunction.h"
 19#include "llvm/CodeGen/MachineInstrBuilder.h"
 20#include "llvm/CodeGen/MachineModuleInfo.h"
 21#include "llvm/CodeGen/MachineRegisterInfo.h"
 22#include "llvm/IR/DataLayout.h"
 23#include "llvm/IR/Function.h"
 24#include "llvm/Support/CommandLine.h"
 25#include "llvm/Target/TargetOptions.h"
 26
 27using namespace llvm;
 28
 29static cl::opt<bool>
 30DisableLeafProc("disable-sparc-leaf-proc",
 31                cl::init(false),
 32                cl::desc("Disable Sparc leaf procedure optimization."),
 33                cl::Hidden);
 34
 35
 36void SparcFrameLowering::emitSPAdjustment(MachineFunction &MF,
 37                                          MachineBasicBlock &MBB,
 38                                          MachineBasicBlock::iterator MBBI,
 39                                          int NumBytes,
 40                                          unsigned ADDrr,
 41                                          unsigned ADDri) const {
 42
 43  DebugLoc dl = (MBBI != MBB.end()) ? MBBI->getDebugLoc() : DebugLoc();
 44  const SparcInstrInfo &TII =
 45    *static_cast<const SparcInstrInfo*>(MF.getTarget().getInstrInfo());
 46
 47  if (NumBytes >= -4096 && NumBytes < 4096) {
 48    BuildMI(MBB, MBBI, dl, TII.get(ADDri), SP::O6)
 49      .addReg(SP::O6).addImm(NumBytes);
 50    return;
 51  }
 52
 53  // Emit this the hard way.  This clobbers G1 which we always know is
 54  // available here.
 55  if (NumBytes >= 0) {
 56    // Emit nonnegative numbers with sethi + or.
 57    // sethi %hi(NumBytes), %g1
 58    // or %g1, %lo(NumBytes), %g1
 59    // add %sp, %g1, %sp
 60    BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1)
 61      .addImm(HI22(NumBytes));
 62    BuildMI(MBB, MBBI, dl, TII.get(SP::ORri), SP::G1)
 63      .addReg(SP::G1).addImm(LO10(NumBytes));
 64    BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6)
 65      .addReg(SP::O6).addReg(SP::G1);
 66    return ;
 67  }
 68
 69  // Emit negative numbers with sethi + xor.
 70  // sethi %hix(NumBytes), %g1
 71  // xor %g1, %lox(NumBytes), %g1
 72  // add %sp, %g1, %sp
 73  BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1)
 74    .addImm(HIX22(NumBytes));
 75  BuildMI(MBB, MBBI, dl, TII.get(SP::XORri), SP::G1)
 76    .addReg(SP::G1).addImm(LOX10(NumBytes));
 77  BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6)
 78    .addReg(SP::O6).addReg(SP::G1);
 79}
 80
 81void SparcFrameLowering::emitPrologue(MachineFunction &MF) const {
 82  SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
 83
 84  MachineBasicBlock &MBB = MF.front();
 85  MachineFrameInfo *MFI = MF.getFrameInfo();
 86  const SparcInstrInfo &TII =
 87    *static_cast<const SparcInstrInfo*>(MF.getTarget().getInstrInfo());
 88  MachineBasicBlock::iterator MBBI = MBB.begin();
 89  DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
 90
 91  // Get the number of bytes to allocate from the FrameInfo
 92  int NumBytes = (int) MFI->getStackSize();
 93
 94  unsigned SAVEri = SP::SAVEri;
 95  unsigned SAVErr = SP::SAVErr;
 96  if (FuncInfo->isLeafProc()) {
 97    if (NumBytes == 0)
 98      return;
 99    SAVEri = SP::ADDri;
100    SAVErr = SP::ADDrr;
101  }
102  NumBytes = - SubTarget.getAdjustedFrameSize(NumBytes);
103  emitSPAdjustment(MF, MBB, MBBI, NumBytes, SAVErr, SAVEri);
104
105  MachineModuleInfo &MMI = MF.getMMI();
106  const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
107  MCSymbol *FrameLabel = MMI.getContext().CreateTempSymbol();
108  BuildMI(MBB, MBBI, dl, TII.get(SP::PROLOG_LABEL)).addSym(FrameLabel);
109
110  unsigned regFP = MRI->getDwarfRegNum(SP::I6, true);
111
112  // Emit ".cfi_def_cfa_register 30".
113  MMI.addFrameInst(MCCFIInstruction::createDefCfaRegister(FrameLabel,
114                                                          regFP));
115  // Emit ".cfi_window_save".
116  MMI.addFrameInst(MCCFIInstruction::createWindowSave(FrameLabel));
117
118  unsigned regInRA = MRI->getDwarfRegNum(SP::I7, true);
119  unsigned regOutRA = MRI->getDwarfRegNum(SP::O7, true);
120  // Emit ".cfi_register 15, 31".
121  MMI.addFrameInst(MCCFIInstruction::createRegister(FrameLabel,
122                                                    regOutRA,
123                                                    regInRA));
124}
125
126void SparcFrameLowering::
127eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
128                              MachineBasicBlock::iterator I) const {
129  if (!hasReservedCallFrame(MF)) {
130    MachineInstr &MI = *I;
131    int Size = MI.getOperand(0).getImm();
132    if (MI.getOpcode() == SP::ADJCALLSTACKDOWN)
133      Size = -Size;
134
135    if (Size)
136      emitSPAdjustment(MF, MBB, I, Size, SP::ADDrr, SP::ADDri);
137  }
138  MBB.erase(I);
139}
140
141
142void SparcFrameLowering::emitEpilogue(MachineFunction &MF,
143                                  MachineBasicBlock &MBB) const {
144  SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
145  MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
146  const SparcInstrInfo &TII =
147    *static_cast<const SparcInstrInfo*>(MF.getTarget().getInstrInfo());
148  DebugLoc dl = MBBI->getDebugLoc();
149  assert(MBBI->getOpcode() == SP::RETL &&
150         "Can only put epilog before 'retl' instruction!");
151  if (!FuncInfo->isLeafProc()) {
152    BuildMI(MBB, MBBI, dl, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0)
153      .addReg(SP::G0);
154    return;
155  }
156  MachineFrameInfo *MFI = MF.getFrameInfo();
157
158  int NumBytes = (int) MFI->getStackSize();
159  if (NumBytes == 0)
160    return;
161
162  NumBytes = SubTarget.getAdjustedFrameSize(NumBytes);
163  emitSPAdjustment(MF, MBB, MBBI, NumBytes, SP::ADDrr, SP::ADDri);
164}
165
166bool SparcFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
167  // Reserve call frame if there are no variable sized objects on the stack.
168  return !MF.getFrameInfo()->hasVarSizedObjects();
169}
170
171// hasFP - Return true if the specified function should have a dedicated frame
172// pointer register.  This is true if the function has variable sized allocas or
173// if frame pointer elimination is disabled.
174bool SparcFrameLowering::hasFP(const MachineFunction &MF) const {
175  const MachineFrameInfo *MFI = MF.getFrameInfo();
176  return MF.getTarget().Options.DisableFramePointerElim(MF) ||
177    MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken();
178}
179
180
181static bool LLVM_ATTRIBUTE_UNUSED verifyLeafProcRegUse(MachineRegisterInfo *MRI)
182{
183
184  for (unsigned reg = SP::I0; reg <= SP::I7; ++reg)
185    if (MRI->isPhysRegUsed(reg))
186      return false;
187
188  for (unsigned reg = SP::L0; reg <= SP::L7; ++reg)
189    if (MRI->isPhysRegUsed(reg))
190      return false;
191
192  return true;
193}
194
195bool SparcFrameLowering::isLeafProc(MachineFunction &MF) const
196{
197
198  MachineRegisterInfo &MRI = MF.getRegInfo();
199  MachineFrameInfo    *MFI = MF.getFrameInfo();
200
201  return !(MFI->hasCalls()              // has calls
202           || MRI.isPhysRegUsed(SP::L0) // Too many registers needed
203           || MRI.isPhysRegUsed(SP::O6) // %SP is used
204           || hasFP(MF));               // need %FP
205}
206
207void SparcFrameLowering::remapRegsForLeafProc(MachineFunction &MF) const {
208
209  MachineRegisterInfo &MRI = MF.getRegInfo();
210
211  // Remap %i[0-7] to %o[0-7].
212  for (unsigned reg = SP::I0; reg <= SP::I7; ++reg) {
213    if (!MRI.isPhysRegUsed(reg))
214      continue;
215    unsigned mapped_reg = (reg - SP::I0 + SP::O0);
216    assert(!MRI.isPhysRegUsed(mapped_reg));
217
218    // Replace I register with O register.
219    MRI.replaceRegWith(reg, mapped_reg);
220
221    // Mark the reg unused.
222    MRI.setPhysRegUnused(reg);
223  }
224
225  // Rewrite MBB's Live-ins.
226  for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
227       MBB != E; ++MBB) {
228    for (unsigned reg = SP::I0; reg <= SP::I7; ++reg) {
229      if (!MBB->isLiveIn(reg))
230        continue;
231      MBB->removeLiveIn(reg);
232      MBB->addLiveIn(reg - SP::I0 + SP::O0);
233    }
234  }
235
236  assert(verifyLeafProcRegUse(&MRI));
237#ifdef XDEBUG
238  MF.verify(0, "After LeafProc Remapping");
239#endif
240}
241
242void SparcFrameLowering::processFunctionBeforeCalleeSavedScan
243                  (MachineFunction &MF, RegScavenger *RS) const {
244
245  if (!DisableLeafProc && isLeafProc(MF)) {
246    SparcMachineFunctionInfo *MFI = MF.getInfo<SparcMachineFunctionInfo>();
247    MFI->setLeafProc(true);
248
249    remapRegsForLeafProc(MF);
250  }
251
252}