/3rd_party/llvm/utils/TableGen/X86RecognizableInstr.h

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  1. //===- X86RecognizableInstr.h - Disassembler instruction spec ----*- C++ -*-===//
  2. //
  3. // The LLVM Compiler Infrastructure
  4. //
  5. // This file is distributed under the University of Illinois Open Source
  6. // License. See LICENSE.TXT for details.
  7. //
  8. //===----------------------------------------------------------------------===//
  9. //
  10. // This file is part of the X86 Disassembler Emitter.
  11. // It contains the interface of a single recognizable instruction.
  12. // Documentation for the disassembler emitter in general can be found in
  13. // X86DisasemblerEmitter.h.
  14. //
  15. //===----------------------------------------------------------------------===//
  16. #ifndef X86RECOGNIZABLEINSTR_H
  17. #define X86RECOGNIZABLEINSTR_H
  18. #include "CodeGenTarget.h"
  19. #include "X86DisassemblerTables.h"
  20. #include "llvm/ADT/SmallVector.h"
  21. #include "llvm/Support/DataTypes.h"
  22. #include "llvm/TableGen/Record.h"
  23. namespace llvm {
  24. namespace X86Disassembler {
  25. /// RecognizableInstr - Encapsulates all information required to decode a single
  26. /// instruction, as extracted from the LLVM instruction tables. Has methods
  27. /// to interpret the information available in the LLVM tables, and to emit the
  28. /// instruction into DisassemblerTables.
  29. class RecognizableInstr {
  30. private:
  31. /// The opcode of the instruction, as used in an MCInst
  32. InstrUID UID;
  33. /// The record from the .td files corresponding to this instruction
  34. const Record* Rec;
  35. /// The prefix field from the record
  36. uint8_t Prefix;
  37. /// The opcode field from the record; this is the opcode used in the Intel
  38. /// encoding and therefore distinct from the UID
  39. uint8_t Opcode;
  40. /// The form field from the record
  41. uint8_t Form;
  42. /// The segment override field from the record
  43. uint8_t SegOvr;
  44. /// The hasOpSizePrefix field from the record
  45. bool HasOpSizePrefix;
  46. /// The hasAdSizePrefix field from the record
  47. bool HasAdSizePrefix;
  48. /// The hasREX_WPrefix field from the record
  49. bool HasREX_WPrefix;
  50. /// The hasVEXPrefix field from the record
  51. bool HasVEXPrefix;
  52. /// The hasVEX_4VPrefix field from the record
  53. bool HasVEX_4VPrefix;
  54. /// The hasVEX_4VOp3Prefix field from the record
  55. bool HasVEX_4VOp3Prefix;
  56. /// The hasVEX_WPrefix field from the record
  57. bool HasVEX_WPrefix;
  58. /// Inferred from the operands; indicates whether the L bit in the VEX prefix is set
  59. bool HasVEX_LPrefix;
  60. /// The hasMemOp4Prefix field from the record
  61. bool HasMemOp4Prefix;
  62. /// The ignoreVEX_L field from the record
  63. bool IgnoresVEX_L;
  64. /// The hasEVEXPrefix field from the record
  65. bool HasEVEXPrefix;
  66. /// The hasEVEX_L2Prefix field from the record
  67. bool HasEVEX_L2Prefix;
  68. /// The hasEVEX_K field from the record
  69. bool HasEVEX_K;
  70. /// The hasEVEX_KZ field from the record
  71. bool HasEVEX_KZ;
  72. /// The hasEVEX_B field from the record
  73. bool HasEVEX_B;
  74. /// The hasLockPrefix field from the record
  75. bool HasLockPrefix;
  76. /// The isCodeGenOnly filed from the record
  77. bool IsCodeGenOnly;
  78. // Whether the instruction has the predicate "In64BitMode"
  79. bool Is64Bit;
  80. // Whether the instruction has the predicate "In32BitMode"
  81. bool Is32Bit;
  82. /// The instruction name as listed in the tables
  83. std::string Name;
  84. /// The AT&T AsmString for the instruction
  85. std::string AsmString;
  86. /// Indicates whether the instruction is SSE
  87. bool IsSSE;
  88. /// Indicates whether the instruction has FR operands - MOVs with FR operands
  89. /// are typically ignored
  90. bool HasFROperands;
  91. /// Indicates whether the instruction should be emitted into the decode
  92. /// tables; regardless, it will be emitted into the instruction info table
  93. bool ShouldBeEmitted;
  94. /// The operands of the instruction, as listed in the CodeGenInstruction.
  95. /// They are not one-to-one with operands listed in the MCInst; for example,
  96. /// memory operands expand to 5 operands in the MCInst
  97. const std::vector<CGIOperandList::OperandInfo>* Operands;
  98. /// The description of the instruction that is emitted into the instruction
  99. /// info table
  100. InstructionSpecifier* Spec;
  101. /// insnContext - Returns the primary context in which the instruction is
  102. /// valid.
  103. ///
  104. /// @return - The context in which the instruction is valid.
  105. InstructionContext insnContext() const;
  106. enum filter_ret {
  107. FILTER_STRONG, // instruction has no place in the instruction tables
  108. FILTER_WEAK, // instruction may conflict, and should be eliminated if
  109. // it does
  110. FILTER_NORMAL // instruction should have high priority and generate an
  111. // error if it conflcits with any other FILTER_NORMAL
  112. // instruction
  113. };
  114. /// filter - Determines whether the instruction should be decodable. Some
  115. /// instructions are pure intrinsics and use unencodable operands; many
  116. /// synthetic instructions are duplicates of other instructions; other
  117. /// instructions only differ in the logical way in which they are used, and
  118. /// have the same decoding. Because these would cause decode conflicts,
  119. /// they must be filtered out.
  120. ///
  121. /// @return - The degree of filtering to be applied (see filter_ret).
  122. filter_ret filter() const;
  123. /// hasFROperands - Returns true if any operand is a FR operand.
  124. bool hasFROperands() const;
  125. /// typeFromString - Translates an operand type from the string provided in
  126. /// the LLVM tables to an OperandType for use in the operand specifier.
  127. ///
  128. /// @param s - The string, as extracted by calling Rec->getName()
  129. /// on a CodeGenInstruction::OperandInfo.
  130. /// @param isSSE - Indicates whether the instruction is an SSE
  131. /// instruction. For SSE instructions, immediates are
  132. /// fixed-size rather than being affected by the
  133. /// mandatory OpSize prefix.
  134. /// @param hasREX_WPrefix - Indicates whether the instruction has a REX.W
  135. /// prefix. If it does, 32-bit register operands stay
  136. /// 32-bit regardless of the operand size.
  137. /// @param hasOpSizePrefix Indicates whether the instruction has an OpSize
  138. /// prefix. If it does not, then 16-bit register
  139. /// operands stay 16-bit.
  140. /// @return - The operand's type.
  141. static OperandType typeFromString(const std::string& s,
  142. bool isSSE,
  143. bool hasREX_WPrefix,
  144. bool hasOpSizePrefix);
  145. /// immediateEncodingFromString - Translates an immediate encoding from the
  146. /// string provided in the LLVM tables to an OperandEncoding for use in
  147. /// the operand specifier.
  148. ///
  149. /// @param s - See typeFromString().
  150. /// @param hasOpSizePrefix - Indicates whether the instruction has an OpSize
  151. /// prefix. If it does not, then 16-bit immediate
  152. /// operands stay 16-bit.
  153. /// @return - The operand's encoding.
  154. static OperandEncoding immediateEncodingFromString(const std::string &s,
  155. bool hasOpSizePrefix);
  156. /// rmRegisterEncodingFromString - Like immediateEncodingFromString, but
  157. /// handles operands that are in the REG field of the ModR/M byte.
  158. static OperandEncoding rmRegisterEncodingFromString(const std::string &s,
  159. bool hasOpSizePrefix);
  160. /// rmRegisterEncodingFromString - Like immediateEncodingFromString, but
  161. /// handles operands that are in the REG field of the ModR/M byte.
  162. static OperandEncoding roRegisterEncodingFromString(const std::string &s,
  163. bool hasOpSizePrefix);
  164. static OperandEncoding memoryEncodingFromString(const std::string &s,
  165. bool hasOpSizePrefix);
  166. static OperandEncoding relocationEncodingFromString(const std::string &s,
  167. bool hasOpSizePrefix);
  168. static OperandEncoding opcodeModifierEncodingFromString(const std::string &s,
  169. bool hasOpSizePrefix);
  170. static OperandEncoding vvvvRegisterEncodingFromString(const std::string &s,
  171. bool HasOpSizePrefix);
  172. static OperandEncoding writemaskRegisterEncodingFromString(const std::string &s,
  173. bool HasOpSizePrefix);
  174. /// handleOperand - Converts a single operand from the LLVM table format to
  175. /// the emitted table format, handling any duplicate operands it encounters
  176. /// and then one non-duplicate.
  177. ///
  178. /// @param optional - Determines whether to assert that the
  179. /// operand exists.
  180. /// @param operandIndex - The index into the generated operand table.
  181. /// Incremented by this function one or more
  182. /// times to reflect possible duplicate
  183. /// operands).
  184. /// @param physicalOperandIndex - The index of the current operand into the
  185. /// set of non-duplicate ('physical') operands.
  186. /// Incremented by this function once.
  187. /// @param numPhysicalOperands - The number of non-duplicate operands in the
  188. /// instructions.
  189. /// @param operandMapping - The operand mapping, which has an entry for
  190. /// each operand that indicates whether it is a
  191. /// duplicate, and of what.
  192. void handleOperand(bool optional,
  193. unsigned &operandIndex,
  194. unsigned &physicalOperandIndex,
  195. unsigned &numPhysicalOperands,
  196. const unsigned *operandMapping,
  197. OperandEncoding (*encodingFromString)
  198. (const std::string&,
  199. bool hasOpSizePrefix));
  200. /// shouldBeEmitted - Returns the shouldBeEmitted field. Although filter()
  201. /// filters out many instructions, at various points in decoding we
  202. /// determine that the instruction should not actually be decodable. In
  203. /// particular, MMX MOV instructions aren't emitted, but they're only
  204. /// identified during operand parsing.
  205. ///
  206. /// @return - true if at this point we believe the instruction should be
  207. /// emitted; false if not. This will return false if filter() returns false
  208. /// once emitInstructionSpecifier() has been called.
  209. bool shouldBeEmitted() const {
  210. return ShouldBeEmitted;
  211. }
  212. /// emitInstructionSpecifier - Loads the instruction specifier for the current
  213. /// instruction into a DisassemblerTables.
  214. ///
  215. /// \param tables The DisassemblerTables to populate with the specifier for
  216. /// the current instruction.
  217. void emitInstructionSpecifier(DisassemblerTables &tables);
  218. /// emitDecodePath - Populates the proper fields in the decode tables
  219. /// corresponding to the decode paths for this instruction.
  220. ///
  221. /// \param tables The DisassemblerTables to populate with the decode
  222. /// decode information for the current instruction.
  223. void emitDecodePath(DisassemblerTables &tables) const;
  224. /// Constructor - Initializes a RecognizableInstr with the appropriate fields
  225. /// from a CodeGenInstruction.
  226. ///
  227. /// \param tables The DisassemblerTables that the specifier will be added to.
  228. /// \param insn The CodeGenInstruction to extract information from.
  229. /// \param uid The unique ID of the current instruction.
  230. RecognizableInstr(DisassemblerTables &tables,
  231. const CodeGenInstruction &insn,
  232. InstrUID uid);
  233. public:
  234. /// processInstr - Accepts a CodeGenInstruction and loads decode information
  235. /// for it into a DisassemblerTables if appropriate.
  236. ///
  237. /// \param tables The DiassemblerTables to be populated with decode
  238. /// information.
  239. /// \param insn The CodeGenInstruction to be used as a source for this
  240. /// information.
  241. /// \param uid The unique ID of the instruction.
  242. static void processInstr(DisassemblerTables &tables,
  243. const CodeGenInstruction &insn,
  244. InstrUID uid);
  245. };
  246. } // namespace X86Disassembler
  247. } // namespace llvm
  248. #endif