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/drivers/net/enc28j60_hw.h

https://gitlab.com/TeamCarbonXtreme/android_kernel_samsung_bcm21553-common
C Header | 309 lines | 242 code | 17 blank | 50 comment | 0 complexity | a4faf31558ba804cbefd58b5bf690efd MD5 | raw file
  1/*
  2 * enc28j60_hw.h: EDTP FrameThrower style enc28j60 registers
  3 *
  4 * $Id: enc28j60_hw.h,v 1.9 2007/12/14 11:59:16 claudio Exp $
  5 */
  6
  7#ifndef _ENC28J60_HW_H
  8#define _ENC28J60_HW_H
  9
 10/*
 11 * ENC28J60 Control Registers
 12 * Control register definitions are a combination of address,
 13 * bank number, and Ethernet/MAC/PHY indicator bits.
 14 * - Register address	(bits 0-4)
 15 * - Bank number	(bits 5-6)
 16 * - MAC/MII indicator	(bit 7)
 17 */
 18#define ADDR_MASK	0x1F
 19#define BANK_MASK	0x60
 20#define SPRD_MASK	0x80
 21/* All-bank registers */
 22#define EIE		0x1B
 23#define EIR		0x1C
 24#define ESTAT		0x1D
 25#define ECON2		0x1E
 26#define ECON1		0x1F
 27/* Bank 0 registers */
 28#define ERDPTL		(0x00|0x00)
 29#define ERDPTH		(0x01|0x00)
 30#define EWRPTL		(0x02|0x00)
 31#define EWRPTH		(0x03|0x00)
 32#define ETXSTL		(0x04|0x00)
 33#define ETXSTH		(0x05|0x00)
 34#define ETXNDL		(0x06|0x00)
 35#define ETXNDH		(0x07|0x00)
 36#define ERXSTL		(0x08|0x00)
 37#define ERXSTH		(0x09|0x00)
 38#define ERXNDL		(0x0A|0x00)
 39#define ERXNDH		(0x0B|0x00)
 40#define ERXRDPTL	(0x0C|0x00)
 41#define ERXRDPTH	(0x0D|0x00)
 42#define ERXWRPTL	(0x0E|0x00)
 43#define ERXWRPTH	(0x0F|0x00)
 44#define EDMASTL		(0x10|0x00)
 45#define EDMASTH		(0x11|0x00)
 46#define EDMANDL		(0x12|0x00)
 47#define EDMANDH		(0x13|0x00)
 48#define EDMADSTL	(0x14|0x00)
 49#define EDMADSTH	(0x15|0x00)
 50#define EDMACSL		(0x16|0x00)
 51#define EDMACSH		(0x17|0x00)
 52/* Bank 1 registers */
 53#define EHT0		(0x00|0x20)
 54#define EHT1		(0x01|0x20)
 55#define EHT2		(0x02|0x20)
 56#define EHT3		(0x03|0x20)
 57#define EHT4		(0x04|0x20)
 58#define EHT5		(0x05|0x20)
 59#define EHT6		(0x06|0x20)
 60#define EHT7		(0x07|0x20)
 61#define EPMM0		(0x08|0x20)
 62#define EPMM1		(0x09|0x20)
 63#define EPMM2		(0x0A|0x20)
 64#define EPMM3		(0x0B|0x20)
 65#define EPMM4		(0x0C|0x20)
 66#define EPMM5		(0x0D|0x20)
 67#define EPMM6		(0x0E|0x20)
 68#define EPMM7		(0x0F|0x20)
 69#define EPMCSL		(0x10|0x20)
 70#define EPMCSH		(0x11|0x20)
 71#define EPMOL		(0x14|0x20)
 72#define EPMOH		(0x15|0x20)
 73#define EWOLIE		(0x16|0x20)
 74#define EWOLIR		(0x17|0x20)
 75#define ERXFCON		(0x18|0x20)
 76#define EPKTCNT		(0x19|0x20)
 77/* Bank 2 registers */
 78#define MACON1		(0x00|0x40|SPRD_MASK)
 79/* #define MACON2	(0x01|0x40|SPRD_MASK) */
 80#define MACON3		(0x02|0x40|SPRD_MASK)
 81#define MACON4		(0x03|0x40|SPRD_MASK)
 82#define MABBIPG		(0x04|0x40|SPRD_MASK)
 83#define MAIPGL		(0x06|0x40|SPRD_MASK)
 84#define MAIPGH		(0x07|0x40|SPRD_MASK)
 85#define MACLCON1	(0x08|0x40|SPRD_MASK)
 86#define MACLCON2	(0x09|0x40|SPRD_MASK)
 87#define MAMXFLL		(0x0A|0x40|SPRD_MASK)
 88#define MAMXFLH		(0x0B|0x40|SPRD_MASK)
 89#define MAPHSUP		(0x0D|0x40|SPRD_MASK)
 90#define MICON		(0x11|0x40|SPRD_MASK)
 91#define MICMD		(0x12|0x40|SPRD_MASK)
 92#define MIREGADR	(0x14|0x40|SPRD_MASK)
 93#define MIWRL		(0x16|0x40|SPRD_MASK)
 94#define MIWRH		(0x17|0x40|SPRD_MASK)
 95#define MIRDL		(0x18|0x40|SPRD_MASK)
 96#define MIRDH		(0x19|0x40|SPRD_MASK)
 97/* Bank 3 registers */
 98#define MAADR1		(0x00|0x60|SPRD_MASK)
 99#define MAADR0		(0x01|0x60|SPRD_MASK)
100#define MAADR3		(0x02|0x60|SPRD_MASK)
101#define MAADR2		(0x03|0x60|SPRD_MASK)
102#define MAADR5		(0x04|0x60|SPRD_MASK)
103#define MAADR4		(0x05|0x60|SPRD_MASK)
104#define EBSTSD		(0x06|0x60)
105#define EBSTCON		(0x07|0x60)
106#define EBSTCSL		(0x08|0x60)
107#define EBSTCSH		(0x09|0x60)
108#define MISTAT		(0x0A|0x60|SPRD_MASK)
109#define EREVID		(0x12|0x60)
110#define ECOCON		(0x15|0x60)
111#define EFLOCON		(0x17|0x60)
112#define EPAUSL		(0x18|0x60)
113#define EPAUSH		(0x19|0x60)
114/* PHY registers */
115#define PHCON1		0x00
116#define PHSTAT1		0x01
117#define PHHID1		0x02
118#define PHHID2		0x03
119#define PHCON2		0x10
120#define PHSTAT2		0x11
121#define PHIE		0x12
122#define PHIR		0x13
123#define PHLCON		0x14
124
125/* ENC28J60 EIE Register Bit Definitions */
126#define EIE_INTIE	0x80
127#define EIE_PKTIE	0x40
128#define EIE_DMAIE	0x20
129#define EIE_LINKIE	0x10
130#define EIE_TXIE	0x08
131/* #define EIE_WOLIE	0x04 (reserved) */
132#define EIE_TXERIE	0x02
133#define EIE_RXERIE	0x01
134/* ENC28J60 EIR Register Bit Definitions */
135#define EIR_PKTIF	0x40
136#define EIR_DMAIF	0x20
137#define EIR_LINKIF	0x10
138#define EIR_TXIF	0x08
139/* #define EIR_WOLIF	0x04 (reserved) */
140#define EIR_TXERIF	0x02
141#define EIR_RXERIF	0x01
142/* ENC28J60 ESTAT Register Bit Definitions */
143#define ESTAT_INT	0x80
144#define ESTAT_LATECOL	0x10
145#define ESTAT_RXBUSY	0x04
146#define ESTAT_TXABRT	0x02
147#define ESTAT_CLKRDY	0x01
148/* ENC28J60 ECON2 Register Bit Definitions */
149#define ECON2_AUTOINC	0x80
150#define ECON2_PKTDEC	0x40
151#define ECON2_PWRSV	0x20
152#define ECON2_VRPS	0x08
153/* ENC28J60 ECON1 Register Bit Definitions */
154#define ECON1_TXRST	0x80
155#define ECON1_RXRST	0x40
156#define ECON1_DMAST	0x20
157#define ECON1_CSUMEN	0x10
158#define ECON1_TXRTS	0x08
159#define ECON1_RXEN	0x04
160#define ECON1_BSEL1	0x02
161#define ECON1_BSEL0	0x01
162/* ENC28J60 MACON1 Register Bit Definitions */
163#define MACON1_LOOPBK	0x10
164#define MACON1_TXPAUS	0x08
165#define MACON1_RXPAUS	0x04
166#define MACON1_PASSALL	0x02
167#define MACON1_MARXEN	0x01
168/* ENC28J60 MACON2 Register Bit Definitions */
169#define MACON2_MARST	0x80
170#define MACON2_RNDRST	0x40
171#define MACON2_MARXRST	0x08
172#define MACON2_RFUNRST	0x04
173#define MACON2_MATXRST	0x02
174#define MACON2_TFUNRST	0x01
175/* ENC28J60 MACON3 Register Bit Definitions */
176#define MACON3_PADCFG2	0x80
177#define MACON3_PADCFG1	0x40
178#define MACON3_PADCFG0	0x20
179#define MACON3_TXCRCEN	0x10
180#define MACON3_PHDRLEN	0x08
181#define MACON3_HFRMLEN	0x04
182#define MACON3_FRMLNEN	0x02
183#define MACON3_FULDPX	0x01
184/* ENC28J60 MICMD Register Bit Definitions */
185#define MICMD_MIISCAN	0x02
186#define MICMD_MIIRD	0x01
187/* ENC28J60 MISTAT Register Bit Definitions */
188#define MISTAT_NVALID	0x04
189#define MISTAT_SCAN	0x02
190#define MISTAT_BUSY	0x01
191/* ENC28J60 ERXFCON Register Bit Definitions */
192#define ERXFCON_UCEN	0x80
193#define ERXFCON_ANDOR	0x40
194#define ERXFCON_CRCEN	0x20
195#define ERXFCON_PMEN	0x10
196#define ERXFCON_MPEN	0x08
197#define ERXFCON_HTEN	0x04
198#define ERXFCON_MCEN	0x02
199#define ERXFCON_BCEN	0x01
200
201/* ENC28J60 PHY PHCON1 Register Bit Definitions */
202#define PHCON1_PRST	0x8000
203#define PHCON1_PLOOPBK	0x4000
204#define PHCON1_PPWRSV	0x0800
205#define PHCON1_PDPXMD	0x0100
206/* ENC28J60 PHY PHSTAT1 Register Bit Definitions */
207#define PHSTAT1_PFDPX	0x1000
208#define PHSTAT1_PHDPX	0x0800
209#define PHSTAT1_LLSTAT	0x0004
210#define PHSTAT1_JBSTAT	0x0002
211/* ENC28J60 PHY PHSTAT2 Register Bit Definitions */
212#define PHSTAT2_TXSTAT	(1 << 13)
213#define PHSTAT2_RXSTAT	(1 << 12)
214#define PHSTAT2_COLSTAT	(1 << 11)
215#define PHSTAT2_LSTAT	(1 << 10)
216#define PHSTAT2_DPXSTAT	(1 << 9)
217#define PHSTAT2_PLRITY	(1 << 5)
218/* ENC28J60 PHY PHCON2 Register Bit Definitions */
219#define PHCON2_FRCLINK	0x4000
220#define PHCON2_TXDIS	0x2000
221#define PHCON2_JABBER	0x0400
222#define PHCON2_HDLDIS	0x0100
223/* ENC28J60 PHY PHIE Register Bit Definitions */
224#define PHIE_PLNKIE	(1 << 4)
225#define PHIE_PGEIE	(1 << 1)
226/* ENC28J60 PHY PHIR Register Bit Definitions */
227#define PHIR_PLNKIF	(1 << 4)
228#define PHIR_PGEIF	(1 << 1)
229
230/* ENC28J60 Packet Control Byte Bit Definitions */
231#define PKTCTRL_PHUGEEN		0x08
232#define PKTCTRL_PPADEN		0x04
233#define PKTCTRL_PCRCEN		0x02
234#define PKTCTRL_POVERRIDE	0x01
235
236/* ENC28J60 Transmit Status Vector */
237#define TSV_TXBYTECNT		0
238#define TSV_TXCOLLISIONCNT	16
239#define TSV_TXCRCERROR		20
240#define TSV_TXLENCHKERROR	21
241#define TSV_TXLENOUTOFRANGE	22
242#define TSV_TXDONE		23
243#define TSV_TXMULTICAST		24
244#define TSV_TXBROADCAST		25
245#define TSV_TXPACKETDEFER	26
246#define TSV_TXEXDEFER		27
247#define TSV_TXEXCOLLISION	28
248#define TSV_TXLATECOLLISION	29
249#define TSV_TXGIANT		30
250#define TSV_TXUNDERRUN		31
251#define TSV_TOTBYTETXONWIRE	32
252#define TSV_TXCONTROLFRAME	48
253#define TSV_TXPAUSEFRAME	49
254#define TSV_BACKPRESSUREAPP	50
255#define TSV_TXVLANTAGFRAME	51
256
257#define TSV_SIZE		7
258#define TSV_BYTEOF(x)		((x) / 8)
259#define TSV_BITMASK(x)		(1 << ((x) % 8))
260#define TSV_GETBIT(x, y)	(((x)[TSV_BYTEOF(y)] & TSV_BITMASK(y)) ? 1 : 0)
261
262/* ENC28J60 Receive Status Vector */
263#define RSV_RXLONGEVDROPEV	16
264#define RSV_CARRIEREV		18
265#define RSV_CRCERROR		20
266#define RSV_LENCHECKERR		21
267#define RSV_LENOUTOFRANGE	22
268#define RSV_RXOK		23
269#define RSV_RXMULTICAST		24
270#define RSV_RXBROADCAST		25
271#define RSV_DRIBBLENIBBLE	26
272#define RSV_RXCONTROLFRAME	27
273#define RSV_RXPAUSEFRAME	28
274#define RSV_RXUNKNOWNOPCODE	29
275#define RSV_RXTYPEVLAN		30
276
277#define RSV_SIZE		6
278#define RSV_BITMASK(x)		(1 << ((x) - 16))
279#define RSV_GETBIT(x, y)	(((x) & RSV_BITMASK(y)) ? 1 : 0)
280
281
282/* SPI operation codes */
283#define ENC28J60_READ_CTRL_REG	0x00
284#define ENC28J60_READ_BUF_MEM	0x3A
285#define ENC28J60_WRITE_CTRL_REG 0x40
286#define ENC28J60_WRITE_BUF_MEM	0x7A
287#define ENC28J60_BIT_FIELD_SET	0x80
288#define ENC28J60_BIT_FIELD_CLR	0xA0
289#define ENC28J60_SOFT_RESET	0xFF
290
291
292/* buffer boundaries applied to internal 8K ram
293 * entire available packet buffer space is allocated.
294 * Give TX buffer space for one full ethernet frame (~1500 bytes)
295 * receive buffer gets the rest */
296#define TXSTART_INIT		0x1A00
297#define TXEND_INIT		0x1FFF
298
299/* Put RX buffer at 0 as suggested by the Errata datasheet */
300#define RXSTART_INIT		0x0000
301#define RXEND_INIT		0x19FF
302
303/* maximum ethernet frame length */
304#define MAX_FRAMELEN		1518
305
306/* Prefered half duplex: LEDA: Link status LEDB: Rx/Tx activity */
307#define ENC28J60_LAMPS_MODE	0x3476
308
309#endif