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/drivers/usb/host/ehci-hcd.c

https://gitlab.com/stalker-android/linux-omap3
C | 1352 lines | 874 code | 193 blank | 285 comment | 139 complexity | 6b996f456481513e21c85146eb2ee5a2 MD5 | raw file
   1/*
   2 * Copyright (c) 2000-2004 by David Brownell
   3 *
   4 * This program is free software; you can redistribute it and/or modify it
   5 * under the terms of the GNU General Public License as published by the
   6 * Free Software Foundation; either version 2 of the License, or (at your
   7 * option) any later version.
   8 *
   9 * This program is distributed in the hope that it will be useful, but
  10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  11 * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12 * for more details.
  13 *
  14 * You should have received a copy of the GNU General Public License
  15 * along with this program; if not, write to the Free Software Foundation,
  16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  17 */
  18
  19#include <linux/module.h>
  20#include <linux/pci.h>
  21#include <linux/dmapool.h>
  22#include <linux/kernel.h>
  23#include <linux/delay.h>
  24#include <linux/ioport.h>
  25#include <linux/sched.h>
  26#include <linux/vmalloc.h>
  27#include <linux/errno.h>
  28#include <linux/init.h>
  29#include <linux/timer.h>
  30#include <linux/ktime.h>
  31#include <linux/list.h>
  32#include <linux/interrupt.h>
  33#include <linux/usb.h>
  34#include <linux/usb/hcd.h>
  35#include <linux/moduleparam.h>
  36#include <linux/dma-mapping.h>
  37#include <linux/debugfs.h>
  38#include <linux/slab.h>
  39#include <linux/uaccess.h>
  40
  41#include <asm/byteorder.h>
  42#include <asm/io.h>
  43#include <asm/irq.h>
  44#include <asm/system.h>
  45#include <asm/unaligned.h>
  46
  47/*-------------------------------------------------------------------------*/
  48
  49/*
  50 * EHCI hc_driver implementation ... experimental, incomplete.
  51 * Based on the final 1.0 register interface specification.
  52 *
  53 * USB 2.0 shows up in upcoming www.pcmcia.org technology.
  54 * First was PCMCIA, like ISA; then CardBus, which is PCI.
  55 * Next comes "CardBay", using USB 2.0 signals.
  56 *
  57 * Contains additional contributions by Brad Hards, Rory Bolt, and others.
  58 * Special thanks to Intel and VIA for providing host controllers to
  59 * test this driver on, and Cypress (including In-System Design) for
  60 * providing early devices for those host controllers to talk to!
  61 */
  62
  63#define DRIVER_AUTHOR "David Brownell"
  64#define DRIVER_DESC "USB 2.0 'Enhanced' Host Controller (EHCI) Driver"
  65
  66static const char	hcd_name [] = "ehci_hcd";
  67
  68static void ehci_hcd_cleanup(void);
  69static int ehci_hcd_init(void);
  70
  71#undef VERBOSE_DEBUG
  72#undef EHCI_URB_TRACE
  73
  74#ifdef DEBUG
  75#define EHCI_STATS
  76#endif
  77
  78/* magic numbers that can affect system performance */
  79#define	EHCI_TUNE_CERR		3	/* 0-3 qtd retries; 0 == don't stop */
  80#define	EHCI_TUNE_RL_HS		4	/* nak throttle; see 4.9 */
  81#define	EHCI_TUNE_RL_TT		0
  82#define	EHCI_TUNE_MULT_HS	1	/* 1-3 transactions/uframe; 4.10.3 */
  83#define	EHCI_TUNE_MULT_TT	1
  84/*
  85 * Some drivers think it's safe to schedule isochronous transfers more than
  86 * 256 ms into the future (partly as a result of an old bug in the scheduling
  87 * code).  In an attempt to avoid trouble, we will use a minimum scheduling
  88 * length of 512 frames instead of 256.
  89 */
  90#define	EHCI_TUNE_FLS		1	/* (medium) 512-frame schedule */
  91
  92#define EHCI_IAA_MSECS		10		/* arbitrary */
  93#define EHCI_IO_JIFFIES		(HZ/10)		/* io watchdog > irq_thresh */
  94#define EHCI_ASYNC_JIFFIES	(HZ/20)		/* async idle timeout */
  95#define EHCI_SHRINK_FRAMES	5		/* async qh unlink delay */
  96
  97/* Initial IRQ latency:  faster than hw default */
  98static int log2_irq_thresh = 0;		// 0 to 6
  99module_param (log2_irq_thresh, int, S_IRUGO);
 100MODULE_PARM_DESC (log2_irq_thresh, "log2 IRQ latency, 1-64 microframes");
 101
 102/* initial park setting:  slower than hw default */
 103static unsigned park = 0;
 104module_param (park, uint, S_IRUGO);
 105MODULE_PARM_DESC (park, "park setting; 1-3 back-to-back async packets");
 106
 107/* for flakey hardware, ignore overcurrent indicators */
 108static int ignore_oc = 0;
 109module_param (ignore_oc, bool, S_IRUGO);
 110MODULE_PARM_DESC (ignore_oc, "ignore bogus hardware overcurrent indications");
 111
 112/* for link power management(LPM) feature */
 113static unsigned int hird;
 114module_param(hird, int, S_IRUGO);
 115MODULE_PARM_DESC(hird, "host initiated resume duration, +1 for each 75us\n");
 116
 117#define	INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT)
 118
 119/*-------------------------------------------------------------------------*/
 120
 121#include "ehci.h"
 122#include "ehci-dbg.c"
 123
 124/*-------------------------------------------------------------------------*/
 125
 126static void
 127timer_action(struct ehci_hcd *ehci, enum ehci_timer_action action)
 128{
 129	/* Don't override timeouts which shrink or (later) disable
 130	 * the async ring; just the I/O watchdog.  Note that if a
 131	 * SHRINK were pending, OFF would never be requested.
 132	 */
 133	if (timer_pending(&ehci->watchdog)
 134			&& ((BIT(TIMER_ASYNC_SHRINK) | BIT(TIMER_ASYNC_OFF))
 135				& ehci->actions))
 136		return;
 137
 138	if (!test_and_set_bit(action, &ehci->actions)) {
 139		unsigned long t;
 140
 141		switch (action) {
 142		case TIMER_IO_WATCHDOG:
 143			if (!ehci->need_io_watchdog)
 144				return;
 145			t = EHCI_IO_JIFFIES;
 146			break;
 147		case TIMER_ASYNC_OFF:
 148			t = EHCI_ASYNC_JIFFIES;
 149			break;
 150		/* case TIMER_ASYNC_SHRINK: */
 151		default:
 152			/* add a jiffie since we synch against the
 153			 * 8 KHz uframe counter.
 154			 */
 155			t = DIV_ROUND_UP(EHCI_SHRINK_FRAMES * HZ, 1000) + 1;
 156			break;
 157		}
 158		mod_timer(&ehci->watchdog, t + jiffies);
 159	}
 160}
 161
 162/*-------------------------------------------------------------------------*/
 163
 164/*
 165 * handshake - spin reading hc until handshake completes or fails
 166 * @ptr: address of hc register to be read
 167 * @mask: bits to look at in result of read
 168 * @done: value of those bits when handshake succeeds
 169 * @usec: timeout in microseconds
 170 *
 171 * Returns negative errno, or zero on success
 172 *
 173 * Success happens when the "mask" bits have the specified value (hardware
 174 * handshake done).  There are two failure modes:  "usec" have passed (major
 175 * hardware flakeout), or the register reads as all-ones (hardware removed).
 176 *
 177 * That last failure should_only happen in cases like physical cardbus eject
 178 * before driver shutdown. But it also seems to be caused by bugs in cardbus
 179 * bridge shutdown:  shutting down the bridge before the devices using it.
 180 */
 181static int handshake (struct ehci_hcd *ehci, void __iomem *ptr,
 182		      u32 mask, u32 done, int usec)
 183{
 184	u32	result;
 185
 186	do {
 187		result = ehci_readl(ehci, ptr);
 188		if (result == ~(u32)0)		/* card removed */
 189			return -ENODEV;
 190		result &= mask;
 191		if (result == done)
 192			return 0;
 193		udelay (1);
 194		usec--;
 195	} while (usec > 0);
 196	return -ETIMEDOUT;
 197}
 198
 199/* check TDI/ARC silicon is in host mode */
 200static int tdi_in_host_mode (struct ehci_hcd *ehci)
 201{
 202	u32 __iomem	*reg_ptr;
 203	u32		tmp;
 204
 205	reg_ptr = (u32 __iomem *)(((u8 __iomem *)ehci->regs) + USBMODE);
 206	tmp = ehci_readl(ehci, reg_ptr);
 207	return (tmp & 3) == USBMODE_CM_HC;
 208}
 209
 210/* force HC to halt state from unknown (EHCI spec section 2.3) */
 211static int ehci_halt (struct ehci_hcd *ehci)
 212{
 213	u32	temp = ehci_readl(ehci, &ehci->regs->status);
 214
 215	/* disable any irqs left enabled by previous code */
 216	ehci_writel(ehci, 0, &ehci->regs->intr_enable);
 217
 218	if (ehci_is_TDI(ehci) && tdi_in_host_mode(ehci) == 0) {
 219		return 0;
 220	}
 221
 222	if ((temp & STS_HALT) != 0)
 223		return 0;
 224
 225	temp = ehci_readl(ehci, &ehci->regs->command);
 226	temp &= ~CMD_RUN;
 227	ehci_writel(ehci, temp, &ehci->regs->command);
 228	return handshake (ehci, &ehci->regs->status,
 229			  STS_HALT, STS_HALT, 16 * 125);
 230}
 231
 232static int handshake_on_error_set_halt(struct ehci_hcd *ehci, void __iomem *ptr,
 233				       u32 mask, u32 done, int usec)
 234{
 235	int error;
 236
 237	error = handshake(ehci, ptr, mask, done, usec);
 238	if (error) {
 239		ehci_halt(ehci);
 240		ehci_to_hcd(ehci)->state = HC_STATE_HALT;
 241		ehci_err(ehci, "force halt; handshake %p %08x %08x -> %d\n",
 242			ptr, mask, done, error);
 243	}
 244
 245	return error;
 246}
 247
 248/* put TDI/ARC silicon into EHCI mode */
 249static void tdi_reset (struct ehci_hcd *ehci)
 250{
 251	u32 __iomem	*reg_ptr;
 252	u32		tmp;
 253
 254	reg_ptr = (u32 __iomem *)(((u8 __iomem *)ehci->regs) + USBMODE);
 255	tmp = ehci_readl(ehci, reg_ptr);
 256	tmp |= USBMODE_CM_HC;
 257	/* The default byte access to MMR space is LE after
 258	 * controller reset. Set the required endian mode
 259	 * for transfer buffers to match the host microprocessor
 260	 */
 261	if (ehci_big_endian_mmio(ehci))
 262		tmp |= USBMODE_BE;
 263	ehci_writel(ehci, tmp, reg_ptr);
 264}
 265
 266/* reset a non-running (STS_HALT == 1) controller */
 267static int ehci_reset (struct ehci_hcd *ehci)
 268{
 269	int	retval;
 270	u32	command = ehci_readl(ehci, &ehci->regs->command);
 271
 272	/* If the EHCI debug controller is active, special care must be
 273	 * taken before and after a host controller reset */
 274	if (ehci->debug && !dbgp_reset_prep())
 275		ehci->debug = NULL;
 276
 277	command |= CMD_RESET;
 278	dbg_cmd (ehci, "reset", command);
 279	ehci_writel(ehci, command, &ehci->regs->command);
 280	ehci_to_hcd(ehci)->state = HC_STATE_HALT;
 281	ehci->next_statechange = jiffies;
 282	retval = handshake (ehci, &ehci->regs->command,
 283			    CMD_RESET, 0, 250 * 1000);
 284
 285	if (ehci->has_hostpc) {
 286		ehci_writel(ehci, USBMODE_EX_HC | USBMODE_EX_VBPS,
 287			(u32 __iomem *)(((u8 *)ehci->regs) + USBMODE_EX));
 288		ehci_writel(ehci, TXFIFO_DEFAULT,
 289			(u32 __iomem *)(((u8 *)ehci->regs) + TXFILLTUNING));
 290	}
 291	if (retval)
 292		return retval;
 293
 294	if (ehci_is_TDI(ehci))
 295		tdi_reset (ehci);
 296
 297	if (ehci->debug)
 298		dbgp_external_startup();
 299
 300	return retval;
 301}
 302
 303/* idle the controller (from running) */
 304static void ehci_quiesce (struct ehci_hcd *ehci)
 305{
 306	u32	temp;
 307
 308#ifdef DEBUG
 309	if (!HC_IS_RUNNING (ehci_to_hcd(ehci)->state))
 310		BUG ();
 311#endif
 312
 313	/* wait for any schedule enables/disables to take effect */
 314	temp = ehci_readl(ehci, &ehci->regs->command) << 10;
 315	temp &= STS_ASS | STS_PSS;
 316	if (handshake_on_error_set_halt(ehci, &ehci->regs->status,
 317					STS_ASS | STS_PSS, temp, 16 * 125))
 318		return;
 319
 320	/* then disable anything that's still active */
 321	temp = ehci_readl(ehci, &ehci->regs->command);
 322	temp &= ~(CMD_ASE | CMD_IAAD | CMD_PSE);
 323	ehci_writel(ehci, temp, &ehci->regs->command);
 324
 325	/* hardware can take 16 microframes to turn off ... */
 326	handshake_on_error_set_halt(ehci, &ehci->regs->status,
 327				    STS_ASS | STS_PSS, 0, 16 * 125);
 328}
 329
 330/*-------------------------------------------------------------------------*/
 331
 332static void end_unlink_async(struct ehci_hcd *ehci);
 333static void ehci_work(struct ehci_hcd *ehci);
 334
 335#include "ehci-hub.c"
 336#include "ehci-lpm.c"
 337#include "ehci-mem.c"
 338#include "ehci-q.c"
 339#include "ehci-sched.c"
 340
 341/*-------------------------------------------------------------------------*/
 342
 343static void ehci_iaa_watchdog(unsigned long param)
 344{
 345	struct ehci_hcd		*ehci = (struct ehci_hcd *) param;
 346	unsigned long		flags;
 347
 348	spin_lock_irqsave (&ehci->lock, flags);
 349
 350	/* Lost IAA irqs wedge things badly; seen first with a vt8235.
 351	 * So we need this watchdog, but must protect it against both
 352	 * (a) SMP races against real IAA firing and retriggering, and
 353	 * (b) clean HC shutdown, when IAA watchdog was pending.
 354	 */
 355	if (ehci->reclaim
 356			&& !timer_pending(&ehci->iaa_watchdog)
 357			&& HC_IS_RUNNING(ehci_to_hcd(ehci)->state)) {
 358		u32 cmd, status;
 359
 360		/* If we get here, IAA is *REALLY* late.  It's barely
 361		 * conceivable that the system is so busy that CMD_IAAD
 362		 * is still legitimately set, so let's be sure it's
 363		 * clear before we read STS_IAA.  (The HC should clear
 364		 * CMD_IAAD when it sets STS_IAA.)
 365		 */
 366		cmd = ehci_readl(ehci, &ehci->regs->command);
 367		if (cmd & CMD_IAAD)
 368			ehci_writel(ehci, cmd & ~CMD_IAAD,
 369					&ehci->regs->command);
 370
 371		/* If IAA is set here it either legitimately triggered
 372		 * before we cleared IAAD above (but _way_ late, so we'll
 373		 * still count it as lost) ... or a silicon erratum:
 374		 * - VIA seems to set IAA without triggering the IRQ;
 375		 * - IAAD potentially cleared without setting IAA.
 376		 */
 377		status = ehci_readl(ehci, &ehci->regs->status);
 378		if ((status & STS_IAA) || !(cmd & CMD_IAAD)) {
 379			COUNT (ehci->stats.lost_iaa);
 380			ehci_writel(ehci, STS_IAA, &ehci->regs->status);
 381		}
 382
 383		ehci_vdbg(ehci, "IAA watchdog: status %x cmd %x\n",
 384				status, cmd);
 385		end_unlink_async(ehci);
 386	}
 387
 388	spin_unlock_irqrestore(&ehci->lock, flags);
 389}
 390
 391static void ehci_watchdog(unsigned long param)
 392{
 393	struct ehci_hcd		*ehci = (struct ehci_hcd *) param;
 394	unsigned long		flags;
 395
 396	spin_lock_irqsave(&ehci->lock, flags);
 397
 398	/* stop async processing after it's idled a bit */
 399	if (test_bit (TIMER_ASYNC_OFF, &ehci->actions))
 400		start_unlink_async (ehci, ehci->async);
 401
 402	/* ehci could run by timer, without IRQs ... */
 403	ehci_work (ehci);
 404
 405	spin_unlock_irqrestore (&ehci->lock, flags);
 406}
 407
 408/* On some systems, leaving remote wakeup enabled prevents system shutdown.
 409 * The firmware seems to think that powering off is a wakeup event!
 410 * This routine turns off remote wakeup and everything else, on all ports.
 411 */
 412static void ehci_turn_off_all_ports(struct ehci_hcd *ehci)
 413{
 414	int	port = HCS_N_PORTS(ehci->hcs_params);
 415
 416	while (port--)
 417		ehci_writel(ehci, PORT_RWC_BITS,
 418				&ehci->regs->port_status[port]);
 419}
 420
 421/*
 422 * Halt HC, turn off all ports, and let the BIOS use the companion controllers.
 423 * Should be called with ehci->lock held.
 424 */
 425static void ehci_silence_controller(struct ehci_hcd *ehci)
 426{
 427	ehci_halt(ehci);
 428	ehci_turn_off_all_ports(ehci);
 429
 430	/* make BIOS/etc use companion controller during reboot */
 431	ehci_writel(ehci, 0, &ehci->regs->configured_flag);
 432
 433	/* unblock posted writes */
 434	ehci_readl(ehci, &ehci->regs->configured_flag);
 435}
 436
 437/* ehci_shutdown kick in for silicon on any bus (not just pci, etc).
 438 * This forcibly disables dma and IRQs, helping kexec and other cases
 439 * where the next system software may expect clean state.
 440 */
 441static void ehci_shutdown(struct usb_hcd *hcd)
 442{
 443	struct ehci_hcd	*ehci = hcd_to_ehci(hcd);
 444
 445	del_timer_sync(&ehci->watchdog);
 446	del_timer_sync(&ehci->iaa_watchdog);
 447
 448	spin_lock_irq(&ehci->lock);
 449	ehci_silence_controller(ehci);
 450	spin_unlock_irq(&ehci->lock);
 451}
 452
 453static void ehci_port_power (struct ehci_hcd *ehci, int is_on)
 454{
 455	unsigned port;
 456
 457	if (!HCS_PPC (ehci->hcs_params))
 458		return;
 459
 460	ehci_dbg (ehci, "...power%s ports...\n", is_on ? "up" : "down");
 461	for (port = HCS_N_PORTS (ehci->hcs_params); port > 0; )
 462		(void) ehci_hub_control(ehci_to_hcd(ehci),
 463				is_on ? SetPortFeature : ClearPortFeature,
 464				USB_PORT_FEAT_POWER,
 465				port--, NULL, 0);
 466	/* Flush those writes */
 467	ehci_readl(ehci, &ehci->regs->command);
 468	msleep(20);
 469}
 470
 471/*-------------------------------------------------------------------------*/
 472
 473/*
 474 * ehci_work is called from some interrupts, timers, and so on.
 475 * it calls driver completion functions, after dropping ehci->lock.
 476 */
 477static void ehci_work (struct ehci_hcd *ehci)
 478{
 479	timer_action_done (ehci, TIMER_IO_WATCHDOG);
 480
 481	/* another CPU may drop ehci->lock during a schedule scan while
 482	 * it reports urb completions.  this flag guards against bogus
 483	 * attempts at re-entrant schedule scanning.
 484	 */
 485	if (ehci->scanning)
 486		return;
 487	ehci->scanning = 1;
 488	scan_async (ehci);
 489	if (ehci->next_uframe != -1)
 490		scan_periodic (ehci);
 491	ehci->scanning = 0;
 492
 493	/* the IO watchdog guards against hardware or driver bugs that
 494	 * misplace IRQs, and should let us run completely without IRQs.
 495	 * such lossage has been observed on both VT6202 and VT8235.
 496	 */
 497	if (HC_IS_RUNNING (ehci_to_hcd(ehci)->state) &&
 498			(ehci->async->qh_next.ptr != NULL ||
 499			 ehci->periodic_sched != 0))
 500		timer_action (ehci, TIMER_IO_WATCHDOG);
 501}
 502
 503/*
 504 * Called when the ehci_hcd module is removed.
 505 */
 506static void ehci_stop (struct usb_hcd *hcd)
 507{
 508	struct ehci_hcd		*ehci = hcd_to_ehci (hcd);
 509
 510	ehci_dbg (ehci, "stop\n");
 511
 512	/* no more interrupts ... */
 513	del_timer_sync (&ehci->watchdog);
 514	del_timer_sync(&ehci->iaa_watchdog);
 515
 516	spin_lock_irq(&ehci->lock);
 517	if (HC_IS_RUNNING (hcd->state))
 518		ehci_quiesce (ehci);
 519
 520	ehci_silence_controller(ehci);
 521	ehci_reset (ehci);
 522	spin_unlock_irq(&ehci->lock);
 523
 524	remove_companion_file(ehci);
 525	remove_debug_files (ehci);
 526
 527	/* root hub is shut down separately (first, when possible) */
 528	spin_lock_irq (&ehci->lock);
 529	if (ehci->async)
 530		ehci_work (ehci);
 531	spin_unlock_irq (&ehci->lock);
 532	ehci_mem_cleanup (ehci);
 533
 534#ifdef	EHCI_STATS
 535	ehci_dbg (ehci, "irq normal %ld err %ld reclaim %ld (lost %ld)\n",
 536		ehci->stats.normal, ehci->stats.error, ehci->stats.reclaim,
 537		ehci->stats.lost_iaa);
 538	ehci_dbg (ehci, "complete %ld unlink %ld\n",
 539		ehci->stats.complete, ehci->stats.unlink);
 540#endif
 541
 542	dbg_status (ehci, "ehci_stop completed",
 543		    ehci_readl(ehci, &ehci->regs->status));
 544}
 545
 546/* one-time init, only for memory state */
 547static int ehci_init(struct usb_hcd *hcd)
 548{
 549	struct ehci_hcd		*ehci = hcd_to_ehci(hcd);
 550	u32			temp;
 551	int			retval;
 552	u32			hcc_params;
 553	struct ehci_qh_hw	*hw;
 554
 555	spin_lock_init(&ehci->lock);
 556
 557	/*
 558	 * keep io watchdog by default, those good HCDs could turn off it later
 559	 */
 560	ehci->need_io_watchdog = 1;
 561	init_timer(&ehci->watchdog);
 562	ehci->watchdog.function = ehci_watchdog;
 563	ehci->watchdog.data = (unsigned long) ehci;
 564
 565	init_timer(&ehci->iaa_watchdog);
 566	ehci->iaa_watchdog.function = ehci_iaa_watchdog;
 567	ehci->iaa_watchdog.data = (unsigned long) ehci;
 568
 569	hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params);
 570
 571	/*
 572	 * hw default: 1K periodic list heads, one per frame.
 573	 * periodic_size can shrink by USBCMD update if hcc_params allows.
 574	 */
 575	ehci->periodic_size = DEFAULT_I_TDPS;
 576	INIT_LIST_HEAD(&ehci->cached_itd_list);
 577	INIT_LIST_HEAD(&ehci->cached_sitd_list);
 578
 579	if (HCC_PGM_FRAMELISTLEN(hcc_params)) {
 580		/* periodic schedule size can be smaller than default */
 581		switch (EHCI_TUNE_FLS) {
 582		case 0:
 583			ehci->periodic_size = 1024; break;
 584		case 1:
 585			ehci->periodic_size = 512; break;
 586		case 2:
 587			ehci->periodic_size = 256; break;
 588		default:
 589			BUG();
 590		}
 591	}
 592	if ((retval = ehci_mem_init(ehci, GFP_KERNEL)) < 0)
 593		return retval;
 594
 595	/* controllers may cache some of the periodic schedule ... */
 596	if (HCC_ISOC_CACHE(hcc_params))		// full frame cache
 597		ehci->i_thresh = 2 + 8;
 598	else					// N microframes cached
 599		ehci->i_thresh = 2 + HCC_ISOC_THRES(hcc_params);
 600
 601	ehci->reclaim = NULL;
 602	ehci->next_uframe = -1;
 603	ehci->clock_frame = -1;
 604
 605	/*
 606	 * dedicate a qh for the async ring head, since we couldn't unlink
 607	 * a 'real' qh without stopping the async schedule [4.8].  use it
 608	 * as the 'reclamation list head' too.
 609	 * its dummy is used in hw_alt_next of many tds, to prevent the qh
 610	 * from automatically advancing to the next td after short reads.
 611	 */
 612	ehci->async->qh_next.qh = NULL;
 613	hw = ehci->async->hw;
 614	hw->hw_next = QH_NEXT(ehci, ehci->async->qh_dma);
 615	hw->hw_info1 = cpu_to_hc32(ehci, QH_HEAD);
 616	hw->hw_token = cpu_to_hc32(ehci, QTD_STS_HALT);
 617	hw->hw_qtd_next = EHCI_LIST_END(ehci);
 618	ehci->async->qh_state = QH_STATE_LINKED;
 619	hw->hw_alt_next = QTD_NEXT(ehci, ehci->async->dummy->qtd_dma);
 620
 621	/* clear interrupt enables, set irq latency */
 622	if (log2_irq_thresh < 0 || log2_irq_thresh > 6)
 623		log2_irq_thresh = 0;
 624	temp = 1 << (16 + log2_irq_thresh);
 625	if (HCC_PER_PORT_CHANGE_EVENT(hcc_params)) {
 626		ehci->has_ppcd = 1;
 627		ehci_dbg(ehci, "enable per-port change event\n");
 628		temp |= CMD_PPCEE;
 629	}
 630	if (HCC_CANPARK(hcc_params)) {
 631		/* HW default park == 3, on hardware that supports it (like
 632		 * NVidia and ALI silicon), maximizes throughput on the async
 633		 * schedule by avoiding QH fetches between transfers.
 634		 *
 635		 * With fast usb storage devices and NForce2, "park" seems to
 636		 * make problems:  throughput reduction (!), data errors...
 637		 */
 638		if (park) {
 639			park = min(park, (unsigned) 3);
 640			temp |= CMD_PARK;
 641			temp |= park << 8;
 642		}
 643		ehci_dbg(ehci, "park %d\n", park);
 644	}
 645	if (HCC_PGM_FRAMELISTLEN(hcc_params)) {
 646		/* periodic schedule size can be smaller than default */
 647		temp &= ~(3 << 2);
 648		temp |= (EHCI_TUNE_FLS << 2);
 649	}
 650	if (HCC_LPM(hcc_params)) {
 651		/* support link power management EHCI 1.1 addendum */
 652		ehci_dbg(ehci, "support lpm\n");
 653		ehci->has_lpm = 1;
 654		if (hird > 0xf) {
 655			ehci_dbg(ehci, "hird %d invalid, use default 0",
 656			hird);
 657			hird = 0;
 658		}
 659		temp |= hird << 24;
 660	}
 661	ehci->command = temp;
 662
 663	/* Accept arbitrarily long scatter-gather lists */
 664	if (!(hcd->driver->flags & HCD_LOCAL_MEM))
 665		hcd->self.sg_tablesize = ~0;
 666	return 0;
 667}
 668
 669/* start HC running; it's halted, ehci_init() has been run (once) */
 670static int ehci_run (struct usb_hcd *hcd)
 671{
 672	struct ehci_hcd		*ehci = hcd_to_ehci (hcd);
 673	int			retval;
 674	u32			temp;
 675	u32			hcc_params;
 676
 677	hcd->uses_new_polling = 1;
 678
 679	/* EHCI spec section 4.1 */
 680	if ((retval = ehci_reset(ehci)) != 0) {
 681		ehci_mem_cleanup(ehci);
 682		return retval;
 683	}
 684	ehci_writel(ehci, ehci->periodic_dma, &ehci->regs->frame_list);
 685	ehci_writel(ehci, (u32)ehci->async->qh_dma, &ehci->regs->async_next);
 686
 687	/*
 688	 * hcc_params controls whether ehci->regs->segment must (!!!)
 689	 * be used; it constrains QH/ITD/SITD and QTD locations.
 690	 * pci_pool consistent memory always uses segment zero.
 691	 * streaming mappings for I/O buffers, like pci_map_single(),
 692	 * can return segments above 4GB, if the device allows.
 693	 *
 694	 * NOTE:  the dma mask is visible through dma_supported(), so
 695	 * drivers can pass this info along ... like NETIF_F_HIGHDMA,
 696	 * Scsi_Host.highmem_io, and so forth.  It's readonly to all
 697	 * host side drivers though.
 698	 */
 699	hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params);
 700	if (HCC_64BIT_ADDR(hcc_params)) {
 701		ehci_writel(ehci, 0, &ehci->regs->segment);
 702#if 0
 703// this is deeply broken on almost all architectures
 704		if (!dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64)))
 705			ehci_info(ehci, "enabled 64bit DMA\n");
 706#endif
 707	}
 708
 709
 710	// Philips, Intel, and maybe others need CMD_RUN before the
 711	// root hub will detect new devices (why?); NEC doesn't
 712	ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
 713	ehci->command |= CMD_RUN;
 714	ehci_writel(ehci, ehci->command, &ehci->regs->command);
 715	dbg_cmd (ehci, "init", ehci->command);
 716
 717	/*
 718	 * Start, enabling full USB 2.0 functionality ... usb 1.1 devices
 719	 * are explicitly handed to companion controller(s), so no TT is
 720	 * involved with the root hub.  (Except where one is integrated,
 721	 * and there's no companion controller unless maybe for USB OTG.)
 722	 *
 723	 * Turning on the CF flag will transfer ownership of all ports
 724	 * from the companions to the EHCI controller.  If any of the
 725	 * companions are in the middle of a port reset at the time, it
 726	 * could cause trouble.  Write-locking ehci_cf_port_reset_rwsem
 727	 * guarantees that no resets are in progress.  After we set CF,
 728	 * a short delay lets the hardware catch up; new resets shouldn't
 729	 * be started before the port switching actions could complete.
 730	 */
 731	down_write(&ehci_cf_port_reset_rwsem);
 732	hcd->state = HC_STATE_RUNNING;
 733	ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
 734	ehci_readl(ehci, &ehci->regs->command);	/* unblock posted writes */
 735	msleep(5);
 736	up_write(&ehci_cf_port_reset_rwsem);
 737	ehci->last_periodic_enable = ktime_get_real();
 738
 739	temp = HC_VERSION(ehci_readl(ehci, &ehci->caps->hc_capbase));
 740	ehci_info (ehci,
 741		"USB %x.%x started, EHCI %x.%02x%s\n",
 742		((ehci->sbrn & 0xf0)>>4), (ehci->sbrn & 0x0f),
 743		temp >> 8, temp & 0xff,
 744		ignore_oc ? ", overcurrent ignored" : "");
 745
 746	ehci_writel(ehci, INTR_MASK,
 747		    &ehci->regs->intr_enable); /* Turn On Interrupts */
 748
 749	/* GRR this is run-once init(), being done every time the HC starts.
 750	 * So long as they're part of class devices, we can't do it init()
 751	 * since the class device isn't created that early.
 752	 */
 753	create_debug_files(ehci);
 754	create_companion_file(ehci);
 755
 756	return 0;
 757}
 758
 759/*-------------------------------------------------------------------------*/
 760
 761static irqreturn_t ehci_irq (struct usb_hcd *hcd)
 762{
 763	struct ehci_hcd		*ehci = hcd_to_ehci (hcd);
 764	u32			status, masked_status, pcd_status = 0, cmd;
 765	int			bh;
 766
 767	spin_lock (&ehci->lock);
 768
 769	status = ehci_readl(ehci, &ehci->regs->status);
 770
 771	/* e.g. cardbus physical eject */
 772	if (status == ~(u32) 0) {
 773		ehci_dbg (ehci, "device removed\n");
 774		goto dead;
 775	}
 776
 777	masked_status = status & INTR_MASK;
 778	if (!masked_status) {		/* irq sharing? */
 779		spin_unlock(&ehci->lock);
 780		return IRQ_NONE;
 781	}
 782
 783	/* clear (just) interrupts */
 784	ehci_writel(ehci, masked_status, &ehci->regs->status);
 785	cmd = ehci_readl(ehci, &ehci->regs->command);
 786	bh = 0;
 787
 788#ifdef	VERBOSE_DEBUG
 789	/* unrequested/ignored: Frame List Rollover */
 790	dbg_status (ehci, "irq", status);
 791#endif
 792
 793	/* INT, ERR, and IAA interrupt rates can be throttled */
 794
 795	/* normal [4.15.1.2] or error [4.15.1.1] completion */
 796	if (likely ((status & (STS_INT|STS_ERR)) != 0)) {
 797		if (likely ((status & STS_ERR) == 0))
 798			COUNT (ehci->stats.normal);
 799		else
 800			COUNT (ehci->stats.error);
 801		bh = 1;
 802	}
 803
 804	/* complete the unlinking of some qh [4.15.2.3] */
 805	if (status & STS_IAA) {
 806		/* guard against (alleged) silicon errata */
 807		if (cmd & CMD_IAAD) {
 808			ehci_writel(ehci, cmd & ~CMD_IAAD,
 809					&ehci->regs->command);
 810			ehci_dbg(ehci, "IAA with IAAD still set?\n");
 811		}
 812		if (ehci->reclaim) {
 813			COUNT(ehci->stats.reclaim);
 814			end_unlink_async(ehci);
 815		} else
 816			ehci_dbg(ehci, "IAA with nothing to reclaim?\n");
 817	}
 818
 819	/* remote wakeup [4.3.1] */
 820	if (status & STS_PCD) {
 821		unsigned	i = HCS_N_PORTS (ehci->hcs_params);
 822		u32		ppcd = 0;
 823
 824		/* kick root hub later */
 825		pcd_status = status;
 826
 827		/* resume root hub? */
 828		if (!(cmd & CMD_RUN))
 829			usb_hcd_resume_root_hub(hcd);
 830
 831		/* get per-port change detect bits */
 832		if (ehci->has_ppcd)
 833			ppcd = status >> 16;
 834
 835		while (i--) {
 836			int pstatus;
 837
 838			/* leverage per-port change bits feature */
 839			if (ehci->has_ppcd && !(ppcd & (1 << i)))
 840				continue;
 841			pstatus = ehci_readl(ehci,
 842					 &ehci->regs->port_status[i]);
 843
 844			if (pstatus & PORT_OWNER)
 845				continue;
 846			if (!(test_bit(i, &ehci->suspended_ports) &&
 847					((pstatus & PORT_RESUME) ||
 848						!(pstatus & PORT_SUSPEND)) &&
 849					(pstatus & PORT_PE) &&
 850					ehci->reset_done[i] == 0))
 851				continue;
 852
 853			/* start 20 msec resume signaling from this port,
 854			 * and make khubd collect PORT_STAT_C_SUSPEND to
 855			 * stop that signaling.  Use 5 ms extra for safety,
 856			 * like usb_port_resume() does.
 857			 */
 858			ehci->reset_done[i] = jiffies + msecs_to_jiffies(25);
 859			ehci_dbg (ehci, "port %d remote wakeup\n", i + 1);
 860			mod_timer(&hcd->rh_timer, ehci->reset_done[i]);
 861		}
 862	}
 863
 864	/* PCI errors [4.15.2.4] */
 865	if (unlikely ((status & STS_FATAL) != 0)) {
 866		ehci_err(ehci, "fatal error\n");
 867		dbg_cmd(ehci, "fatal", cmd);
 868		dbg_status(ehci, "fatal", status);
 869		ehci_halt(ehci);
 870dead:
 871		ehci_reset(ehci);
 872		ehci_writel(ehci, 0, &ehci->regs->configured_flag);
 873		/* generic layer kills/unlinks all urbs, then
 874		 * uses ehci_stop to clean up the rest
 875		 */
 876		bh = 1;
 877	}
 878
 879	if (bh)
 880		ehci_work (ehci);
 881	spin_unlock (&ehci->lock);
 882	if (pcd_status)
 883		usb_hcd_poll_rh_status(hcd);
 884	return IRQ_HANDLED;
 885}
 886
 887/*-------------------------------------------------------------------------*/
 888
 889/*
 890 * non-error returns are a promise to giveback() the urb later
 891 * we drop ownership so next owner (or urb unlink) can get it
 892 *
 893 * urb + dev is in hcd.self.controller.urb_list
 894 * we're queueing TDs onto software and hardware lists
 895 *
 896 * hcd-specific init for hcpriv hasn't been done yet
 897 *
 898 * NOTE:  control, bulk, and interrupt share the same code to append TDs
 899 * to a (possibly active) QH, and the same QH scanning code.
 900 */
 901static int ehci_urb_enqueue (
 902	struct usb_hcd	*hcd,
 903	struct urb	*urb,
 904	gfp_t		mem_flags
 905) {
 906	struct ehci_hcd		*ehci = hcd_to_ehci (hcd);
 907	struct list_head	qtd_list;
 908
 909	INIT_LIST_HEAD (&qtd_list);
 910
 911	switch (usb_pipetype (urb->pipe)) {
 912	case PIPE_CONTROL:
 913		/* qh_completions() code doesn't handle all the fault cases
 914		 * in multi-TD control transfers.  Even 1KB is rare anyway.
 915		 */
 916		if (urb->transfer_buffer_length > (16 * 1024))
 917			return -EMSGSIZE;
 918		/* FALLTHROUGH */
 919	/* case PIPE_BULK: */
 920	default:
 921		if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags))
 922			return -ENOMEM;
 923		return submit_async(ehci, urb, &qtd_list, mem_flags);
 924
 925	case PIPE_INTERRUPT:
 926		if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags))
 927			return -ENOMEM;
 928		return intr_submit(ehci, urb, &qtd_list, mem_flags);
 929
 930	case PIPE_ISOCHRONOUS:
 931		if (urb->dev->speed == USB_SPEED_HIGH)
 932			return itd_submit (ehci, urb, mem_flags);
 933		else
 934			return sitd_submit (ehci, urb, mem_flags);
 935	}
 936}
 937
 938static void unlink_async (struct ehci_hcd *ehci, struct ehci_qh *qh)
 939{
 940	/* failfast */
 941	if (!HC_IS_RUNNING(ehci_to_hcd(ehci)->state) && ehci->reclaim)
 942		end_unlink_async(ehci);
 943
 944	/* If the QH isn't linked then there's nothing we can do
 945	 * unless we were called during a giveback, in which case
 946	 * qh_completions() has to deal with it.
 947	 */
 948	if (qh->qh_state != QH_STATE_LINKED) {
 949		if (qh->qh_state == QH_STATE_COMPLETING)
 950			qh->needs_rescan = 1;
 951		return;
 952	}
 953
 954	/* defer till later if busy */
 955	if (ehci->reclaim) {
 956		struct ehci_qh		*last;
 957
 958		for (last = ehci->reclaim;
 959				last->reclaim;
 960				last = last->reclaim)
 961			continue;
 962		qh->qh_state = QH_STATE_UNLINK_WAIT;
 963		last->reclaim = qh;
 964
 965	/* start IAA cycle */
 966	} else
 967		start_unlink_async (ehci, qh);
 968}
 969
 970/* remove from hardware lists
 971 * completions normally happen asynchronously
 972 */
 973
 974static int ehci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
 975{
 976	struct ehci_hcd		*ehci = hcd_to_ehci (hcd);
 977	struct ehci_qh		*qh;
 978	unsigned long		flags;
 979	int			rc;
 980
 981	spin_lock_irqsave (&ehci->lock, flags);
 982	rc = usb_hcd_check_unlink_urb(hcd, urb, status);
 983	if (rc)
 984		goto done;
 985
 986	switch (usb_pipetype (urb->pipe)) {
 987	// case PIPE_CONTROL:
 988	// case PIPE_BULK:
 989	default:
 990		qh = (struct ehci_qh *) urb->hcpriv;
 991		if (!qh)
 992			break;
 993		switch (qh->qh_state) {
 994		case QH_STATE_LINKED:
 995		case QH_STATE_COMPLETING:
 996			unlink_async(ehci, qh);
 997			break;
 998		case QH_STATE_UNLINK:
 999		case QH_STATE_UNLINK_WAIT:
1000			/* already started */
1001			break;
1002		case QH_STATE_IDLE:
1003			/* QH might be waiting for a Clear-TT-Buffer */
1004			qh_completions(ehci, qh);
1005			break;
1006		}
1007		break;
1008
1009	case PIPE_INTERRUPT:
1010		qh = (struct ehci_qh *) urb->hcpriv;
1011		if (!qh)
1012			break;
1013		switch (qh->qh_state) {
1014		case QH_STATE_LINKED:
1015		case QH_STATE_COMPLETING:
1016			intr_deschedule (ehci, qh);
1017			break;
1018		case QH_STATE_IDLE:
1019			qh_completions (ehci, qh);
1020			break;
1021		default:
1022			ehci_dbg (ehci, "bogus qh %p state %d\n",
1023					qh, qh->qh_state);
1024			goto done;
1025		}
1026		break;
1027
1028	case PIPE_ISOCHRONOUS:
1029		// itd or sitd ...
1030
1031		// wait till next completion, do it then.
1032		// completion irqs can wait up to 1024 msec,
1033		break;
1034	}
1035done:
1036	spin_unlock_irqrestore (&ehci->lock, flags);
1037	return rc;
1038}
1039
1040/*-------------------------------------------------------------------------*/
1041
1042// bulk qh holds the data toggle
1043
1044static void
1045ehci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep)
1046{
1047	struct ehci_hcd		*ehci = hcd_to_ehci (hcd);
1048	unsigned long		flags;
1049	struct ehci_qh		*qh, *tmp;
1050
1051	/* ASSERT:  any requests/urbs are being unlinked */
1052	/* ASSERT:  nobody can be submitting urbs for this any more */
1053
1054rescan:
1055	spin_lock_irqsave (&ehci->lock, flags);
1056	qh = ep->hcpriv;
1057	if (!qh)
1058		goto done;
1059
1060	/* endpoints can be iso streams.  for now, we don't
1061	 * accelerate iso completions ... so spin a while.
1062	 */
1063	if (qh->hw == NULL) {
1064		ehci_vdbg (ehci, "iso delay\n");
1065		goto idle_timeout;
1066	}
1067
1068	if (!HC_IS_RUNNING (hcd->state))
1069		qh->qh_state = QH_STATE_IDLE;
1070	switch (qh->qh_state) {
1071	case QH_STATE_LINKED:
1072	case QH_STATE_COMPLETING:
1073		for (tmp = ehci->async->qh_next.qh;
1074				tmp && tmp != qh;
1075				tmp = tmp->qh_next.qh)
1076			continue;
1077		/* periodic qh self-unlinks on empty, and a COMPLETING qh
1078		 * may already be unlinked.
1079		 */
1080		if (tmp)
1081			unlink_async(ehci, qh);
1082		/* FALL THROUGH */
1083	case QH_STATE_UNLINK:		/* wait for hw to finish? */
1084	case QH_STATE_UNLINK_WAIT:
1085idle_timeout:
1086		spin_unlock_irqrestore (&ehci->lock, flags);
1087		schedule_timeout_uninterruptible(1);
1088		goto rescan;
1089	case QH_STATE_IDLE:		/* fully unlinked */
1090		if (qh->clearing_tt)
1091			goto idle_timeout;
1092		if (list_empty (&qh->qtd_list)) {
1093			qh_put (qh);
1094			break;
1095		}
1096		/* else FALL THROUGH */
1097	default:
1098		/* caller was supposed to have unlinked any requests;
1099		 * that's not our job.  just leak this memory.
1100		 */
1101		ehci_err (ehci, "qh %p (#%02x) state %d%s\n",
1102			qh, ep->desc.bEndpointAddress, qh->qh_state,
1103			list_empty (&qh->qtd_list) ? "" : "(has tds)");
1104		break;
1105	}
1106	ep->hcpriv = NULL;
1107done:
1108	spin_unlock_irqrestore (&ehci->lock, flags);
1109}
1110
1111static void
1112ehci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep)
1113{
1114	struct ehci_hcd		*ehci = hcd_to_ehci(hcd);
1115	struct ehci_qh		*qh;
1116	int			eptype = usb_endpoint_type(&ep->desc);
1117	int			epnum = usb_endpoint_num(&ep->desc);
1118	int			is_out = usb_endpoint_dir_out(&ep->desc);
1119	unsigned long		flags;
1120
1121	if (eptype != USB_ENDPOINT_XFER_BULK && eptype != USB_ENDPOINT_XFER_INT)
1122		return;
1123
1124	spin_lock_irqsave(&ehci->lock, flags);
1125	qh = ep->hcpriv;
1126
1127	/* For Bulk and Interrupt endpoints we maintain the toggle state
1128	 * in the hardware; the toggle bits in udev aren't used at all.
1129	 * When an endpoint is reset by usb_clear_halt() we must reset
1130	 * the toggle bit in the QH.
1131	 */
1132	if (qh) {
1133		usb_settoggle(qh->dev, epnum, is_out, 0);
1134		if (!list_empty(&qh->qtd_list)) {
1135			WARN_ONCE(1, "clear_halt for a busy endpoint\n");
1136		} else if (qh->qh_state == QH_STATE_LINKED ||
1137				qh->qh_state == QH_STATE_COMPLETING) {
1138
1139			/* The toggle value in the QH can't be updated
1140			 * while the QH is active.  Unlink it now;
1141			 * re-linking will call qh_refresh().
1142			 */
1143			if (eptype == USB_ENDPOINT_XFER_BULK)
1144				unlink_async(ehci, qh);
1145			else
1146				intr_deschedule(ehci, qh);
1147		}
1148	}
1149	spin_unlock_irqrestore(&ehci->lock, flags);
1150}
1151
1152static int ehci_get_frame (struct usb_hcd *hcd)
1153{
1154	struct ehci_hcd		*ehci = hcd_to_ehci (hcd);
1155	return (ehci_readl(ehci, &ehci->regs->frame_index) >> 3) %
1156		ehci->periodic_size;
1157}
1158
1159static void ehci_omap_recover_work(struct work_struct *data)
1160{
1161	ehci_hcd_cleanup();
1162	ehci_hcd_init();
1163}
1164/*-------------------------------------------------------------------------*/
1165
1166MODULE_DESCRIPTION(DRIVER_DESC);
1167MODULE_AUTHOR (DRIVER_AUTHOR);
1168MODULE_LICENSE ("GPL");
1169
1170#ifdef CONFIG_PCI
1171#include "ehci-pci.c"
1172#define	PCI_DRIVER		ehci_pci_driver
1173#endif
1174
1175#ifdef CONFIG_USB_EHCI_FSL
1176#include "ehci-fsl.c"
1177#define	PLATFORM_DRIVER		ehci_fsl_driver
1178#endif
1179
1180#ifdef CONFIG_USB_EHCI_MXC
1181#include "ehci-mxc.c"
1182#define PLATFORM_DRIVER		ehci_mxc_driver
1183#endif
1184
1185#ifdef CONFIG_SOC_AU1200
1186#include "ehci-au1xxx.c"
1187#define	PLATFORM_DRIVER		ehci_hcd_au1xxx_driver
1188#endif
1189
1190#ifdef CONFIG_ARCH_OMAP3
1191#include "ehci-omap.c"
1192#define        PLATFORM_DRIVER         ehci_hcd_omap_driver
1193#endif
1194
1195#ifdef CONFIG_PPC_PS3
1196#include "ehci-ps3.c"
1197#define	PS3_SYSTEM_BUS_DRIVER	ps3_ehci_driver
1198#endif
1199
1200#ifdef CONFIG_USB_EHCI_HCD_PPC_OF
1201#include "ehci-ppc-of.c"
1202#define OF_PLATFORM_DRIVER	ehci_hcd_ppc_of_driver
1203#endif
1204
1205#ifdef CONFIG_XPS_USB_HCD_XILINX
1206#include "ehci-xilinx-of.c"
1207#define XILINX_OF_PLATFORM_DRIVER	ehci_hcd_xilinx_of_driver
1208#endif
1209
1210#ifdef CONFIG_PLAT_ORION
1211#include "ehci-orion.c"
1212#define	PLATFORM_DRIVER		ehci_orion_driver
1213#endif
1214
1215#ifdef CONFIG_ARCH_IXP4XX
1216#include "ehci-ixp4xx.c"
1217#define	PLATFORM_DRIVER		ixp4xx_ehci_driver
1218#endif
1219
1220#ifdef CONFIG_USB_W90X900_EHCI
1221#include "ehci-w90x900.c"
1222#define	PLATFORM_DRIVER		ehci_hcd_w90x900_driver
1223#endif
1224
1225#ifdef CONFIG_ARCH_AT91
1226#include "ehci-atmel.c"
1227#define	PLATFORM_DRIVER		ehci_atmel_driver
1228#endif
1229
1230#ifdef CONFIG_USB_OCTEON_EHCI
1231#include "ehci-octeon.c"
1232#define PLATFORM_DRIVER		ehci_octeon_driver
1233#endif
1234
1235#if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \
1236    !defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER) && \
1237    !defined(XILINX_OF_PLATFORM_DRIVER)
1238#error "missing bus glue for ehci-hcd"
1239#endif
1240
1241static int ehci_hcd_init(void)
1242{
1243	int retval = 0;
1244
1245	if (usb_disabled())
1246		return -ENODEV;
1247
1248	printk(KERN_INFO "%s: " DRIVER_DESC "\n", hcd_name);
1249	set_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
1250	if (test_bit(USB_UHCI_LOADED, &usb_hcds_loaded) ||
1251			test_bit(USB_OHCI_LOADED, &usb_hcds_loaded))
1252		printk(KERN_WARNING "Warning! ehci_hcd should always be loaded"
1253				" before uhci_hcd and ohci_hcd, not after\n");
1254
1255	pr_debug("%s: block sizes: qh %Zd qtd %Zd itd %Zd sitd %Zd\n",
1256		 hcd_name,
1257		 sizeof(struct ehci_qh), sizeof(struct ehci_qtd),
1258		 sizeof(struct ehci_itd), sizeof(struct ehci_sitd));
1259
1260#ifdef DEBUG
1261	ehci_debug_root = debugfs_create_dir("ehci", usb_debug_root);
1262	if (!ehci_debug_root) {
1263		retval = -ENOENT;
1264		goto err_debug;
1265	}
1266#endif
1267
1268#ifdef PLATFORM_DRIVER
1269	retval = platform_driver_register(&PLATFORM_DRIVER);
1270	if (retval < 0)
1271		goto clean0;
1272#endif
1273
1274#ifdef PCI_DRIVER
1275	retval = pci_register_driver(&PCI_DRIVER);
1276	if (retval < 0)
1277		goto clean1;
1278#endif
1279
1280#ifdef PS3_SYSTEM_BUS_DRIVER
1281	retval = ps3_ehci_driver_register(&PS3_SYSTEM_BUS_DRIVER);
1282	if (retval < 0)
1283		goto clean2;
1284#endif
1285
1286#ifdef OF_PLATFORM_DRIVER
1287	retval = of_register_platform_driver(&OF_PLATFORM_DRIVER);
1288	if (retval < 0)
1289		goto clean3;
1290#endif
1291
1292#ifdef XILINX_OF_PLATFORM_DRIVER
1293	retval = of_register_platform_driver(&XILINX_OF_PLATFORM_DRIVER);
1294	if (retval < 0)
1295		goto clean4;
1296#endif
1297	return retval;
1298
1299#ifdef XILINX_OF_PLATFORM_DRIVER
1300	/* of_unregister_platform_driver(&XILINX_OF_PLATFORM_DRIVER); */
1301clean4:
1302#endif
1303#ifdef OF_PLATFORM_DRIVER
1304	of_unregister_platform_driver(&OF_PLATFORM_DRIVER);
1305clean3:
1306#endif
1307#ifdef PS3_SYSTEM_BUS_DRIVER
1308	ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1309clean2:
1310#endif
1311#ifdef PCI_DRIVER
1312	pci_unregister_driver(&PCI_DRIVER);
1313clean1:
1314#endif
1315#ifdef PLATFORM_DRIVER
1316	platform_driver_unregister(&PLATFORM_DRIVER);
1317clean0:
1318#endif
1319#ifdef DEBUG
1320	debugfs_remove(ehci_debug_root);
1321	ehci_debug_root = NULL;
1322err_debug:
1323#endif
1324	clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
1325	return retval;
1326}
1327module_init(ehci_hcd_init);
1328
1329static void ehci_hcd_cleanup(void)
1330{
1331#ifdef XILINX_OF_PLATFORM_DRIVER
1332	of_unregister_platform_driver(&XILINX_OF_PLATFORM_DRIVER);
1333#endif
1334#ifdef OF_PLATFORM_DRIVER
1335	of_unregister_platform_driver(&OF_PLATFORM_DRIVER);
1336#endif
1337#ifdef PLATFORM_DRIVER
1338	platform_driver_unregister(&PLATFORM_DRIVER);
1339#endif
1340#ifdef PCI_DRIVER
1341	pci_unregister_driver(&PCI_DRIVER);
1342#endif
1343#ifdef PS3_SYSTEM_BUS_DRIVER
1344	ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1345#endif
1346#ifdef DEBUG
1347	debugfs_remove(ehci_debug_root);
1348#endif
1349	clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
1350}
1351module_exit(ehci_hcd_cleanup);
1352