/arch/arm/boot/dts/exynos5440.dtsi

https://gitlab.com/veo-labs/linux · Device Tree · 323 lines · 278 code · 34 blank · 11 comment · 0 complexity · 11ff801cfcefbd45fc8e4a8b6f72efb1 MD5 · raw file

  1. /*
  2. * SAMSUNG EXYNOS5440 SoC device tree source
  3. *
  4. * Copyright (c) 2012 Samsung Electronics Co., Ltd.
  5. * http://www.samsung.com
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. */
  11. #include <dt-bindings/clock/exynos5440.h>
  12. #include "skeleton.dtsi"
  13. / {
  14. compatible = "samsung,exynos5440", "samsung,exynos5";
  15. interrupt-parent = <&gic>;
  16. aliases {
  17. serial0 = &serial_0;
  18. serial1 = &serial_1;
  19. spi0 = &spi_0;
  20. tmuctrl0 = &tmuctrl_0;
  21. tmuctrl1 = &tmuctrl_1;
  22. tmuctrl2 = &tmuctrl_2;
  23. };
  24. clock: clock-controller@160000 {
  25. compatible = "samsung,exynos5440-clock";
  26. reg = <0x160000 0x1000>;
  27. #clock-cells = <1>;
  28. };
  29. gic: interrupt-controller@2E0000 {
  30. compatible = "arm,cortex-a15-gic";
  31. #interrupt-cells = <3>;
  32. interrupt-controller;
  33. reg = <0x2E1000 0x1000>,
  34. <0x2E2000 0x1000>,
  35. <0x2E4000 0x2000>,
  36. <0x2E6000 0x2000>;
  37. interrupts = <1 9 0xf04>;
  38. };
  39. cpus {
  40. #address-cells = <1>;
  41. #size-cells = <0>;
  42. cpu@0 {
  43. device_type = "cpu";
  44. compatible = "arm,cortex-a15";
  45. reg = <0>;
  46. };
  47. cpu@1 {
  48. device_type = "cpu";
  49. compatible = "arm,cortex-a15";
  50. reg = <1>;
  51. };
  52. cpu@2 {
  53. device_type = "cpu";
  54. compatible = "arm,cortex-a15";
  55. reg = <2>;
  56. };
  57. cpu@3 {
  58. device_type = "cpu";
  59. compatible = "arm,cortex-a15";
  60. reg = <3>;
  61. };
  62. };
  63. arm-pmu {
  64. compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu";
  65. interrupts = <0 52 4>,
  66. <0 53 4>,
  67. <0 54 4>,
  68. <0 55 4>;
  69. };
  70. timer {
  71. compatible = "arm,cortex-a15-timer",
  72. "arm,armv7-timer";
  73. interrupts = <1 13 0xf08>,
  74. <1 14 0xf08>,
  75. <1 11 0xf08>,
  76. <1 10 0xf08>;
  77. clock-frequency = <50000000>;
  78. };
  79. cpufreq@160000 {
  80. compatible = "samsung,exynos5440-cpufreq";
  81. reg = <0x160000 0x1000>;
  82. interrupts = <0 57 0>;
  83. operating-points = <
  84. /* KHz uV */
  85. 1500000 1100000
  86. 1400000 1075000
  87. 1300000 1050000
  88. 1200000 1025000
  89. 1100000 1000000
  90. 1000000 975000
  91. 900000 950000
  92. 800000 925000
  93. >;
  94. };
  95. serial_0: serial@B0000 {
  96. compatible = "samsung,exynos4210-uart";
  97. reg = <0xB0000 0x1000>;
  98. interrupts = <0 2 0>;
  99. clocks = <&clock CLK_B_125>, <&clock CLK_B_125>;
  100. clock-names = "uart", "clk_uart_baud0";
  101. };
  102. serial_1: serial@C0000 {
  103. compatible = "samsung,exynos4210-uart";
  104. reg = <0xC0000 0x1000>;
  105. interrupts = <0 3 0>;
  106. clocks = <&clock CLK_B_125>, <&clock CLK_B_125>;
  107. clock-names = "uart", "clk_uart_baud0";
  108. };
  109. spi_0: spi@D0000 {
  110. compatible = "samsung,exynos5440-spi";
  111. reg = <0xD0000 0x100>;
  112. interrupts = <0 4 0>;
  113. #address-cells = <1>;
  114. #size-cells = <0>;
  115. samsung,spi-src-clk = <0>;
  116. num-cs = <1>;
  117. clocks = <&clock CLK_B_125>, <&clock CLK_SPI_BAUD>;
  118. clock-names = "spi", "spi_busclk0";
  119. };
  120. pin_ctrl: pinctrl {
  121. compatible = "samsung,exynos5440-pinctrl";
  122. reg = <0xE0000 0x1000>;
  123. interrupts = <0 37 0>, <0 38 0>, <0 39 0>, <0 40 0>,
  124. <0 41 0>, <0 42 0>, <0 43 0>, <0 44 0>;
  125. interrupt-controller;
  126. #interrupt-cells = <2>;
  127. #gpio-cells = <2>;
  128. fan: fan {
  129. samsung,exynos5440-pin-function = <1>;
  130. };
  131. hdd_led0: hdd_led0 {
  132. samsung,exynos5440-pin-function = <2>;
  133. };
  134. hdd_led1: hdd_led1 {
  135. samsung,exynos5440-pin-function = <3>;
  136. };
  137. uart1: uart1 {
  138. samsung,exynos5440-pin-function = <4>;
  139. };
  140. };
  141. i2c@F0000 {
  142. compatible = "samsung,exynos5440-i2c";
  143. reg = <0xF0000 0x1000>;
  144. interrupts = <0 5 0>;
  145. #address-cells = <1>;
  146. #size-cells = <0>;
  147. clocks = <&clock CLK_B_125>;
  148. clock-names = "i2c";
  149. };
  150. i2c@100000 {
  151. compatible = "samsung,exynos5440-i2c";
  152. reg = <0x100000 0x1000>;
  153. interrupts = <0 6 0>;
  154. #address-cells = <1>;
  155. #size-cells = <0>;
  156. clocks = <&clock CLK_B_125>;
  157. clock-names = "i2c";
  158. };
  159. watchdog@110000 {
  160. compatible = "samsung,s3c2410-wdt";
  161. reg = <0x110000 0x1000>;
  162. interrupts = <0 1 0>;
  163. clocks = <&clock CLK_B_125>;
  164. clock-names = "watchdog";
  165. };
  166. gmac: ethernet@00230000 {
  167. compatible = "snps,dwmac-3.70a";
  168. reg = <0x00230000 0x8000>;
  169. interrupt-parent = <&gic>;
  170. interrupts = <0 31 4>;
  171. interrupt-names = "macirq";
  172. phy-mode = "sgmii";
  173. clocks = <&clock CLK_GMAC0>;
  174. clock-names = "stmmaceth";
  175. };
  176. amba {
  177. #address-cells = <1>;
  178. #size-cells = <1>;
  179. compatible = "arm,amba-bus";
  180. interrupt-parent = <&gic>;
  181. ranges;
  182. };
  183. rtc {
  184. compatible = "samsung,s3c6410-rtc";
  185. reg = <0x130000 0x1000>;
  186. interrupts = <0 17 0>, <0 16 0>;
  187. clocks = <&clock CLK_B_125>;
  188. clock-names = "rtc";
  189. };
  190. tmuctrl_0: tmuctrl@160118 {
  191. compatible = "samsung,exynos5440-tmu";
  192. reg = <0x160118 0x230>, <0x160368 0x10>;
  193. interrupts = <0 58 0>;
  194. clocks = <&clock CLK_B_125>;
  195. clock-names = "tmu_apbif";
  196. #include "exynos5440-tmu-sensor-conf.dtsi"
  197. };
  198. tmuctrl_1: tmuctrl@16011C {
  199. compatible = "samsung,exynos5440-tmu";
  200. reg = <0x16011C 0x230>, <0x160368 0x10>;
  201. interrupts = <0 58 0>;
  202. clocks = <&clock CLK_B_125>;
  203. clock-names = "tmu_apbif";
  204. #include "exynos5440-tmu-sensor-conf.dtsi"
  205. };
  206. tmuctrl_2: tmuctrl@160120 {
  207. compatible = "samsung,exynos5440-tmu";
  208. reg = <0x160120 0x230>, <0x160368 0x10>;
  209. interrupts = <0 58 0>;
  210. clocks = <&clock CLK_B_125>;
  211. clock-names = "tmu_apbif";
  212. #include "exynos5440-tmu-sensor-conf.dtsi"
  213. };
  214. thermal-zones {
  215. cpu0_thermal: cpu0-thermal {
  216. thermal-sensors = <&tmuctrl_0>;
  217. #include "exynos5440-trip-points.dtsi"
  218. };
  219. cpu1_thermal: cpu1-thermal {
  220. thermal-sensors = <&tmuctrl_1>;
  221. #include "exynos5440-trip-points.dtsi"
  222. };
  223. cpu2_thermal: cpu2-thermal {
  224. thermal-sensors = <&tmuctrl_2>;
  225. #include "exynos5440-trip-points.dtsi"
  226. };
  227. };
  228. sata@210000 {
  229. compatible = "snps,exynos5440-ahci";
  230. reg = <0x210000 0x10000>;
  231. interrupts = <0 30 0>;
  232. clocks = <&clock CLK_SATA>;
  233. clock-names = "sata";
  234. };
  235. ohci@220000 {
  236. compatible = "samsung,exynos5440-ohci";
  237. reg = <0x220000 0x1000>;
  238. interrupts = <0 29 0>;
  239. clocks = <&clock CLK_USB>;
  240. clock-names = "usbhost";
  241. };
  242. ehci@221000 {
  243. compatible = "samsung,exynos5440-ehci";
  244. reg = <0x221000 0x1000>;
  245. interrupts = <0 29 0>;
  246. clocks = <&clock CLK_USB>;
  247. clock-names = "usbhost";
  248. };
  249. pcie_0: pcie@290000 {
  250. compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
  251. reg = <0x290000 0x1000
  252. 0x270000 0x1000
  253. 0x271000 0x40>;
  254. interrupts = <0 20 0>, <0 21 0>, <0 22 0>;
  255. clocks = <&clock CLK_PR0_250_O>, <&clock CLK_PB0_250_O>;
  256. clock-names = "pcie", "pcie_bus";
  257. #address-cells = <3>;
  258. #size-cells = <2>;
  259. device_type = "pci";
  260. ranges = <0x00000800 0 0x40000000 0x40000000 0 0x00001000 /* configuration space */
  261. 0x81000000 0 0 0x40001000 0 0x00010000 /* downstream I/O */
  262. 0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>; /* non-prefetchable memory */
  263. #interrupt-cells = <1>;
  264. interrupt-map-mask = <0 0 0 0>;
  265. interrupt-map = <0x0 0 &gic 53>;
  266. num-lanes = <4>;
  267. status = "disabled";
  268. };
  269. pcie_1: pcie@2a0000 {
  270. compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
  271. reg = <0x2a0000 0x1000
  272. 0x272000 0x1000
  273. 0x271040 0x40>;
  274. interrupts = <0 23 0>, <0 24 0>, <0 25 0>;
  275. clocks = <&clock CLK_PR1_250_O>, <&clock CLK_PB0_250_O>;
  276. clock-names = "pcie", "pcie_bus";
  277. #address-cells = <3>;
  278. #size-cells = <2>;
  279. device_type = "pci";
  280. ranges = <0x00000800 0 0x60000000 0x60000000 0 0x00001000 /* configuration space */
  281. 0x81000000 0 0 0x60001000 0 0x00010000 /* downstream I/O */
  282. 0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; /* non-prefetchable memory */
  283. #interrupt-cells = <1>;
  284. interrupt-map-mask = <0 0 0 0>;
  285. interrupt-map = <0x0 0 &gic 56>;
  286. num-lanes = <4>;
  287. status = "disabled";
  288. };
  289. };