/include/configs/ipek01.h

https://gitlab.com/ubuntu-omap/u-boot-omap5 · C Header · 395 lines · 227 code · 63 blank · 105 comment · 0 complexity · 849b150730715b39d8727f911ed08698 MD5 · raw file

  1. /*
  2. * (C) Copyright 2006
  3. * MicroSys GmbH
  4. *
  5. * (C) Copyright 2009
  6. * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
  7. *
  8. * See file CREDITS for list of people who contributed to this
  9. * project.
  10. *
  11. * This program is free software; you can redistribute it and/or
  12. * modify it under the terms of the GNU General Public License as
  13. * published by the Free Software Foundation; either version 2 of
  14. * the License, or (at your option) any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24. * MA 02111-1307 USA
  25. */
  26. #ifndef __CONFIG_H
  27. #define __CONFIG_H
  28. /*
  29. * High Level Configuration Options
  30. */
  31. #define CONFIG_MPC5200
  32. #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
  33. #define CONFIG_MPX5200 1 /* ... on MPX5200 board */
  34. #define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */
  35. #define CONFIG_IPEK01 /* Motherboard is ipek01 */
  36. #define CONFIG_SYS_TEXT_BASE 0xfc000000
  37. #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */
  38. #define CONFIG_MISC_INIT_R
  39. #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
  40. #ifdef CONFIG_CMD_KGDB
  41. #define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
  42. #endif
  43. /*
  44. * Serial console configuration
  45. */
  46. #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
  47. #define CONFIG_BAUDRATE 115200 /* ... at 9600 bps */
  48. #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
  49. #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
  50. /*
  51. * Video configuration for LIME GDC
  52. */
  53. #define CONFIG_VIDEO
  54. #ifdef CONFIG_VIDEO
  55. #define CONFIG_VIDEO_MB862xx
  56. #define CONFIG_VIDEO_MB862xx_ACCEL
  57. #define VIDEO_FB_16BPP_WORD_SWAP
  58. #define CONFIG_CFB_CONSOLE
  59. #define CONFIG_VIDEO_LOGO
  60. #define CONFIG_VIDEO_BMP_LOGO
  61. #define CONFIG_CONSOLE_EXTRA_INFO
  62. #define CONFIG_VGA_AS_SINGLE_DEVICE
  63. #define CONFIG_SYS_CONSOLE_IS_IN_ENV
  64. #define CONFIG_VIDEO_SW_CURSOR
  65. #define CONFIG_SPLASH_SCREEN
  66. #define CONFIG_VIDEO_BMP_GZIP
  67. #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) /* decompressed img */
  68. /* Lime clock frequency */
  69. #define CONFIG_SYS_MB862xx_CCF 0x90000 /* geo 166MHz other 133MHz */
  70. /* SDRAM parameter */
  71. #define CONFIG_SYS_MB862xx_MMR 0x41c767e3
  72. #endif
  73. /*
  74. * PCI Mapping:
  75. * 0x40000000 - 0x4fffffff - PCI Memory
  76. * 0x50000000 - 0x50ffffff - PCI IO Space
  77. */
  78. #define CONFIG_PCI 1
  79. #define CONFIG_PCI_PNP 1
  80. #define CONFIG_PCI_SCAN_SHOW 1
  81. #define CONFIG_PCI_MEM_BUS 0x40000000
  82. #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
  83. #define CONFIG_PCI_MEM_SIZE 0x10000000
  84. #define CONFIG_PCI_IO_BUS 0x50000000
  85. #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
  86. #define CONFIG_PCI_IO_SIZE 0x01000000
  87. #define CONFIG_MII 1
  88. #define CONFIG_EEPRO100 1
  89. #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
  90. /* Partitions */
  91. #define CONFIG_DOS_PARTITION
  92. /* USB */
  93. #define CONFIG_USB_OHCI_NEW
  94. #define CONFIG_SYS_OHCI_BE_CONTROLLER
  95. #define CONFIG_USB_STORAGE
  96. #define CONFIG_SYS_USB_OHCI_CPU_INIT
  97. #define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB
  98. #define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200"
  99. #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
  100. /*
  101. * Command line configuration.
  102. */
  103. #include <config_cmd_default.h>
  104. #ifdef CONFIG_VIDEO
  105. #define CONFIG_CMD_BMP /* BMP support */
  106. #endif
  107. #define CONFIG_CMD_DATE /* support for RTC, date/time...*/
  108. #define CONFIG_CMD_DHCP /* DHCP Support */
  109. #define CONFIG_CMD_FAT /* FAT support */
  110. #define CONFIG_CMD_I2C /* I2C serial bus support */
  111. #define CONFIG_CMD_IDE /* IDE harddisk support */
  112. #define CONFIG_CMD_IRQ /* irqinfo */
  113. #define CONFIG_CMD_MII /* MII support */
  114. #define CONFIG_CMD_PCI /* pciinfo */
  115. #define CONFIG_CMD_USB /* USB Support */
  116. #define CONFIG_SYS_LOWBOOT 1
  117. /*
  118. * Autobooting
  119. */
  120. #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
  121. #define CONFIG_PREBOOT "echo;" \
  122. "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
  123. "echo"
  124. #undef CONFIG_BOOTARGS
  125. #define CONFIG_EXTRA_ENV_SETTINGS \
  126. "netdev=eth0\0" \
  127. "consoledev=ttyPSC0\0" \
  128. "hostname=ipek01\0" \
  129. "nfsargs=setenv bootargs root=/dev/nfs rw " \
  130. "nfsroot=${serverip}:${rootpath}\0" \
  131. "ramargs=setenv bootargs root=/dev/ram rw\0" \
  132. "addip=setenv bootargs ${bootargs} " \
  133. "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
  134. ":${hostname}:${netdev}:off panic=1\0" \
  135. "addtty=setenv bootargs ${bootargs} " \
  136. "console=${consoledev},${baudrate}\0" \
  137. "flash_nfs=run nfsargs addip addtty;" \
  138. "bootm ${kernel_addr} - ${fdtaddr}\0" \
  139. "flash_self=run ramargs addip addtty;" \
  140. "bootm ${kernel_addr} ${ramdisk_addr} ${fdtaddr}\0" \
  141. "net_nfs=tftp 200000 ${bootfile}; tftp ${fdtaddr} ${fdtfile};" \
  142. "run nfsargs addip addtty;" \
  143. "bootm ${loadaddr} - ${fdtaddr}\0" \
  144. "rootpath=/opt/eldk/ppc_6xx\0" \
  145. "bootfile=ipek01/uImage\0" \
  146. "load=tftp 100000 ipek01/u-boot.bin\0" \
  147. "update=protect off FC000000 +60000; era FC000000 +60000; " \
  148. "cp.b 100000 FC000000 ${filesize}\0" \
  149. "upd=run load;run update\0" \
  150. "fdtaddr=800000\0" \
  151. "loadaddr=400000\0" \
  152. "fdtfile=ipek01/ipek01.dtb\0" \
  153. ""
  154. #define CONFIG_BOOTCOMMAND "run flash_self"
  155. /*
  156. * IPB Bus clocking configuration.
  157. */
  158. #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* for 133MHz */
  159. /* PCI clock must be 33, because board will not boot */
  160. #undef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* for 66MHz */
  161. /*
  162. * Open firmware flat tree support
  163. */
  164. #define CONFIG_OF_LIBFDT 1
  165. #define CONFIG_OF_BOARD_SETUP 1
  166. #define OF_CPU "PowerPC,5200@0"
  167. #define OF_SOC "soc5200@f0000000"
  168. #define OF_TBCLK (bd->bi_busfreq / 4)
  169. /*
  170. * I2C configuration
  171. */
  172. #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
  173. #define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
  174. #define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
  175. #define CONFIG_SYS_I2C_SLAVE 0x7F
  176. /*
  177. * EEPROM configuration
  178. */
  179. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
  180. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
  181. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
  182. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
  183. /*
  184. * RTC configuration
  185. */
  186. #define CONFIG_RTC_PCF8563
  187. #define CONFIG_SYS_I2C_RTC_ADDR 0x51
  188. #define CONFIG_SYS_FLASH_BASE 0xFC000000
  189. #define CONFIG_SYS_FLASH_SIZE 0x01000000
  190. #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
  191. CONFIG_SYS_MONITOR_LEN)
  192. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
  193. #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */
  194. #define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
  195. /* use CFI flash driver */
  196. #define CONFIG_FLASH_CFI_DRIVER
  197. #define CONFIG_SYS_FLASH_CFI
  198. #define CONFIG_SYS_FLASH_EMPTY_INFO
  199. #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
  200. /*
  201. * Environment settings
  202. */
  203. #define CONFIG_ENV_IS_IN_FLASH 1
  204. #define CONFIG_ENV_SIZE 0x10000
  205. #define CONFIG_ENV_SECT_SIZE 0x20000
  206. #define CONFIG_ENV_OVERWRITE 1
  207. #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
  208. #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
  209. /*
  210. * Memory map
  211. */
  212. #define CONFIG_SYS_MBAR 0xf0000000
  213. #define CONFIG_SYS_SDRAM_BASE 0x00000000
  214. #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
  215. #define CONFIG_SYS_SRAM_BASE 0xF1000000
  216. #define CONFIG_SYS_SRAM_SIZE 0x00200000
  217. #define CONFIG_SYS_LIME_BASE 0xE4000000
  218. #define CONFIG_SYS_LIME_SIZE 0x04000000
  219. #define CONFIG_SYS_FPGA_BASE 0xC0000000
  220. #define CONFIG_SYS_FPGA_SIZE 0x10000000
  221. #define CONFIG_SYS_MPEG_BASE 0xe2000000
  222. #define CONFIG_SYS_MPEG_SIZE 0x01000000
  223. #define CONFIG_SYS_CF_BASE 0xe1000000
  224. #define CONFIG_SYS_CF_SIZE 0x01000000
  225. /* Use SRAM until RAM will be available */
  226. #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
  227. /* End of used area in DPRAM */
  228. #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
  229. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
  230. GENERATED_GBL_DATA_SIZE)
  231. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  232. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
  233. #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  234. # define CONFIG_SYS_RAMBOOT 1
  235. #endif
  236. #define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
  237. #define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 128 kB for malloc() */
  238. #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  239. /*
  240. * Ethernet configuration
  241. */
  242. #define CONFIG_MPC5xxx_FEC 1
  243. #define CONFIG_MPC5xxx_FEC_MII100
  244. #define CONFIG_PHY_ADDR 0x00
  245. /*
  246. * GPIO configuration
  247. */
  248. #define CONFIG_SYS_GPS_PORT_CONFIG 0x1d556624
  249. /*
  250. * Miscellaneous configurable options
  251. */
  252. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  253. #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
  254. #ifdef CONFIG_CMD_KGDB
  255. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  256. #else
  257. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  258. #endif
  259. /* Print Buffer Size */
  260. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
  261. sizeof(CONFIG_SYS_PROMPT) + 16)
  262. /* max number of command args */
  263. #define CONFIG_SYS_MAXARGS 16
  264. /* Boot Argument Buffer Size */
  265. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  266. #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
  267. #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1...15 MB in DRAM */
  268. #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
  269. #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
  270. #define CONFIG_LOOPW
  271. /*
  272. * Various low-level settings
  273. */
  274. #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
  275. #define CONFIG_SYS_HID0_FINAL HID0_ICE
  276. #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
  277. #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
  278. #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
  279. #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
  280. #define CONFIG_SYS_CS1_START CONFIG_SYS_SRAM_BASE
  281. #define CONFIG_SYS_CS1_SIZE CONFIG_SYS_SRAM_SIZE
  282. #define CONFIG_SYS_CS3_START CONFIG_SYS_LIME_BASE
  283. #define CONFIG_SYS_CS3_SIZE CONFIG_SYS_LIME_SIZE
  284. #define CONFIG_SYS_CS6_START CONFIG_SYS_FPGA_BASE
  285. #define CONFIG_SYS_CS6_SIZE CONFIG_SYS_FPGA_SIZE
  286. #define CONFIG_SYS_CS5_START CONFIG_SYS_CF_BASE
  287. #define CONFIG_SYS_CS5_SIZE CONFIG_SYS_CF_SIZE
  288. #define CONFIG_SYS_CS7_START CONFIG_SYS_MPEG_BASE
  289. #define CONFIG_SYS_CS7_SIZE CONFIG_SYS_MPEG_SIZE
  290. #ifdef CONFIG_SYS_PCISPEED_66
  291. #define CONFIG_SYS_BOOTCS_CFG 0x0006F900
  292. #define CONFIG_SYS_CS1_CFG 0x0004FB00
  293. #define CONFIG_SYS_CS2_CFG 0x0006F900
  294. #else
  295. #define CONFIG_SYS_BOOTCS_CFG 0x0002F900
  296. #define CONFIG_SYS_CS1_CFG 0x0001FB00
  297. #define CONFIG_SYS_CS2_CFG 0x0002F90C
  298. #endif
  299. /*
  300. * Ack active, Muxed mode, AS=24 bit address, DS=32 bit data, 0
  301. * waitstates, writeswap and readswap enabled
  302. */
  303. #define CONFIG_SYS_CS3_CFG 0x00FFFB0C
  304. #define CONFIG_SYS_CS6_CFG 0x00FFFB0C
  305. #define CONFIG_SYS_CS7_CFG 0x4040751C
  306. #define CONFIG_SYS_CS_BURST 0x00000000
  307. #define CONFIG_SYS_CS_DEADCYCLE 0x33330000
  308. #define CONFIG_SYS_RESET_ADDRESS 0xff000000
  309. /*-----------------------------------------------------------------------
  310. * USB stuff
  311. *-----------------------------------------------------------------------
  312. */
  313. #define CONFIG_USB_CLOCK 0x0001BBBB
  314. #define CONFIG_USB_CONFIG 0x00005000
  315. /*-----------------------------------------------------------------------
  316. * IDE/ATA stuff Supports IDE harddisk
  317. *-----------------------------------------------------------------------
  318. */
  319. #define CONFIG_IDE_PREINIT
  320. #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
  321. #define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
  322. #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
  323. #define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
  324. /* Offset for data I/O */
  325. #define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
  326. /* Offset for normal register accesses */
  327. #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
  328. /* Offset for alternate registers */
  329. #define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
  330. /* Interval between registers */
  331. #define CONFIG_SYS_ATA_STRIDE 4
  332. #endif /* __CONFIG_H */