/include/configs/km82xx.h

https://gitlab.com/ubuntu-omap/u-boot-omap5 · C Header · 448 lines · 244 code · 75 blank · 129 comment · 7 complexity · eb7f06f7780f342218704d46a886ffce MD5 · raw file

  1. /*
  2. * (C) Copyright 2007-2011
  3. * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. #ifndef __CONFIG_H
  24. #define __CONFIG_H
  25. /*
  26. * High Level Configuration Options
  27. * (easy to change)
  28. */
  29. #define CONFIG_MPC8247
  30. /* MGCOGE */
  31. #if defined(CONFIG_MGCOGE)
  32. #define CONFIG_HOSTNAME mgcoge
  33. #define CONFIG_KM_BOARD_EXTRA_ENV ""
  34. /* MGCOGE3NE */
  35. #elif defined(CONFIG_MGCOGE3NE)
  36. #define CONFIG_HOSTNAME mgcoge3ne
  37. #define CONFIG_KM_82XX
  38. #define CONFIG_KM_BOARD_EXTRA_ENV "bobcatreset=true\0"
  39. #else
  40. #error ("Board unsupported")
  41. #endif
  42. #define CONFIG_SYS_TEXT_BASE 0xFE000000
  43. /* include common defines/options for all Keymile boards */
  44. #include "km/keymile-common.h"
  45. #include "km/km-powerpc.h"
  46. #define CONFIG_SYS_SDRAM_BASE 0x00000000
  47. #define CONFIG_SYS_FLASH_BASE 0xFE000000
  48. #define CONFIG_SYS_FLASH_SIZE 32
  49. #define CONFIG_SYS_FLASH_CFI
  50. #define CONFIG_FLASH_CFI_DRIVER
  51. /* MGCOGE */
  52. #if defined(CONFIG_MGCOGE)
  53. #define CONFIG_SYS_MAX_FLASH_BANKS 3
  54. /* max num of sects on one chip */
  55. #define CONFIG_SYS_MAX_FLASH_SECT 512
  56. #define CONFIG_SYS_FLASH_BASE_1 0x50000000
  57. #define CONFIG_SYS_FLASH_SIZE_1 32
  58. #define CONFIG_SYS_FLASH_BASE_2 0x52000000
  59. #define CONFIG_SYS_FLASH_SIZE_2 32
  60. #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \
  61. CONFIG_SYS_FLASH_BASE_1, \
  62. CONFIG_SYS_FLASH_BASE_2 }
  63. #define MTDIDS_DEFAULT "nor3=app"
  64. /*
  65. * Bank 1 - 60x bus SDRAM
  66. */
  67. #define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */
  68. #define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (256 << 20) /* less than 256 MB */
  69. /* SDRAM initialization values
  70. */
  71. #define CONFIG_SYS_OR1 ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & \
  72. ORxS_SDAM_MSK) |\
  73. ORxS_BPD_8 |\
  74. ORxS_ROWST_PBI0_A7 |\
  75. ORxS_NUMR_13)
  76. #define CONFIG_SYS_PSDMR ( \
  77. PSDMR_SDAM_A14_IS_A5 |\
  78. PSDMR_BSMA_A14_A16 |\
  79. PSDMR_SDA10_PBI0_A9 |\
  80. PSDMR_RFRC_5_CLK |\
  81. PSDMR_PRETOACT_2W |\
  82. PSDMR_ACTTORW_2W |\
  83. PSDMR_LDOTOPRE_1C |\
  84. PSDMR_WRC_1C |\
  85. PSDMR_CL_2)
  86. /* MGCOGE3NE */
  87. #elif defined(CONFIG_MGCOGE3NE)
  88. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of flash banks */
  89. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /*
  90. * max num of sects on one
  91. * chip
  92. */
  93. #define CONFIG_SYS_FLASH_BASE_1 0x50000000
  94. #define CONFIG_SYS_FLASH_SIZE_1 128
  95. #define CONFIG_SYS_FLASH_SIZE_2 0 /* dummy value to calc SYS_OR5 */
  96. #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \
  97. CONFIG_SYS_FLASH_BASE_1 }
  98. #define MTDIDS_DEFAULT "nor2=app"
  99. /*
  100. * Bank 1 - 60x bus SDRAM
  101. * mgcoge3ne has 256MB
  102. * mgcoge2ne has 128MB
  103. */
  104. #define SDRAM_MAX_SIZE 0x10000000 /* max. 256 MB */
  105. #define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (512 << 20) /* less than 512 MB */
  106. #define CONFIG_SYS_OR1 ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & \
  107. ORxS_SDAM_MSK) |\
  108. ORxS_BPD_4 |\
  109. ORxS_NUMR_13 |\
  110. ORxS_IBID)
  111. #define CONFIG_SYS_PSDMR ( \
  112. PSDMR_PBI |\
  113. PSDMR_RFEN |\
  114. PSDMR_BSMA_A13_A15 |\
  115. PSDMR_RFRC_5_CLK |\
  116. PSDMR_PRETOACT_2W |\
  117. PSDMR_ACTTORW_2W |\
  118. PSDMR_LDOTOPRE_1C |\
  119. PSDMR_WRC_1C |\
  120. PSDMR_CL_2)
  121. #define CONFIG_SYS_SDRAM_LIST { \
  122. { .size = 256 << 20, \
  123. .or1 = ORxS_ROWST_PBI1_A4, \
  124. .psdmr = PSDMR_SDAM_A17_IS_A5 | PSDMR_SDA10_PBI1_A6, \
  125. }, \
  126. { .size = 128 << 20, \
  127. .or1 = ORxS_ROWST_PBI1_A5, \
  128. .psdmr = PSDMR_SDAM_A16_IS_A5 | PSDMR_SDA10_PBI1_A7, \
  129. }, \
  130. }
  131. #endif /* defined(CONFIG_MGCOGE3NE) */
  132. /* include further common stuff for all keymile 82xx boards */
  133. /*
  134. * Select serial console configuration
  135. *
  136. * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
  137. * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
  138. * for SCC).
  139. */
  140. #define CONFIG_CONS_ON_SMC /* Console is on SMC */
  141. #undef CONFIG_CONS_ON_SCC /* It's not on SCC */
  142. #undef CONFIG_CONS_NONE /* It's not on external UART */
  143. #define CONFIG_CONS_INDEX 2 /* SMC2 is used for console */
  144. #define CONFIG_SYS_SMC_RXBUFLEN 128
  145. #define CONFIG_SYS_MAXIDLE 10
  146. /*
  147. * Select ethernet configuration
  148. *
  149. * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
  150. * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
  151. * SCC, 1-3 for FCC)
  152. *
  153. * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
  154. * must be defined elsewhere (as for the console), or CONFIG_CMD_NET
  155. * must be unset.
  156. */
  157. #define CONFIG_ETHER_ON_SCC /* Ethernet is on SCC */
  158. #undef CONFIG_ETHER_ON_FCC /* Ethernet is not on FCC */
  159. #undef CONFIG_ETHER_NONE /* No external Ethernet */
  160. #define CONFIG_ETHER_INDEX 4
  161. #define CONFIG_HAS_ETH0
  162. #define CONFIG_SYS_SCC_TOUT_LOOP 10000000
  163. #define CONFIG_SYS_CMXSCR_VALUE (CMXSCR_RS4CS_CLK7 | CMXSCR_TS4CS_CLK8)
  164. #ifndef CONFIG_8260_CLKIN
  165. #define CONFIG_8260_CLKIN 66000000 /* in Hz */
  166. #endif
  167. #define BOOTFLASH_START 0xFE000000
  168. #define CONFIG_KM_CONSOLE_TTY "ttyCPM0"
  169. #define MTDPARTS_DEFAULT "mtdparts=" \
  170. "app:" \
  171. "768k(u-boot)," \
  172. "128k(env)," \
  173. "128k(envred)," \
  174. "3072k(free)," \
  175. "-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ")"
  176. /*
  177. * Default environment settings
  178. */
  179. #define CONFIG_EXTRA_ENV_SETTINGS \
  180. CONFIG_KM_BOARD_EXTRA_ENV \
  181. CONFIG_KM_DEF_ENV \
  182. "EEprom_ivm=pca9544a:70:4 \0" \
  183. "unlock=yes\0" \
  184. "newenv=" \
  185. "prot off 0xFE0C0000 +0x40000 && " \
  186. "era 0xFE0C0000 +0x40000\0" \
  187. "arch=ppc_82xx\0" \
  188. ""
  189. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
  190. #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  191. #define CONFIG_SYS_RAMBOOT
  192. #endif
  193. #define CONFIG_SYS_MONITOR_LEN (768 << 10)
  194. #define CONFIG_ENV_IS_IN_FLASH
  195. #ifdef CONFIG_ENV_IS_IN_FLASH
  196. #define CONFIG_ENV_SECT_SIZE 0x20000
  197. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
  198. CONFIG_SYS_MONITOR_LEN)
  199. #define CONFIG_ENV_OFFSET CONFIG_SYS_MONITOR_LEN
  200. /* Address and size of Redundant Environment Sector */
  201. #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
  202. CONFIG_ENV_SECT_SIZE)
  203. #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
  204. #endif /* CONFIG_ENV_IS_IN_FLASH */
  205. /* enable I2C and select the hardware/software driver */
  206. #undef CONFIG_HARD_I2C /* I2C with hardware support */
  207. #define CONFIG_SOFT_I2C /* I2C bit-banged */
  208. #define CONFIG_SYS_I2C_SPEED 50000 /* I2C speed */
  209. #define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave address */
  210. /*
  211. * Software (bit-bang) I2C driver configuration
  212. */
  213. #define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
  214. #define I2C_ACTIVE (iop->pdir |= 0x00010000)
  215. #define I2C_TRISTATE (iop->pdir &= ~0x00010000)
  216. #define I2C_READ ((iop->pdat & 0x00010000) != 0)
  217. #define I2C_SDA(bit) do { \
  218. if (bit) \
  219. iop->pdat |= 0x00010000; \
  220. else \
  221. iop->pdat &= ~0x00010000; \
  222. } while (0)
  223. #define I2C_SCL(bit) do { \
  224. if (bit) \
  225. iop->pdat |= 0x00020000; \
  226. else \
  227. iop->pdat &= ~0x00020000; \
  228. } while (0)
  229. #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
  230. #ifndef __ASSEMBLY__
  231. void set_sda(int state);
  232. void set_scl(int state);
  233. int get_sda(void);
  234. int get_scl(void);
  235. #endif
  236. /* I2C SYSMON (LM75, AD7414 is almost compatible) */
  237. #define CONFIG_DTT_LM75 /* ON Semi's LM75 */
  238. #define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
  239. #define CONFIG_SYS_DTT_MAX_TEMP 70
  240. #define CONFIG_SYS_DTT_LOW_TEMP -30
  241. #define CONFIG_SYS_DTT_HYSTERESIS 3
  242. #define CONFIG_SYS_DTT_BUS_NUM (CONFIG_SYS_MAX_I2C_BUS)
  243. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  244. #define CONFIG_SYS_IMMR 0xF0000000
  245. #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
  246. #define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* used size in DPRAM */
  247. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
  248. GENERATED_GBL_DATA_SIZE)
  249. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  250. /* Hard reset configuration word */
  251. #define CONFIG_SYS_HRCW_MASTER 0x0604b211
  252. /* No slaves */
  253. #define CONFIG_SYS_HRCW_SLAVE1 0
  254. #define CONFIG_SYS_HRCW_SLAVE2 0
  255. #define CONFIG_SYS_HRCW_SLAVE3 0
  256. #define CONFIG_SYS_HRCW_SLAVE4 0
  257. #define CONFIG_SYS_HRCW_SLAVE5 0
  258. #define CONFIG_SYS_HRCW_SLAVE6 0
  259. #define CONFIG_SYS_HRCW_SLAVE7 0
  260. /* Initial Memory map for Linux */
  261. #define CONFIG_SYS_BOOTMAPSZ (8 << 20)
  262. #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPUs */
  263. #if defined(CONFIG_CMD_KGDB)
  264. # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
  265. #endif
  266. #define CONFIG_SYS_HID0_INIT 0
  267. #define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE)
  268. #define CONFIG_SYS_HID2 0
  269. #define CONFIG_SYS_SIUMCR 0x4020c200
  270. #define CONFIG_SYS_SYPCR 0xFFFFFF83
  271. #define CONFIG_SYS_BCR 0x10000000
  272. #define CONFIG_SYS_SCCR (SCCR_PCI_MODE | SCCR_PCI_MODCK)
  273. /*
  274. *-----------------------------------------------------------------------
  275. * RMR - Reset Mode Register 5-5
  276. *-----------------------------------------------------------------------
  277. * turn on Checkstop Reset Enable
  278. */
  279. #define CONFIG_SYS_RMR 0
  280. /*
  281. *-----------------------------------------------------------------------
  282. * TMCNTSC - Time Counter Status and Control 4-40
  283. *-----------------------------------------------------------------------
  284. * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
  285. * and enable Time Counter
  286. */
  287. #define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
  288. /*
  289. *-----------------------------------------------------------------------
  290. * PISCR - Periodic Interrupt Status and Control 4-42
  291. *-----------------------------------------------------------------------
  292. * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
  293. * Periodic timer
  294. */
  295. #define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
  296. /*
  297. *-----------------------------------------------------------------------
  298. * RCCR - RISC Controller Configuration 13-7
  299. *-----------------------------------------------------------------------
  300. */
  301. #define CONFIG_SYS_RCCR 0
  302. /*
  303. * Init Memory Controller:
  304. *
  305. * Bank Bus Machine PortSz Device
  306. * ---- --- ------- ------ ------
  307. * 0 60x GPCM 8 bit FLASH
  308. * 1 60x SDRAM 32 bit SDRAM
  309. * 3 60x GPCM 8 bit GPIO/PIGGY
  310. * 5 60x GPCM 16 bit CFG-Flash
  311. *
  312. */
  313. /* Bank 0 - FLASH
  314. */
  315. #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\
  316. BRx_PS_8 |\
  317. BRx_MS_GPCM_P |\
  318. BRx_V)
  319. #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
  320. ORxG_CSNT |\
  321. ORxG_ACS_DIV2 |\
  322. ORxG_SCY_5_CLK |\
  323. ORxG_TRLX)
  324. #define CONFIG_SYS_MPTPR 0x1800
  325. /*
  326. *-----------------------------------------------------------------------------
  327. * Address for Mode Register Set (MRS) command
  328. *-----------------------------------------------------------------------------
  329. */
  330. #define CONFIG_SYS_MRS_OFFS 0x00000110
  331. #define CONFIG_SYS_PSRT 0x0e
  332. #define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
  333. BRx_PS_64 |\
  334. BRx_MS_SDRAM_P |\
  335. BRx_V)
  336. #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR1
  337. /*
  338. * UPIO FPGA (GPIO/PIGGY) on CS3 initialization values
  339. */
  340. #define CONFIG_SYS_KMBEC_FPGA_BASE 0x30000000
  341. #define CONFIG_SYS_KMBEC_FPGA_SIZE 128
  342. #define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_KMBEC_FPGA_BASE & BRx_BA_MSK) |\
  343. BRx_PS_8 | BRx_MS_GPCM_P | BRx_V)
  344. #define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) |\
  345. ORxG_CSNT | ORxG_ACS_DIV2 |\
  346. ORxG_SCY_3_CLK | ORxG_TRLX)
  347. /*
  348. * BFTICU board FPGA on CS4 initialization values
  349. */
  350. #define CONFIG_SYS_FPGA_BASE 0x40000000
  351. #define CONFIG_SYS_FPGA_SIZE 1 /*1KB*/
  352. #define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_FPGA_BASE & BRx_BA_MSK) |\
  353. BRx_PS_8 | BRx_MS_GPCM_P | BRx_V)
  354. #define CONFIG_SYS_OR4_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FPGA_SIZE << 10) |\
  355. ORxG_CSNT | ORxG_ACS_DIV2 |\
  356. ORxG_SCY_3_CLK | ORxG_TRLX)
  357. /*
  358. * CFG-Flash on CS5 initialization values
  359. */
  360. #define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_FLASH_BASE_1 & BRx_BA_MSK) |\
  361. BRx_PS_16 | BRx_MS_GPCM_P | BRx_V)
  362. #define CONFIG_SYS_OR5_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE_1 + \
  363. CONFIG_SYS_FLASH_SIZE_2) |\
  364. ORxG_CSNT | ORxG_ACS_DIV2 |\
  365. ORxG_SCY_5_CLK | ORxG_TRLX)
  366. #define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */
  367. /* pass open firmware flat tree */
  368. #define CONFIG_FIT 1
  369. #define CONFIG_OF_LIBFDT 1
  370. #define CONFIG_OF_BOARD_SETUP 1
  371. #define OF_TBCLK (bd->bi_busfreq / 4)
  372. #define OF_STDOUT_PATH "/soc/cpm/serial@11a90"
  373. #endif /* __CONFIG_H */