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/include/configs/korat.h

https://gitlab.com/ubuntu-omap/u-boot-omap5
C Header | 567 lines | 336 code | 64 blank | 167 comment | 5 complexity | 3d692c62e5ffccce3e26281f756bb81b MD5 | raw file
  1/*
  2 * (C) Copyright 2007-2009
  3 * Larry Johnson, lrj@acm.org
  4 *
  5 * (C) Copyright 2006-2007
  6 * Stefan Roese, DENX Software Engineering, sr@denx.de.
  7 *
  8 * (C) Copyright 2006
  9 * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
 10 * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
 11 *
 12 * This program is free software; you can redistribute it and/or
 13 * modify it under the terms of the GNU General Public License as
 14 * published by the Free Software Foundation; either version 2 of
 15 * the License, or (at your option) any later version.
 16 *
 17 * This program is distributed in the hope that it will be useful,
 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 20 * GNU General Public License for more details.
 21 *
 22 * You should have received a copy of the GNU General Public License
 23 * along with this program; if not, write to the Free Software
 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 25 * MA 02111-1307 USA
 26 */
 27
 28/*
 29 * korat.h - configuration for Korat board
 30 */
 31#ifndef __CONFIG_H
 32#define __CONFIG_H
 33
 34/*
 35 * High Level Configuration Options
 36 */
 37#define CONFIG_440EPX		1	/* Specific PPC440EPx		*/
 38#define CONFIG_4xx		1	/* ... PPC4xx family		*/
 39#define CONFIG_SYS_CLK_FREQ	33333333
 40
 41#ifdef CONFIG_KORAT_PERMANENT
 42#define CONFIG_SYS_TEXT_BASE	0xFFFA0000
 43#else
 44#define	CONFIG_SYS_TEXT_BASE	0xF7F60000
 45#endif
 46
 47#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f	*/
 48#define CONFIG_MISC_INIT_R	1	/* Call misc_init_r		*/
 49
 50/*
 51 * Manufacturer's information serial EEPROM parameters
 52 */
 53#define MAN_DATA_EEPROM_ADDR	0x53	/* EEPROM I2C address		*/
 54#define MAN_INFO_FIELD		2
 55#define MAN_INFO_LENGTH		9
 56#define MAN_MAC_ADDR_FIELD	3
 57#define MAN_MAC_ADDR_LENGTH	12
 58
 59/*
 60 * Base addresses -- Note these are effective addresses where the actual
 61 * resources get mapped (not physical addresses).
 62 */
 63#define CONFIG_SYS_MONITOR_LEN		(384 * 1024) /* Reserve 384 kiB for Monitor  */
 64#define CONFIG_SYS_MALLOC_LEN		(256 * 1024) /* Reserve 256 kiB for malloc() */
 65
 66#define CONFIG_SYS_SDRAM_BASE		0x00000000	/* _must_ be 0		*/
 67#define CONFIG_SYS_FLASH0_SIZE		0x01000000
 68#define CONFIG_SYS_FLASH0_ADDR		(-CONFIG_SYS_FLASH0_SIZE)
 69#define CONFIG_SYS_FLASH1_TOP		0xF8000000
 70#define CONFIG_SYS_FLASH1_MAX_SIZE	0x08000000
 71#define CONFIG_SYS_FLASH1_ADDR		(CONFIG_SYS_FLASH1_TOP - CONFIG_SYS_FLASH1_MAX_SIZE)
 72#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_FLASH1_ADDR	/* start of FLASH	*/
 73#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
 74#define CONFIG_SYS_OCM_BASE		0xe0010000	/* ocm			*/
 75#define CONFIG_SYS_OCM_DATA_ADDR	CONFIG_SYS_OCM_BASE
 76#define CONFIG_SYS_PCI_BASE		0xe0000000	/* Internal PCI regs	*/
 77#define CONFIG_SYS_PCI_MEMBASE		0x80000000	/* mapped pci memory	*/
 78#define CONFIG_SYS_PCI_MEMBASE2		(CONFIG_SYS_PCI_MEMBASE + 0x20000000)
 79
 80#define CONFIG_SYS_USB2D0_BASE		0xe0000100
 81#define CONFIG_SYS_USB_DEVICE		0xe0000000
 82#define CONFIG_SYS_USB_HOST		0xe0000400
 83#define CONFIG_SYS_CPLD_BASE		0xc0000000
 84
 85/*
 86 * Initial RAM & stack pointer
 87 */
 88/* 440EPx has 16KB of internal SRAM, so no need for D-Cache		*/
 89#undef CONFIG_SYS_INIT_RAM_DCACHE
 90#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_BASE	/* OCM			*/
 91#define CONFIG_SYS_INIT_RAM_SIZE	(4 << 10)
 92#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 93#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
 94
 95/*
 96 * Serial Port
 97 */
 98#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
 99#define CONFIG_SYS_NS16550
100#define CONFIG_SYS_NS16550_SERIAL
101#define CONFIG_SYS_NS16550_REG_SIZE	1
102#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
103#define CONFIG_SYS_EXT_SERIAL_CLOCK	11059200	/* ext. 11.059MHz clk	*/
104#define CONFIG_BAUDRATE		115200
105
106#define CONFIG_SYS_BAUDRATE_TABLE						\
107	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
108
109/*
110 * Environment
111 */
112#define CONFIG_ENV_IS_IN_FLASH	1	/* use FLASH for environ vars	*/
113
114/*
115 * FLASH related
116 */
117#define CONFIG_SYS_FLASH_CFI			/* The flash is CFI compatible	      */
118#define CONFIG_FLASH_CFI_DRIVER		/* Use common CFI driver	      */
119#define CONFIG_FLASH_CFI_LEGACY		/* Allow hard-coded config for FLASH0 */
120
121#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH1_ADDR, CONFIG_SYS_FLASH0_ADDR }
122
123#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks	      */
124#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* max number of sectors on one chip  */
125
126#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)    */
127#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)    */
128
129#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)   */
130#define CONFIG_SYS_FLASH_PROTECTION	1	/* use hardware flash protection      */
131
132#define CONFIG_SYS_FLASH_EMPTY_INFO	      /* print 'E' for empty sector on flinfo */
133#define CONFIG_SYS_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash      */
134
135#define CONFIG_ENV_SECT_SIZE	0x20000	/* size of one complete sector	      */
136#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH1_TOP - CONFIG_ENV_SECT_SIZE)
137#define CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector   */
138
139/* Address and size of Redundant Environment Sector */
140#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
141#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
142
143/*
144 * DDR SDRAM
145 */
146#define CONFIG_DDR_DATA_EYE		/* use DDR2 optimization	*/
147#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for setup	*/
148#define CONFIG_ZERO_SDRAM		/* Zero SDRAM after setup	*/
149#define CONFIG_DDR_ECC			/* Use ECC when available	*/
150#define SPD_EEPROM_ADDRESS	{0x50}
151#define CONFIG_PROG_SDRAM_TLB
152#define CONFIG_SYS_MEM_TOP_HIDE	(4 << 10) /* don't use last 4 KiB as	*/
153					/* per 440EPx Errata CHIP_11	*/
154
155/*
156 * I2C
157 */
158#define CONFIG_HARD_I2C		1	/* I2C with hardware support	*/
159#undef	CONFIG_SOFT_I2C			/* I2C bit-banged		*/
160#define CONFIG_PPC4XX_I2C		/* use PPC4xx driver		*/
161#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address	*/
162#define CONFIG_SYS_I2C_SLAVE		0x7F
163
164#define CONFIG_SYS_I2C_MULTI_EEPROMS
165#define CONFIG_SYS_I2C_EEPROM_ADDR	(0xa8>>1)
166#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
167#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
168#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
169
170/* I2C RTC */
171#define CONFIG_RTC_M41T60	1
172#define CONFIG_SYS_I2C_RTC_ADDR	0x68
173
174/* I2C SYSMON (LM73)							*/
175#define CONFIG_DTT_LM73		1	/* National Semi's LM73		*/
176#define CONFIG_DTT_SENSORS	{2}	/* Sensor addresses		*/
177#define CONFIG_SYS_DTT_MAX_TEMP	70
178#define CONFIG_SYS_DTT_MIN_TEMP	-30
179
180#define CONFIG_PREBOOT	"echo;"						\
181	"echo Type \\\"run flash_cf\\\" to mount from CompactFlash(R);" \
182	"echo"
183
184#undef	CONFIG_BOOTARGS
185
186/* Setup some board specific values for the default environment variables */
187#define CONFIG_HOSTNAME		korat
188
189/* Note: kernel_addr and ramdisk_addr assume that FLASH1 is 64 MiB. */
190#define CONFIG_EXTRA_ENV_SETTINGS					\
191	"u_boot=korat/u-boot.bin\0"					\
192	"load=tftp 200000 ${u_boot}\0"					\
193	"update=protect off F7F60000 F7FBFFFF;erase F7F60000 F7FBFFFF;"	\
194		"cp.b ${fileaddr} F7F60000 ${filesize};protect on "	\
195		"F7F60000 F7FBFFFF\0"					\
196	"upd=run load update\0"						\
197	"bootfile=korat/uImage\0"					\
198	"dtb=korat/korat.dtb\0"						\
199	"kernel_addr=F4000000\0"					\
200	"ramdisk_addr=F4400000\0"					\
201	"dtb_addr=F41E0000\0"						\
202	"udl=tftp 200000 ${bootfile}; erase F4000000 F41DFFFF; "	\
203		"cp.b ${fileaddr} F4000000 ${filesize}\0"		\
204	"udd=tftp 200000 ${dtb}; erase F41E0000 F41FFFFF; "		\
205		"cp.b ${fileaddr} F41E0000 ${filesize}\0"		\
206	"ll=setenv kernel_addr 200000; setenv dtb_addr 1000000; "	\
207		"tftp ${kernel_addr} ${uImage}; tftp ${dtb_addr} "	\
208		"${dtb}\0"						\
209	"rd_size=73728\0"						\
210	"ramargs=setenv bootargs root=/dev/ram rw "			\
211		"ramdisk_size=${rd_size}\0"				\
212	"usbdev=sda1\0"							\
213	"usbargs=setenv bootargs root=/dev/${usbdev} ro rootdelay=10\0"	\
214	"rootpath=/opt/eldk/ppc_4xxFP\0"				\
215	"netdev=eth0\0"							\
216	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
217		"nfsroot=${serverip}:${rootpath}\0"			\
218	"pciclk=33\0"							\
219	"addide=setenv bootargs ${bootargs} ide=reverse "		\
220		"idebus=${pciclk}\0"					\
221	"addip=setenv bootargs ${bootargs} "				\
222		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
223		":${hostname}:${netdev}:off panic=1\0"			\
224	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
225	"flash_cf=run usbargs addide addip addtty; "			\
226		"bootm ${kernel_addr} - ${dtb_addr}\0"			\
227	"flash_nfs=run nfsargs addide addip addtty; "			\
228		"bootm ${kernel_addr} - ${dtb_addr}\0"			\
229	"flash_self=run ramargs addip addtty; "				\
230		"bootm ${kernel_addr} ${ramdisk_addr} ${dtb_addr}\0"	\
231	""
232
233#define CONFIG_BOOTCOMMAND	"run flash_cf"
234
235#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
236
237#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
238#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
239
240#define CONFIG_PPC4xx_EMAC
241#define CONFIG_IBM_EMAC4_V4	1
242#define CONFIG_MII		1	/* MII PHY management		*/
243#define CONFIG_PHY_ADDR		2	/* PHY address, See schematics	*/
244#define CONFIG_PHY_DYNAMIC_ANEG	1
245
246#undef CONFIG_PHY_RESET			/* Don't do software PHY reset	*/
247#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
248
249#define CONFIG_HAS_ETH0
250#define CONFIG_SYS_RX_ETH_BUFFER	32	/* Number of ethernet rx	*/
251					/*   buffers & descriptors	*/
252#define CONFIG_HAS_ETH1		1	/* add support for "eth1addr"	*/
253#define CONFIG_PHY1_ADDR	3
254
255/* USB */
256#define CONFIG_USB_OHCI
257#define CONFIG_USB_STORAGE
258
259/* Comment this out to enable USB 1.1 device */
260#define USB_2_0_DEVICE
261
262/* Partitions */
263#define CONFIG_MAC_PARTITION
264#define CONFIG_DOS_PARTITION
265#define CONFIG_ISO_PARTITION
266
267/*
268 * BOOTP options
269 */
270#define CONFIG_BOOTP_BOOTFILESIZE
271#define CONFIG_BOOTP_BOOTPATH
272#define CONFIG_BOOTP_GATEWAY
273#define CONFIG_BOOTP_HOSTNAME
274#define CONFIG_BOOTP_SUBNETMASK
275
276/*
277 * Command line configuration.
278 */
279#include <config_cmd_default.h>
280
281#define CONFIG_CMD_ASKENV
282#define CONFIG_CMD_DATE
283#define CONFIG_CMD_DHCP
284#define CONFIG_CMD_DTT
285#define CONFIG_CMD_DIAG
286#define CONFIG_CMD_EEPROM
287#define CONFIG_CMD_ELF
288#define CONFIG_CMD_FAT
289#define CONFIG_CMD_I2C
290#define CONFIG_CMD_IRQ
291#define CONFIG_CMD_MII
292#define CONFIG_CMD_NET
293#define CONFIG_CMD_NFS
294#define CONFIG_CMD_PCI
295#define CONFIG_CMD_PING
296#define CONFIG_CMD_REGINFO
297#define CONFIG_CMD_SDRAM
298#define CONFIG_CMD_USB
299
300/* POST support */
301#define CONFIG_POST		(CONFIG_SYS_POST_CACHE	| \
302				 CONFIG_SYS_POST_CPU	| \
303				 CONFIG_SYS_POST_ECC	| \
304				 CONFIG_SYS_POST_ETHER	| \
305				 CONFIG_SYS_POST_FPU	| \
306				 CONFIG_SYS_POST_I2C	| \
307				 CONFIG_SYS_POST_MEMORY	| \
308				 CONFIG_SYS_POST_RTC	| \
309				 CONFIG_SYS_POST_SPR	| \
310				 CONFIG_SYS_POST_UART)
311
312#define CONFIG_LOGBUFFER
313#define CONFIG_SYS_POST_CACHE_ADDR	0xC8000000	/* free virtual address     */
314
315#define CONFIG_SYS_CONSOLE_IS_IN_ENV	/* Otherwise it catches logbuffer as output */
316
317#define CONFIG_SUPPORT_VFAT
318
319/*
320 * Miscellaneous configurable options
321 */
322#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
323#define CONFIG_SYS_PROMPT	        "=> "	/* Monitor Command Prompt	*/
324#if defined(CONFIG_CMD_KGDB)
325#define CONFIG_SYS_CBSIZE	        1024	/* Console I/O Buffer Size	*/
326#else
327#define CONFIG_SYS_CBSIZE	        256	/* Console I/O Buffer Size	*/
328#endif
329#define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
330					/* Print Buffer Size		*/
331#define CONFIG_SYS_MAXARGS	        16	/* max number of command args	*/
332#define CONFIG_SYS_BARGSIZE	        CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size	*/
333
334#define CONFIG_SYS_MEMTEST_START	0x0400000 /* memtest works on		*/
335#define CONFIG_SYS_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM	*/
336
337#define CONFIG_SYS_LOAD_ADDR		0x100000  /* default load address	*/
338#define CONFIG_SYS_EXTBDINFO		1  /* To use extended board_into (bd_t)	*/
339
340#define CONFIG_SYS_HZ		        1000	/* decrementer freq: 1 ms ticks	*/
341
342#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
343#define CONFIG_LOOPW		1	/* enable loopw command		*/
344#define CONFIG_MX_CYCLIC	1	/* enable mdc/mwc commands	*/
345#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
346#define CONFIG_VERSION_VARIABLE 1	/* include version env variable	*/
347
348/*
349 * Korat-specific options
350 */
351#define CONFIG_SYS_KORAT_MAN_RESET_MS	10000	/* timeout for manufacturer reset */
352
353/*
354 * PCI stuff
355 */
356/* General PCI */
357#define CONFIG_PCI			/* include pci support		*/
358#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
359#define CONFIG_SYS_PCI_CACHE_LINE_SIZE	0	/* to avoid problems with PNP	*/
360#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup	*/
361#define CONFIG_SYS_PCI_TARGBASE	0x80000000	/* PCIaddr mapped to	*/
362						/*   CONFIG_SYS_PCI_MEMBASE	*/
363/* Board-specific PCI */
364#define CONFIG_SYS_PCI_TARGET_INIT
365#define CONFIG_SYS_PCI_MASTER_INIT
366#define CONFIG_SYS_PCI_BOARD_FIXUP_IRQ
367
368#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC				*/
369#define CONFIG_SYS_PCI_SUBSYS_ID       0xcafe	/* Whatever			*/
370
371/*
372 * For booting Linux, the board info and command line data have to be in the
373 * first 8 MB of memory, since this is the maximum mapped by the Linux kernel
374 * during initialization.
375 */
376#define CONFIG_SYS_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
377
378/*
379 * External Bus Controller (EBC) Setup
380 */
381
382/* Memory Bank 0 (NOR-FLASH) initialization				*/
383#if CONFIG_SYS_FLASH0_SIZE == 0x01000000
384#define CONFIG_SYS_EBC_PB0AP		0x04017300
385#define CONFIG_SYS_EBC_PB0CR		(CONFIG_SYS_FLASH0_ADDR | 0x0009A000)
386#elif CONFIG_SYS_FLASH0_SIZE == 0x04000000
387#define CONFIG_SYS_EBC_PB0AP		0x04017300
388#define CONFIG_SYS_EBC_PB0CR		(CONFIG_SYS_FLASH0_ADDR | 0x000DA000)
389#else
390#error Unable to configure chip select for current CONFIG_SYS_FLASH0_SIZE
391#endif
392
393/* Memory Bank 1 (NOR-FLASH) initialization				*/
394#if CONFIG_SYS_FLASH1_MAX_SIZE == 0x08000000
395#define CONFIG_SYS_EBC_PB1AP		0x04017300
396#define CONFIG_SYS_EBC_PB1CR		(CONFIG_SYS_FLASH1_ADDR | 0x000FA000)
397#else
398#error Unable to configure chip select for current CONFIG_SYS_FLASH1_MAX_SIZE
399#endif
400
401/* Memory Bank 2 (CPLD) initialization					*/
402#define CONFIG_SYS_EBC_PB2AP		0x04017300
403#define CONFIG_SYS_EBC_PB2CR		(CONFIG_SYS_CPLD_BASE | 0x00038000)
404
405/*
406 * GPIO Setup
407 *
408 * Korat GPIO usage:
409 *
410 *                   Init.
411 * Pin    Source I/O value Function
412 * ------ ------ --- ----- ---------------------------------
413 * GPIO00  Alt1  I/O   x   PerAddr07
414 * GPIO01  Alt1  I/O   x   PerAddr06
415 * GPIO02  Alt1  I/O   x   PerAddr05
416 * GPIO03  GPIO   x    x   GPIO03 to expansion bus connector
417 * GPIO04  GPIO   x    x   GPIO04 to expansion bus connector
418 * GPIO05  GPIO   x    x   GPIO05 to expansion bus connector
419 * GPIO06  Alt1   O    x   PerCS1 (2nd NOR flash)
420 * GPIO07  Alt1   O    x   PerCS2 (CPLD)
421 * GPIO08  Alt1   O    x   PerCS3 to expansion bus connector
422 * GPIO09  Alt1   O    x   PerCS4 to expansion bus connector
423 * GPIO10  Alt1   O    x   PerCS5 to expansion bus connector
424 * GPIO11  Alt1   I    x   PerErr
425 * GPIO12  GPIO   O    0   ATMega !Reset
426 * GPIO13  GPIO   x    x   Test Point 2 (TP2)
427 * GPIO14  GPIO   O    1   Write protect EEPROM #1 (0xA8)
428 * GPIO15  GPIO   O    0   CPU Run LED !On
429 * GPIO16  Alt1   O    x   GMC1TxD0
430 * GPIO17  Alt1   O    x   GMC1TxD1
431 * GPIO18  Alt1   O    x   GMC1TxD2
432 * GPIO19  Alt1   O    x   GMC1TxD3
433 * GPIO20  Alt1   I    x   RejectPkt0
434 * GPIO21  Alt1   I    x   RejectPkt1
435 * GPIO22  GPIO   I    x   PGOOD_DDR
436 * GPIO23  Alt1   O    x   SCPD0
437 * GPIO24  Alt1   O    x   GMC0TxD2
438 * GPIO25  Alt1   O    x   GMC0TxD3
439 * GPIO26  GPIO? I/O   x   IIC0SDA (selected in SDR0_PFC4)
440 * GPIO27  GPIO   O    0   PHY #0 1000BASE-X select
441 * GPIO28  GPIO   O    0   PHY #1 1000BASE-X select
442 * GPIO29  GPIO   I    x   Test jumper !Present
443 * GPIO30  GPIO   I    x   SFP module #0 !Present
444 * GPIO31  GPIO   I    x   SFP module #1 !Present
445 *
446 * GPIO32  GPIO   O    1   SFP module #0 Tx !Enable
447 * GPIO33  GPIO   O    1   SFP module #1 Tx !Enable
448 * GPIO34  Alt2   I    x   !UART1_CTS
449 * GPIO35  Alt2   O    x   !UART1_RTS
450 * GPIO36  Alt1   I    x   !UART0_CTS
451 * GPIO37  Alt1   O    x   !UART0_RTS
452 * GPIO38  Alt2   O    x   UART1_Tx
453 * GPIO39  Alt2   I    x   UART1_Rx
454 * GPIO40  Alt1   I    x   IRQ0 (Ethernet 0)
455 * GPIO41  Alt1   I    x   IRQ1 (Ethernet 1)
456 * GPIO42  Alt1   I    x   IRQ2 (PCI interrupt)
457 * GPIO43  Alt1   I    x   IRQ3 (System Alert from CPLD)
458 * GPIO44  xxxx   x    x   (grounded through pulldown)
459 * GPIO45  GPIO   O    0   PHY #0 Enable
460 * GPIO46  GPIO   O    0   PHY #1 Enable
461 * GPIO47  GPIO   I    x   Reset switch !Pressed
462 * GPIO48  GPIO   I    x   Shutdown switch !Pressed
463 * GPIO49  xxxx   x    x   (reserved for trace port)
464 *   .      .     .    .               .
465 *   .      .     .    .               .
466 *   .      .     .    .               .
467 * GPIO63  xxxx   x    x   (reserved for trace port)
468 */
469
470#define CONFIG_SYS_GPIO_ATMEGA_RESET_	12
471#define CONFIG_SYS_GPIO_ATMEGA_SS_	13
472#define CONFIG_SYS_GPIO_PHY0_FIBER_SEL	27
473#define CONFIG_SYS_GPIO_PHY1_FIBER_SEL	28
474#define CONFIG_SYS_GPIO_SFP0_PRESENT_	30
475#define CONFIG_SYS_GPIO_SFP1_PRESENT_	31
476#define CONFIG_SYS_GPIO_SFP0_TX_EN_	32
477#define CONFIG_SYS_GPIO_SFP1_TX_EN_	33
478#define CONFIG_SYS_GPIO_PHY0_EN	45
479#define CONFIG_SYS_GPIO_PHY1_EN	46
480#define CONFIG_SYS_GPIO_RESET_PRESSED_	47
481
482/*
483 * PPC440 GPIO Configuration
484 */
485#define CONFIG_SYS_4xx_GPIO_TABLE { /*	  Out		  GPIO	Alternate1	Alternate2	Alternate3 */ \
486{											\
487/* GPIO Core 0 */									\
488{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0	EBC_ADDR(7)	DMA_REQ(2)	*/	\
489{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1	EBC_ADDR(6)	DMA_ACK(2)	*/	\
490{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO2	EBC_ADDR(5)	DMA_EOT/TC(2)	*/	\
491{GPIO0_BASE, GPIO_DIS, GPIO_SEL , GPIO_OUT_0}, /* GPIO3	EBC_ADDR(4)	DMA_REQ(3)	*/	\
492{GPIO0_BASE, GPIO_DIS, GPIO_SEL , GPIO_OUT_0}, /* GPIO4	EBC_ADDR(3)	DMA_ACK(3)	*/	\
493{GPIO0_BASE, GPIO_DIS, GPIO_SEL , GPIO_OUT_0}, /* GPIO5	EBC_ADDR(2)	DMA_EOT/TC(3)	*/	\
494{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6	EBC_CS_N(1)			*/	\
495{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7	EBC_CS_N(2)			*/	\
496{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8	EBC_CS_N(3)			*/	\
497{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9	EBC_CS_N(4)			*/	\
498{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5)			*/	\
499{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR			*/	\
500{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO12				*/	\
501{GPIO0_BASE, GPIO_DIS, GPIO_SEL , GPIO_OUT_0}, /* GPIO13				*/	\
502{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO14				*/	\
503{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO15				*/	\
504{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO16 GMCTxD(4)			*/	\
505{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO17 GMCTxD(5)			*/	\
506{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO18 GMCTxD(6)			*/	\
507{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO19 GMCTxD(7)			*/	\
508{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 RejectPkt0			*/	\
509{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 RejectPkt1			*/	\
510{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO22				*/	\
511{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 SCPD0				*/	\
512{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO24 GMCTxD(2)			*/	\
513{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO25 GMCTxD(3)			*/	\
514{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26				*/	\
515{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ	USB2D_RXERROR	*/	\
516{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO28		USB2D_TXVALID	*/	\
517{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO29 EBC_EXT_HDLA	USB2D_PAD_SUSPNDM */	\
518{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO30 EBC_EXT_ACK	USB2D_XCVRSELECT*/	\
519{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO31 EBC_EXR_BUSREQ	USB2D_TERMSELECT*/	\
520},											\
521{											\
522/* GPIO Core 1 */									\
523{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 USB2D_OPMODE0	EBC_DATA(2)	*/	\
524{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 USB2D_OPMODE1	EBC_DATA(3)	*/	\
525{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO34 UART0_DCD_N	UART1_DSR_CTS_N	UART2_SOUT*/ \
526{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
527{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N EBC_DATA(0)	UART3_SIN*/ \
528{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO37 UART0_RTS_N	EBC_DATA(1)	UART3_SOUT*/ \
529{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N	UART1_SOUT	*/	\
530{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N	UART1_SIN	*/	\
531{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0)			*/	\
532{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1)			*/	\
533{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2)			*/	\
534{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3)			*/	\
535{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4)	DMA_ACK(1)	*/	\
536{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6)	DMA_EOT/TC(1)	*/	\
537{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7)	DMA_REQ(0)	*/	\
538{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8)	DMA_ACK(0)	*/	\
539{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9)	DMA_EOT/TC(0)	*/	\
540{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49  Unselect via TraceSelect Bit	*/	\
541{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50  Unselect via TraceSelect Bit	*/	\
542{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51  Unselect via TraceSelect Bit	*/	\
543{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52  Unselect via TraceSelect Bit	*/	\
544{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53  Unselect via TraceSelect Bit	*/	\
545{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54  Unselect via TraceSelect Bit	*/	\
546{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55  Unselect via TraceSelect Bit	*/	\
547{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56  Unselect via TraceSelect Bit	*/	\
548{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57  Unselect via TraceSelect Bit	*/	\
549{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58  Unselect via TraceSelect Bit	*/	\
550{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59  Unselect via TraceSelect Bit	*/	\
551{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60  Unselect via TraceSelect Bit	*/	\
552{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61  Unselect via TraceSelect Bit	*/	\
553{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62  Unselect via TraceSelect Bit	*/	\
554{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63  Unselect via TraceSelect Bit	*/	\
555}											\
556}
557
558#if defined(CONFIG_CMD_KGDB)
559#define CONFIG_KGDB_BAUDRATE	230400 /* speed to run kgdb serial port	*/
560#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use	*/
561#endif
562
563/* Pass open firmware flat tree */
564#define CONFIG_OF_LIBFDT	1
565#define CONFIG_OF_BOARD_SETUP	1
566
567#endif /* __CONFIG_H */