/include/configs/lubbock.h

https://gitlab.com/ubuntu-omap/u-boot-omap5 · C Header · 254 lines · 139 code · 41 blank · 74 comment · 0 complexity · b40c2e175e3ac52c528feab7fb65f82f MD5 · raw file 

    

  1. /*
    2. 

  2.  * (C) Copyright 2002
    3. 

  3.  * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
    4. 

  4.  *
    5. 

  5.  * (C) Copyright 2002
    6. 

  6.  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
    7. 

  7.  * Marius Groeger <mgroeger@sysgo.de>
    8. 

  8.  *
    9. 

  9.  * Configuation settings for the LUBBOCK board.
    10. 

  10.  *
    11. 

  11.  * See file CREDITS for list of people who contributed to this
    12. 

  12.  * project.
    13. 

  13.  *
    14. 

  14.  * This program is free software; you can redistribute it and/or
    15. 

  15.  * modify it under the terms of the GNU General Public License as
    16. 

  16.  * published by the Free Software Foundation; either version 2 of
    17. 

  17.  * the License, or (at your option) any later version.
    18. 

  18.  *
    19. 

  19.  * This program is distributed in the hope that it will be useful,
    20. 

  20.  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    21. 

  21.  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
    22. 

  22.  * GNU General Public License for more details.
    23. 

  23.  *
    24. 

  24.  * You should have received a copy of the GNU General Public License
    25. 

  25.  * along with this program; if not, write to the Free Software
    26. 

  26.  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
    27. 

  27.  * MA 02111-1307 USA
    28. 

  28.  */
    29. 

  29. 

  30. #ifndef __CONFIG_H
    31. 

  31. #define __CONFIG_H
    32. 

  32. 

  33. /*
    34. 

  34.  * High Level Configuration Options
    35. 

  35.  * (easy to change)
    36. 

  36.  */
    37. 

  37. #define CONFIG_CPU_PXA25X		1	/* This is an PXA250 CPU    */
    38. 

  38. #define CONFIG_LUBBOCK		1	/* on an LUBBOCK Board	    */
    39. 

  39. #define CONFIG_LCD		1
    40. 

  40. #ifdef CONFIG_LCD
    41. 

  41. #define CONFIG_SHARP_LM8V31
    42. 

  42. #endif
    43. 

  43. #define CONFIG_MMC
    44. 

  44. #define CONFIG_BOARD_LATE_INIT
    45. 

  45. #define CONFIG_DOS_PARTITION
    46. 

  46. #define	CONFIG_SYS_TEXT_BASE	0x0
    47. 

  47. 

  48. /* we will never enable dcache, because we have to setup MMU first */
    49. 

  49. #define CONFIG_SYS_DCACHE_OFF
    50. 

  50. 

  51. /*
    52. 

  52.  * Size of malloc() pool
    53. 

  53.  */
    54. 

  54. #define CONFIG_SYS_MALLOC_LEN	    (CONFIG_ENV_SIZE + 128*1024)
    55. 

  55. 

  56. /*
    57. 

  57.  * Hardware drivers
    58. 

  58.  */
    59. 

  59. #define CONFIG_LAN91C96
    60. 

  60. #define CONFIG_LAN91C96_BASE 0x0C000000
    61. 

  61. 

  62. /*
    63. 

  63.  * select serial console configuration
    64. 

  64.  */
    65. 

  65. #define CONFIG_PXA_SERIAL
    66. 

  66. #define CONFIG_FFUART	       1       /* we use FFUART on LUBBOCK */
    67. 

  67. #define CONFIG_CONS_INDEX	3
    68. 

  68. 

  69. /* allow to overwrite serial and ethaddr */
    70. 

  70. #define CONFIG_ENV_OVERWRITE
    71. 

  71. 

  72. #define CONFIG_BAUDRATE		115200
    73. 

  73. 

  74. 

  75. /*
    76. 

  76.  * BOOTP options
    77. 

  77.  */
    78. 

  78. #define CONFIG_BOOTP_BOOTFILESIZE
    79. 

  79. #define CONFIG_BOOTP_BOOTPATH
    80. 

  80. #define CONFIG_BOOTP_GATEWAY
    81. 

  81. #define CONFIG_BOOTP_HOSTNAME
    82. 

  82. 

  83. 

  84. /*
    85. 

  85.  * Command line configuration.
    86. 

  86.  */
    87. 

  87. #include <config_cmd_default.h>
    88. 

  88. 

  89. #define CONFIG_CMD_FAT
    90. 

  90. 

  91. 

  92. #define CONFIG_BOOTDELAY	3
    93. 

  93. #define CONFIG_ETHADDR		08:00:3e:26:0a:5b
    94. 

  94. #define CONFIG_NETMASK		255.255.0.0
    95. 

  95. #define CONFIG_IPADDR		192.168.0.21
    96. 

  96. #define CONFIG_SERVERIP		192.168.0.250
    97. 

  97. #define CONFIG_BOOTCOMMAND	"bootm 80000"
    98. 

  98. #define CONFIG_BOOTARGS		"root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200"
    99. 

  99. #define CONFIG_CMDLINE_TAG
    100. 

  100. #define CONFIG_TIMESTAMP
    101. 

  101. 

  102. #if defined(CONFIG_CMD_KGDB)
    103. 

  103. #define CONFIG_KGDB_BAUDRATE	230400		/* speed to run kgdb serial port */
    104. 

  104. #define CONFIG_KGDB_SER_INDEX	2		/* which serial port to use */
    105. 

  105. #endif
    106. 

  106. 

  107. /*
    108. 

  108.  * Miscellaneous configurable options
    109. 

  109.  */
    110. 

  110. #define CONFIG_SYS_HUSH_PARSER		1
    111. 

  111. 

  112. #define CONFIG_SYS_LONGHELP				/* undef to save memory		*/
    113. 

  113. #ifdef CONFIG_SYS_HUSH_PARSER
    114. 

  114. #define CONFIG_SYS_PROMPT		"$ "		/* Monitor Command Prompt */
    115. 

  115. #else
    116. 

  116. #define CONFIG_SYS_PROMPT		"=> "		/* Monitor Command Prompt */
    117. 

  117. #endif
    118. 

  118. #define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
    119. 

  119. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
    120. 

  120. #define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
    121. 

  121. #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
    122. 

  122. #define CONFIG_SYS_DEVICE_NULLDEV	1
    123. 

  123. 

  124. #define CONFIG_SYS_MEMTEST_START	0xa0400000	/* memtest works on	*/
    125. 

  125. #define CONFIG_SYS_MEMTEST_END		0xa0800000	/* 4 ... 8 MB in DRAM	*/
    126. 

  126. 

  127. #define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_DRAM_BASE + 0x8000) /* default load address */
    128. 

  128. 

  129. #define CONFIG_SYS_HZ			1000
    130. 

  130. #define CONFIG_SYS_CPUSPEED		0x161		/* set core clock to 400/200/100 MHz */
    131. 

  131. 

  132. #ifdef CONFIG_MMC
    133. 

  133. #define	CONFIG_GENERIC_MMC
    134. 

  134. #define	CONFIG_PXA_MMC_GENERIC
    135. 

  135. #define CONFIG_CMD_MMC
    136. 

  136. #define CONFIG_SYS_MMC_BASE		0xF0000000
    137. 

  137. #endif
    138. 

  138. 

  139. /*
    140. 

  140.  * Physical Memory Map
    141. 

  141.  */
    142. 

  142. #define CONFIG_NR_DRAM_BANKS	4	   /* we have 2 banks of DRAM */
    143. 

  143. #define PHYS_SDRAM_1		0xa0000000 /* SDRAM Bank #1 */
    144. 

  144. #define PHYS_SDRAM_1_SIZE	0x04000000 /* 64 MB */
    145. 

  145. #define PHYS_SDRAM_2		0xa4000000 /* SDRAM Bank #2 */
    146. 

  146. #define PHYS_SDRAM_2_SIZE	0x00000000 /* 0 MB */
    147. 

  147. #define PHYS_SDRAM_3		0xa8000000 /* SDRAM Bank #3 */
    148. 

  148. #define PHYS_SDRAM_3_SIZE	0x00000000 /* 0 MB */
    149. 

  149. #define PHYS_SDRAM_4		0xac000000 /* SDRAM Bank #4 */
    150. 

  150. #define PHYS_SDRAM_4_SIZE	0x00000000 /* 0 MB */
    151. 

  151. 

  152. #define PHYS_FLASH_1		0x00000000 /* Flash Bank #1 */
    153. 

  153. #define PHYS_FLASH_2		0x04000000 /* Flash Bank #2 */
    154. 

  154. #define PHYS_FLASH_SIZE		0x02000000 /* 32 MB */
    155. 

  155. #define PHYS_FLASH_BANK_SIZE	0x02000000 /* 32 MB Banks */
    156. 

  156. #define PHYS_FLASH_SECT_SIZE	0x00040000 /* 256 KB sectors (x2) */
    157. 

  157. 

  158. #define CONFIG_SYS_DRAM_BASE		0xa0000000
    159. 

  159. #define CONFIG_SYS_DRAM_SIZE		0x04000000
    160. 

  160. 

  161. #define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
    162. 

  162. 

  163. #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
    164. 

  164. #define	CONFIG_SYS_INIT_SP_ADDR		0xfffff800
    165. 

  165. 

  166. #define FPGA_REGS_BASE_PHYSICAL 0x08000000
    167. 

  167. 

  168. /*
    169. 

  169.  * GPIO settings
    170. 

  170.  */
    171. 

  171. #define CONFIG_SYS_GPSR0_VAL		0x00008000
    172. 

  172. #define CONFIG_SYS_GPSR1_VAL		0x00FC0382
    173. 

  173. #define CONFIG_SYS_GPSR2_VAL		0x0001FFFF
    174. 

  174. #define CONFIG_SYS_GPCR0_VAL		0x00000000
    175. 

  175. #define CONFIG_SYS_GPCR1_VAL		0x00000000
    176. 

  176. #define CONFIG_SYS_GPCR2_VAL		0x00000000
    177. 

  177. #define CONFIG_SYS_GPDR0_VAL		0x0060A800
    178. 

  178. #define CONFIG_SYS_GPDR1_VAL		0x00FF0382
    179. 

  179. #define CONFIG_SYS_GPDR2_VAL		0x0001C000
    180. 

  180. #define CONFIG_SYS_GAFR0_L_VAL		0x98400000
    181. 

  181. #define CONFIG_SYS_GAFR0_U_VAL		0x00002950
    182. 

  182. #define CONFIG_SYS_GAFR1_L_VAL		0x000A9558
    183. 

  183. #define CONFIG_SYS_GAFR1_U_VAL		0x0005AAAA
    184. 

  184. #define CONFIG_SYS_GAFR2_L_VAL		0xA0000000
    185. 

  185. #define CONFIG_SYS_GAFR2_U_VAL		0x00000002
    186. 

  186. 

  187. #define CONFIG_SYS_PSSR_VAL		0x20
    188. 

  188. 

  189. #define	CONFIG_SYS_CCCR			CCCR_L27|CCCR_M2|CCCR_N10
    190. 

  190. #define	CONFIG_SYS_CKEN			0x0
    191. 

  191. 

  192. /*
    193. 

  193.  * Memory settings
    194. 

  194.  */
    195. 

  195. #define CONFIG_SYS_MSC0_VAL		0x23F223F2
    196. 

  196. #define CONFIG_SYS_MSC1_VAL		0x3FF1A441
    197. 

  197. #define CONFIG_SYS_MSC2_VAL		0x7FF97FF1
    198. 

  198. #define CONFIG_SYS_MDCNFG_VAL		0x00001AC9
    199. 

  199. #define CONFIG_SYS_MDREFR_VAL		0x00018018
    200. 

  200. #define CONFIG_SYS_MDMRS_VAL		0x00000000
    201. 

  201. 

  202. #define	CONFIG_SYS_FLYCNFG_VAL		0x00000000
    203. 

  203. #define	CONFIG_SYS_SXCNFG_VAL		0x00000000
    204. 

  204. 

  205. /*
    206. 

  206.  * PCMCIA and CF Interfaces
    207. 

  207.  */
    208. 

  208. #define CONFIG_SYS_MECR_VAL		0x00000000
    209. 

  209. #define CONFIG_SYS_MCMEM0_VAL		0x00010504
    210. 

  210. #define CONFIG_SYS_MCMEM1_VAL		0x00010504
    211. 

  211. #define CONFIG_SYS_MCATT0_VAL		0x00010504
    212. 

  212. #define CONFIG_SYS_MCATT1_VAL		0x00010504
    213. 

  213. #define CONFIG_SYS_MCIO0_VAL		0x00004715
    214. 

  214. #define CONFIG_SYS_MCIO1_VAL		0x00004715
    215. 

  215. 

  216. #define _LED			0x08000010
    217. 

  217. #define LED_BLANK		0x08000040
    218. 

  218. 

  219. /*
    220. 

  220.  * FLASH and environment organization
    221. 

  221.  */
    222. 

  222. #define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
    223. 

  223. #define CONFIG_SYS_MAX_FLASH_SECT	128  /* max number of sectors on one chip    */
    224. 

  224. 

  225. /* timeout values are in ticks */
    226. 

  226. #define CONFIG_SYS_FLASH_ERASE_TOUT	(25*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
    227. 

  227. #define CONFIG_SYS_FLASH_WRITE_TOUT	(25*CONFIG_SYS_HZ) /* Timeout for Flash Write */
    228. 

  228. 

  229. /* NOTE: many default partitioning schemes assume the kernel starts at the
    230. 

  230.  * second sector, not an environment.  You have been warned!
    231. 

  231.  */
    232. 

  232. #define	CONFIG_SYS_MONITOR_LEN		PHYS_FLASH_SECT_SIZE
    233. 

  233. #define CONFIG_ENV_IS_IN_FLASH	1
    234. 

  234. #define CONFIG_ENV_ADDR		(PHYS_FLASH_1 + PHYS_FLASH_SECT_SIZE)
    235. 

  235. #define CONFIG_ENV_SECT_SIZE	PHYS_FLASH_SECT_SIZE
    236. 

  236. #define CONFIG_ENV_SIZE		(PHYS_FLASH_SECT_SIZE / 16)
    237. 

  237. 

  238. 

  239. /*
    240. 

  240.  * FPGA Offsets
    241. 

  241.  */
    242. 

  242. #define WHOAMI_OFFSET		0x00
    243. 

  243. #define HEXLED_OFFSET		0x10
    244. 

  244. #define BLANKLED_OFFSET		0x40
    245. 

  245. #define DISCRETELED_OFFSET	0x40
    246. 

  246. #define CNFG_SWITCHES_OFFSET	0x50
    247. 

  247. #define USER_SWITCHES_OFFSET	0x60
    248. 

  248. #define MISC_WR_OFFSET		0x80
    249. 

  249. #define MISC_RD_OFFSET		0x90
    250. 

  250. #define INT_MASK_OFFSET		0xC0
    251. 

  251. #define INT_CLEAR_OFFSET	0xD0
    252. 

  252. #define GP_OFFSET		0x100
    253. 

  253. 

  254. #endif	/* __CONFIG_H */
    255.