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/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

https://gitlab.com/sunny256/linux
C | 5337 lines | 4318 code | 571 blank | 448 comment | 469 complexity | dc27c900df68462b7f5d7e405e2ffaf8 MD5 | raw file

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   1/*
   2 * Copyright 2014 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 */
  23#include <linux/firmware.h>
  24#include <drm/drmP.h>
  25#include "amdgpu.h"
  26#include "amdgpu_ih.h"
  27#include "amdgpu_gfx.h"
  28#include "cikd.h"
  29#include "cik.h"
  30#include "cik_structs.h"
  31#include "atom.h"
  32#include "amdgpu_ucode.h"
  33#include "clearstate_ci.h"
  34
  35#include "dce/dce_8_0_d.h"
  36#include "dce/dce_8_0_sh_mask.h"
  37
  38#include "bif/bif_4_1_d.h"
  39#include "bif/bif_4_1_sh_mask.h"
  40
  41#include "gca/gfx_7_0_d.h"
  42#include "gca/gfx_7_2_enum.h"
  43#include "gca/gfx_7_2_sh_mask.h"
  44
  45#include "gmc/gmc_7_0_d.h"
  46#include "gmc/gmc_7_0_sh_mask.h"
  47
  48#include "oss/oss_2_0_d.h"
  49#include "oss/oss_2_0_sh_mask.h"
  50
  51#define GFX7_NUM_GFX_RINGS     1
  52#define GFX7_MEC_HPD_SIZE      2048
  53
  54static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev);
  55static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev);
  56static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev);
  57
  58MODULE_FIRMWARE("radeon/bonaire_pfp.bin");
  59MODULE_FIRMWARE("radeon/bonaire_me.bin");
  60MODULE_FIRMWARE("radeon/bonaire_ce.bin");
  61MODULE_FIRMWARE("radeon/bonaire_rlc.bin");
  62MODULE_FIRMWARE("radeon/bonaire_mec.bin");
  63
  64MODULE_FIRMWARE("radeon/hawaii_pfp.bin");
  65MODULE_FIRMWARE("radeon/hawaii_me.bin");
  66MODULE_FIRMWARE("radeon/hawaii_ce.bin");
  67MODULE_FIRMWARE("radeon/hawaii_rlc.bin");
  68MODULE_FIRMWARE("radeon/hawaii_mec.bin");
  69
  70MODULE_FIRMWARE("radeon/kaveri_pfp.bin");
  71MODULE_FIRMWARE("radeon/kaveri_me.bin");
  72MODULE_FIRMWARE("radeon/kaveri_ce.bin");
  73MODULE_FIRMWARE("radeon/kaveri_rlc.bin");
  74MODULE_FIRMWARE("radeon/kaveri_mec.bin");
  75MODULE_FIRMWARE("radeon/kaveri_mec2.bin");
  76
  77MODULE_FIRMWARE("radeon/kabini_pfp.bin");
  78MODULE_FIRMWARE("radeon/kabini_me.bin");
  79MODULE_FIRMWARE("radeon/kabini_ce.bin");
  80MODULE_FIRMWARE("radeon/kabini_rlc.bin");
  81MODULE_FIRMWARE("radeon/kabini_mec.bin");
  82
  83MODULE_FIRMWARE("radeon/mullins_pfp.bin");
  84MODULE_FIRMWARE("radeon/mullins_me.bin");
  85MODULE_FIRMWARE("radeon/mullins_ce.bin");
  86MODULE_FIRMWARE("radeon/mullins_rlc.bin");
  87MODULE_FIRMWARE("radeon/mullins_mec.bin");
  88
  89static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
  90{
  91	{mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},
  92	{mmGDS_VMID1_BASE, mmGDS_VMID1_SIZE, mmGDS_GWS_VMID1, mmGDS_OA_VMID1},
  93	{mmGDS_VMID2_BASE, mmGDS_VMID2_SIZE, mmGDS_GWS_VMID2, mmGDS_OA_VMID2},
  94	{mmGDS_VMID3_BASE, mmGDS_VMID3_SIZE, mmGDS_GWS_VMID3, mmGDS_OA_VMID3},
  95	{mmGDS_VMID4_BASE, mmGDS_VMID4_SIZE, mmGDS_GWS_VMID4, mmGDS_OA_VMID4},
  96	{mmGDS_VMID5_BASE, mmGDS_VMID5_SIZE, mmGDS_GWS_VMID5, mmGDS_OA_VMID5},
  97	{mmGDS_VMID6_BASE, mmGDS_VMID6_SIZE, mmGDS_GWS_VMID6, mmGDS_OA_VMID6},
  98	{mmGDS_VMID7_BASE, mmGDS_VMID7_SIZE, mmGDS_GWS_VMID7, mmGDS_OA_VMID7},
  99	{mmGDS_VMID8_BASE, mmGDS_VMID8_SIZE, mmGDS_GWS_VMID8, mmGDS_OA_VMID8},
 100	{mmGDS_VMID9_BASE, mmGDS_VMID9_SIZE, mmGDS_GWS_VMID9, mmGDS_OA_VMID9},
 101	{mmGDS_VMID10_BASE, mmGDS_VMID10_SIZE, mmGDS_GWS_VMID10, mmGDS_OA_VMID10},
 102	{mmGDS_VMID11_BASE, mmGDS_VMID11_SIZE, mmGDS_GWS_VMID11, mmGDS_OA_VMID11},
 103	{mmGDS_VMID12_BASE, mmGDS_VMID12_SIZE, mmGDS_GWS_VMID12, mmGDS_OA_VMID12},
 104	{mmGDS_VMID13_BASE, mmGDS_VMID13_SIZE, mmGDS_GWS_VMID13, mmGDS_OA_VMID13},
 105	{mmGDS_VMID14_BASE, mmGDS_VMID14_SIZE, mmGDS_GWS_VMID14, mmGDS_OA_VMID14},
 106	{mmGDS_VMID15_BASE, mmGDS_VMID15_SIZE, mmGDS_GWS_VMID15, mmGDS_OA_VMID15}
 107};
 108
 109static const u32 spectre_rlc_save_restore_register_list[] =
 110{
 111	(0x0e00 << 16) | (0xc12c >> 2),
 112	0x00000000,
 113	(0x0e00 << 16) | (0xc140 >> 2),
 114	0x00000000,
 115	(0x0e00 << 16) | (0xc150 >> 2),
 116	0x00000000,
 117	(0x0e00 << 16) | (0xc15c >> 2),
 118	0x00000000,
 119	(0x0e00 << 16) | (0xc168 >> 2),
 120	0x00000000,
 121	(0x0e00 << 16) | (0xc170 >> 2),
 122	0x00000000,
 123	(0x0e00 << 16) | (0xc178 >> 2),
 124	0x00000000,
 125	(0x0e00 << 16) | (0xc204 >> 2),
 126	0x00000000,
 127	(0x0e00 << 16) | (0xc2b4 >> 2),
 128	0x00000000,
 129	(0x0e00 << 16) | (0xc2b8 >> 2),
 130	0x00000000,
 131	(0x0e00 << 16) | (0xc2bc >> 2),
 132	0x00000000,
 133	(0x0e00 << 16) | (0xc2c0 >> 2),
 134	0x00000000,
 135	(0x0e00 << 16) | (0x8228 >> 2),
 136	0x00000000,
 137	(0x0e00 << 16) | (0x829c >> 2),
 138	0x00000000,
 139	(0x0e00 << 16) | (0x869c >> 2),
 140	0x00000000,
 141	(0x0600 << 16) | (0x98f4 >> 2),
 142	0x00000000,
 143	(0x0e00 << 16) | (0x98f8 >> 2),
 144	0x00000000,
 145	(0x0e00 << 16) | (0x9900 >> 2),
 146	0x00000000,
 147	(0x0e00 << 16) | (0xc260 >> 2),
 148	0x00000000,
 149	(0x0e00 << 16) | (0x90e8 >> 2),
 150	0x00000000,
 151	(0x0e00 << 16) | (0x3c000 >> 2),
 152	0x00000000,
 153	(0x0e00 << 16) | (0x3c00c >> 2),
 154	0x00000000,
 155	(0x0e00 << 16) | (0x8c1c >> 2),
 156	0x00000000,
 157	(0x0e00 << 16) | (0x9700 >> 2),
 158	0x00000000,
 159	(0x0e00 << 16) | (0xcd20 >> 2),
 160	0x00000000,
 161	(0x4e00 << 16) | (0xcd20 >> 2),
 162	0x00000000,
 163	(0x5e00 << 16) | (0xcd20 >> 2),
 164	0x00000000,
 165	(0x6e00 << 16) | (0xcd20 >> 2),
 166	0x00000000,
 167	(0x7e00 << 16) | (0xcd20 >> 2),
 168	0x00000000,
 169	(0x8e00 << 16) | (0xcd20 >> 2),
 170	0x00000000,
 171	(0x9e00 << 16) | (0xcd20 >> 2),
 172	0x00000000,
 173	(0xae00 << 16) | (0xcd20 >> 2),
 174	0x00000000,
 175	(0xbe00 << 16) | (0xcd20 >> 2),
 176	0x00000000,
 177	(0x0e00 << 16) | (0x89bc >> 2),
 178	0x00000000,
 179	(0x0e00 << 16) | (0x8900 >> 2),
 180	0x00000000,
 181	0x3,
 182	(0x0e00 << 16) | (0xc130 >> 2),
 183	0x00000000,
 184	(0x0e00 << 16) | (0xc134 >> 2),
 185	0x00000000,
 186	(0x0e00 << 16) | (0xc1fc >> 2),
 187	0x00000000,
 188	(0x0e00 << 16) | (0xc208 >> 2),
 189	0x00000000,
 190	(0x0e00 << 16) | (0xc264 >> 2),
 191	0x00000000,
 192	(0x0e00 << 16) | (0xc268 >> 2),
 193	0x00000000,
 194	(0x0e00 << 16) | (0xc26c >> 2),
 195	0x00000000,
 196	(0x0e00 << 16) | (0xc270 >> 2),
 197	0x00000000,
 198	(0x0e00 << 16) | (0xc274 >> 2),
 199	0x00000000,
 200	(0x0e00 << 16) | (0xc278 >> 2),
 201	0x00000000,
 202	(0x0e00 << 16) | (0xc27c >> 2),
 203	0x00000000,
 204	(0x0e00 << 16) | (0xc280 >> 2),
 205	0x00000000,
 206	(0x0e00 << 16) | (0xc284 >> 2),
 207	0x00000000,
 208	(0x0e00 << 16) | (0xc288 >> 2),
 209	0x00000000,
 210	(0x0e00 << 16) | (0xc28c >> 2),
 211	0x00000000,
 212	(0x0e00 << 16) | (0xc290 >> 2),
 213	0x00000000,
 214	(0x0e00 << 16) | (0xc294 >> 2),
 215	0x00000000,
 216	(0x0e00 << 16) | (0xc298 >> 2),
 217	0x00000000,
 218	(0x0e00 << 16) | (0xc29c >> 2),
 219	0x00000000,
 220	(0x0e00 << 16) | (0xc2a0 >> 2),
 221	0x00000000,
 222	(0x0e00 << 16) | (0xc2a4 >> 2),
 223	0x00000000,
 224	(0x0e00 << 16) | (0xc2a8 >> 2),
 225	0x00000000,
 226	(0x0e00 << 16) | (0xc2ac  >> 2),
 227	0x00000000,
 228	(0x0e00 << 16) | (0xc2b0 >> 2),
 229	0x00000000,
 230	(0x0e00 << 16) | (0x301d0 >> 2),
 231	0x00000000,
 232	(0x0e00 << 16) | (0x30238 >> 2),
 233	0x00000000,
 234	(0x0e00 << 16) | (0x30250 >> 2),
 235	0x00000000,
 236	(0x0e00 << 16) | (0x30254 >> 2),
 237	0x00000000,
 238	(0x0e00 << 16) | (0x30258 >> 2),
 239	0x00000000,
 240	(0x0e00 << 16) | (0x3025c >> 2),
 241	0x00000000,
 242	(0x4e00 << 16) | (0xc900 >> 2),
 243	0x00000000,
 244	(0x5e00 << 16) | (0xc900 >> 2),
 245	0x00000000,
 246	(0x6e00 << 16) | (0xc900 >> 2),
 247	0x00000000,
 248	(0x7e00 << 16) | (0xc900 >> 2),
 249	0x00000000,
 250	(0x8e00 << 16) | (0xc900 >> 2),
 251	0x00000000,
 252	(0x9e00 << 16) | (0xc900 >> 2),
 253	0x00000000,
 254	(0xae00 << 16) | (0xc900 >> 2),
 255	0x00000000,
 256	(0xbe00 << 16) | (0xc900 >> 2),
 257	0x00000000,
 258	(0x4e00 << 16) | (0xc904 >> 2),
 259	0x00000000,
 260	(0x5e00 << 16) | (0xc904 >> 2),
 261	0x00000000,
 262	(0x6e00 << 16) | (0xc904 >> 2),
 263	0x00000000,
 264	(0x7e00 << 16) | (0xc904 >> 2),
 265	0x00000000,
 266	(0x8e00 << 16) | (0xc904 >> 2),
 267	0x00000000,
 268	(0x9e00 << 16) | (0xc904 >> 2),
 269	0x00000000,
 270	(0xae00 << 16) | (0xc904 >> 2),
 271	0x00000000,
 272	(0xbe00 << 16) | (0xc904 >> 2),
 273	0x00000000,
 274	(0x4e00 << 16) | (0xc908 >> 2),
 275	0x00000000,
 276	(0x5e00 << 16) | (0xc908 >> 2),
 277	0x00000000,
 278	(0x6e00 << 16) | (0xc908 >> 2),
 279	0x00000000,
 280	(0x7e00 << 16) | (0xc908 >> 2),
 281	0x00000000,
 282	(0x8e00 << 16) | (0xc908 >> 2),
 283	0x00000000,
 284	(0x9e00 << 16) | (0xc908 >> 2),
 285	0x00000000,
 286	(0xae00 << 16) | (0xc908 >> 2),
 287	0x00000000,
 288	(0xbe00 << 16) | (0xc908 >> 2),
 289	0x00000000,
 290	(0x4e00 << 16) | (0xc90c >> 2),
 291	0x00000000,
 292	(0x5e00 << 16) | (0xc90c >> 2),
 293	0x00000000,
 294	(0x6e00 << 16) | (0xc90c >> 2),
 295	0x00000000,
 296	(0x7e00 << 16) | (0xc90c >> 2),
 297	0x00000000,
 298	(0x8e00 << 16) | (0xc90c >> 2),
 299	0x00000000,
 300	(0x9e00 << 16) | (0xc90c >> 2),
 301	0x00000000,
 302	(0xae00 << 16) | (0xc90c >> 2),
 303	0x00000000,
 304	(0xbe00 << 16) | (0xc90c >> 2),
 305	0x00000000,
 306	(0x4e00 << 16) | (0xc910 >> 2),
 307	0x00000000,
 308	(0x5e00 << 16) | (0xc910 >> 2),
 309	0x00000000,
 310	(0x6e00 << 16) | (0xc910 >> 2),
 311	0x00000000,
 312	(0x7e00 << 16) | (0xc910 >> 2),
 313	0x00000000,
 314	(0x8e00 << 16) | (0xc910 >> 2),
 315	0x00000000,
 316	(0x9e00 << 16) | (0xc910 >> 2),
 317	0x00000000,
 318	(0xae00 << 16) | (0xc910 >> 2),
 319	0x00000000,
 320	(0xbe00 << 16) | (0xc910 >> 2),
 321	0x00000000,
 322	(0x0e00 << 16) | (0xc99c >> 2),
 323	0x00000000,
 324	(0x0e00 << 16) | (0x9834 >> 2),
 325	0x00000000,
 326	(0x0000 << 16) | (0x30f00 >> 2),
 327	0x00000000,
 328	(0x0001 << 16) | (0x30f00 >> 2),
 329	0x00000000,
 330	(0x0000 << 16) | (0x30f04 >> 2),
 331	0x00000000,
 332	(0x0001 << 16) | (0x30f04 >> 2),
 333	0x00000000,
 334	(0x0000 << 16) | (0x30f08 >> 2),
 335	0x00000000,
 336	(0x0001 << 16) | (0x30f08 >> 2),
 337	0x00000000,
 338	(0x0000 << 16) | (0x30f0c >> 2),
 339	0x00000000,
 340	(0x0001 << 16) | (0x30f0c >> 2),
 341	0x00000000,
 342	(0x0600 << 16) | (0x9b7c >> 2),
 343	0x00000000,
 344	(0x0e00 << 16) | (0x8a14 >> 2),
 345	0x00000000,
 346	(0x0e00 << 16) | (0x8a18 >> 2),
 347	0x00000000,
 348	(0x0600 << 16) | (0x30a00 >> 2),
 349	0x00000000,
 350	(0x0e00 << 16) | (0x8bf0 >> 2),
 351	0x00000000,
 352	(0x0e00 << 16) | (0x8bcc >> 2),
 353	0x00000000,
 354	(0x0e00 << 16) | (0x8b24 >> 2),
 355	0x00000000,
 356	(0x0e00 << 16) | (0x30a04 >> 2),
 357	0x00000000,
 358	(0x0600 << 16) | (0x30a10 >> 2),
 359	0x00000000,
 360	(0x0600 << 16) | (0x30a14 >> 2),
 361	0x00000000,
 362	(0x0600 << 16) | (0x30a18 >> 2),
 363	0x00000000,
 364	(0x0600 << 16) | (0x30a2c >> 2),
 365	0x00000000,
 366	(0x0e00 << 16) | (0xc700 >> 2),
 367	0x00000000,
 368	(0x0e00 << 16) | (0xc704 >> 2),
 369	0x00000000,
 370	(0x0e00 << 16) | (0xc708 >> 2),
 371	0x00000000,
 372	(0x0e00 << 16) | (0xc768 >> 2),
 373	0x00000000,
 374	(0x0400 << 16) | (0xc770 >> 2),
 375	0x00000000,
 376	(0x0400 << 16) | (0xc774 >> 2),
 377	0x00000000,
 378	(0x0400 << 16) | (0xc778 >> 2),
 379	0x00000000,
 380	(0x0400 << 16) | (0xc77c >> 2),
 381	0x00000000,
 382	(0x0400 << 16) | (0xc780 >> 2),
 383	0x00000000,
 384	(0x0400 << 16) | (0xc784 >> 2),
 385	0x00000000,
 386	(0x0400 << 16) | (0xc788 >> 2),
 387	0x00000000,
 388	(0x0400 << 16) | (0xc78c >> 2),
 389	0x00000000,
 390	(0x0400 << 16) | (0xc798 >> 2),
 391	0x00000000,
 392	(0x0400 << 16) | (0xc79c >> 2),
 393	0x00000000,
 394	(0x0400 << 16) | (0xc7a0 >> 2),
 395	0x00000000,
 396	(0x0400 << 16) | (0xc7a4 >> 2),
 397	0x00000000,
 398	(0x0400 << 16) | (0xc7a8 >> 2),
 399	0x00000000,
 400	(0x0400 << 16) | (0xc7ac >> 2),
 401	0x00000000,
 402	(0x0400 << 16) | (0xc7b0 >> 2),
 403	0x00000000,
 404	(0x0400 << 16) | (0xc7b4 >> 2),
 405	0x00000000,
 406	(0x0e00 << 16) | (0x9100 >> 2),
 407	0x00000000,
 408	(0x0e00 << 16) | (0x3c010 >> 2),
 409	0x00000000,
 410	(0x0e00 << 16) | (0x92a8 >> 2),
 411	0x00000000,
 412	(0x0e00 << 16) | (0x92ac >> 2),
 413	0x00000000,
 414	(0x0e00 << 16) | (0x92b4 >> 2),
 415	0x00000000,
 416	(0x0e00 << 16) | (0x92b8 >> 2),
 417	0x00000000,
 418	(0x0e00 << 16) | (0x92bc >> 2),
 419	0x00000000,
 420	(0x0e00 << 16) | (0x92c0 >> 2),
 421	0x00000000,
 422	(0x0e00 << 16) | (0x92c4 >> 2),
 423	0x00000000,
 424	(0x0e00 << 16) | (0x92c8 >> 2),
 425	0x00000000,
 426	(0x0e00 << 16) | (0x92cc >> 2),
 427	0x00000000,
 428	(0x0e00 << 16) | (0x92d0 >> 2),
 429	0x00000000,
 430	(0x0e00 << 16) | (0x8c00 >> 2),
 431	0x00000000,
 432	(0x0e00 << 16) | (0x8c04 >> 2),
 433	0x00000000,
 434	(0x0e00 << 16) | (0x8c20 >> 2),
 435	0x00000000,
 436	(0x0e00 << 16) | (0x8c38 >> 2),
 437	0x00000000,
 438	(0x0e00 << 16) | (0x8c3c >> 2),
 439	0x00000000,
 440	(0x0e00 << 16) | (0xae00 >> 2),
 441	0x00000000,
 442	(0x0e00 << 16) | (0x9604 >> 2),
 443	0x00000000,
 444	(0x0e00 << 16) | (0xac08 >> 2),
 445	0x00000000,
 446	(0x0e00 << 16) | (0xac0c >> 2),
 447	0x00000000,
 448	(0x0e00 << 16) | (0xac10 >> 2),
 449	0x00000000,
 450	(0x0e00 << 16) | (0xac14 >> 2),
 451	0x00000000,
 452	(0x0e00 << 16) | (0xac58 >> 2),
 453	0x00000000,
 454	(0x0e00 << 16) | (0xac68 >> 2),
 455	0x00000000,
 456	(0x0e00 << 16) | (0xac6c >> 2),
 457	0x00000000,
 458	(0x0e00 << 16) | (0xac70 >> 2),
 459	0x00000000,
 460	(0x0e00 << 16) | (0xac74 >> 2),
 461	0x00000000,
 462	(0x0e00 << 16) | (0xac78 >> 2),
 463	0x00000000,
 464	(0x0e00 << 16) | (0xac7c >> 2),
 465	0x00000000,
 466	(0x0e00 << 16) | (0xac80 >> 2),
 467	0x00000000,
 468	(0x0e00 << 16) | (0xac84 >> 2),
 469	0x00000000,
 470	(0x0e00 << 16) | (0xac88 >> 2),
 471	0x00000000,
 472	(0x0e00 << 16) | (0xac8c >> 2),
 473	0x00000000,
 474	(0x0e00 << 16) | (0x970c >> 2),
 475	0x00000000,
 476	(0x0e00 << 16) | (0x9714 >> 2),
 477	0x00000000,
 478	(0x0e00 << 16) | (0x9718 >> 2),
 479	0x00000000,
 480	(0x0e00 << 16) | (0x971c >> 2),
 481	0x00000000,
 482	(0x0e00 << 16) | (0x31068 >> 2),
 483	0x00000000,
 484	(0x4e00 << 16) | (0x31068 >> 2),
 485	0x00000000,
 486	(0x5e00 << 16) | (0x31068 >> 2),
 487	0x00000000,
 488	(0x6e00 << 16) | (0x31068 >> 2),
 489	0x00000000,
 490	(0x7e00 << 16) | (0x31068 >> 2),
 491	0x00000000,
 492	(0x8e00 << 16) | (0x31068 >> 2),
 493	0x00000000,
 494	(0x9e00 << 16) | (0x31068 >> 2),
 495	0x00000000,
 496	(0xae00 << 16) | (0x31068 >> 2),
 497	0x00000000,
 498	(0xbe00 << 16) | (0x31068 >> 2),
 499	0x00000000,
 500	(0x0e00 << 16) | (0xcd10 >> 2),
 501	0x00000000,
 502	(0x0e00 << 16) | (0xcd14 >> 2),
 503	0x00000000,
 504	(0x0e00 << 16) | (0x88b0 >> 2),
 505	0x00000000,
 506	(0x0e00 << 16) | (0x88b4 >> 2),
 507	0x00000000,
 508	(0x0e00 << 16) | (0x88b8 >> 2),
 509	0x00000000,
 510	(0x0e00 << 16) | (0x88bc >> 2),
 511	0x00000000,
 512	(0x0400 << 16) | (0x89c0 >> 2),
 513	0x00000000,
 514	(0x0e00 << 16) | (0x88c4 >> 2),
 515	0x00000000,
 516	(0x0e00 << 16) | (0x88c8 >> 2),
 517	0x00000000,
 518	(0x0e00 << 16) | (0x88d0 >> 2),
 519	0x00000000,
 520	(0x0e00 << 16) | (0x88d4 >> 2),
 521	0x00000000,
 522	(0x0e00 << 16) | (0x88d8 >> 2),
 523	0x00000000,
 524	(0x0e00 << 16) | (0x8980 >> 2),
 525	0x00000000,
 526	(0x0e00 << 16) | (0x30938 >> 2),
 527	0x00000000,
 528	(0x0e00 << 16) | (0x3093c >> 2),
 529	0x00000000,
 530	(0x0e00 << 16) | (0x30940 >> 2),
 531	0x00000000,
 532	(0x0e00 << 16) | (0x89a0 >> 2),
 533	0x00000000,
 534	(0x0e00 << 16) | (0x30900 >> 2),
 535	0x00000000,
 536	(0x0e00 << 16) | (0x30904 >> 2),
 537	0x00000000,
 538	(0x0e00 << 16) | (0x89b4 >> 2),
 539	0x00000000,
 540	(0x0e00 << 16) | (0x3c210 >> 2),
 541	0x00000000,
 542	(0x0e00 << 16) | (0x3c214 >> 2),
 543	0x00000000,
 544	(0x0e00 << 16) | (0x3c218 >> 2),
 545	0x00000000,
 546	(0x0e00 << 16) | (0x8904 >> 2),
 547	0x00000000,
 548	0x5,
 549	(0x0e00 << 16) | (0x8c28 >> 2),
 550	(0x0e00 << 16) | (0x8c2c >> 2),
 551	(0x0e00 << 16) | (0x8c30 >> 2),
 552	(0x0e00 << 16) | (0x8c34 >> 2),
 553	(0x0e00 << 16) | (0x9600 >> 2),
 554};
 555
 556static const u32 kalindi_rlc_save_restore_register_list[] =
 557{
 558	(0x0e00 << 16) | (0xc12c >> 2),
 559	0x00000000,
 560	(0x0e00 << 16) | (0xc140 >> 2),
 561	0x00000000,
 562	(0x0e00 << 16) | (0xc150 >> 2),
 563	0x00000000,
 564	(0x0e00 << 16) | (0xc15c >> 2),
 565	0x00000000,
 566	(0x0e00 << 16) | (0xc168 >> 2),
 567	0x00000000,
 568	(0x0e00 << 16) | (0xc170 >> 2),
 569	0x00000000,
 570	(0x0e00 << 16) | (0xc204 >> 2),
 571	0x00000000,
 572	(0x0e00 << 16) | (0xc2b4 >> 2),
 573	0x00000000,
 574	(0x0e00 << 16) | (0xc2b8 >> 2),
 575	0x00000000,
 576	(0x0e00 << 16) | (0xc2bc >> 2),
 577	0x00000000,
 578	(0x0e00 << 16) | (0xc2c0 >> 2),
 579	0x00000000,
 580	(0x0e00 << 16) | (0x8228 >> 2),
 581	0x00000000,
 582	(0x0e00 << 16) | (0x829c >> 2),
 583	0x00000000,
 584	(0x0e00 << 16) | (0x869c >> 2),
 585	0x00000000,
 586	(0x0600 << 16) | (0x98f4 >> 2),
 587	0x00000000,
 588	(0x0e00 << 16) | (0x98f8 >> 2),
 589	0x00000000,
 590	(0x0e00 << 16) | (0x9900 >> 2),
 591	0x00000000,
 592	(0x0e00 << 16) | (0xc260 >> 2),
 593	0x00000000,
 594	(0x0e00 << 16) | (0x90e8 >> 2),
 595	0x00000000,
 596	(0x0e00 << 16) | (0x3c000 >> 2),
 597	0x00000000,
 598	(0x0e00 << 16) | (0x3c00c >> 2),
 599	0x00000000,
 600	(0x0e00 << 16) | (0x8c1c >> 2),
 601	0x00000000,
 602	(0x0e00 << 16) | (0x9700 >> 2),
 603	0x00000000,
 604	(0x0e00 << 16) | (0xcd20 >> 2),
 605	0x00000000,
 606	(0x4e00 << 16) | (0xcd20 >> 2),
 607	0x00000000,
 608	(0x5e00 << 16) | (0xcd20 >> 2),
 609	0x00000000,
 610	(0x6e00 << 16) | (0xcd20 >> 2),
 611	0x00000000,
 612	(0x7e00 << 16) | (0xcd20 >> 2),
 613	0x00000000,
 614	(0x0e00 << 16) | (0x89bc >> 2),
 615	0x00000000,
 616	(0x0e00 << 16) | (0x8900 >> 2),
 617	0x00000000,
 618	0x3,
 619	(0x0e00 << 16) | (0xc130 >> 2),
 620	0x00000000,
 621	(0x0e00 << 16) | (0xc134 >> 2),
 622	0x00000000,
 623	(0x0e00 << 16) | (0xc1fc >> 2),
 624	0x00000000,
 625	(0x0e00 << 16) | (0xc208 >> 2),
 626	0x00000000,
 627	(0x0e00 << 16) | (0xc264 >> 2),
 628	0x00000000,
 629	(0x0e00 << 16) | (0xc268 >> 2),
 630	0x00000000,
 631	(0x0e00 << 16) | (0xc26c >> 2),
 632	0x00000000,
 633	(0x0e00 << 16) | (0xc270 >> 2),
 634	0x00000000,
 635	(0x0e00 << 16) | (0xc274 >> 2),
 636	0x00000000,
 637	(0x0e00 << 16) | (0xc28c >> 2),
 638	0x00000000,
 639	(0x0e00 << 16) | (0xc290 >> 2),
 640	0x00000000,
 641	(0x0e00 << 16) | (0xc294 >> 2),
 642	0x00000000,
 643	(0x0e00 << 16) | (0xc298 >> 2),
 644	0x00000000,
 645	(0x0e00 << 16) | (0xc2a0 >> 2),
 646	0x00000000,
 647	(0x0e00 << 16) | (0xc2a4 >> 2),
 648	0x00000000,
 649	(0x0e00 << 16) | (0xc2a8 >> 2),
 650	0x00000000,
 651	(0x0e00 << 16) | (0xc2ac >> 2),
 652	0x00000000,
 653	(0x0e00 << 16) | (0x301d0 >> 2),
 654	0x00000000,
 655	(0x0e00 << 16) | (0x30238 >> 2),
 656	0x00000000,
 657	(0x0e00 << 16) | (0x30250 >> 2),
 658	0x00000000,
 659	(0x0e00 << 16) | (0x30254 >> 2),
 660	0x00000000,
 661	(0x0e00 << 16) | (0x30258 >> 2),
 662	0x00000000,
 663	(0x0e00 << 16) | (0x3025c >> 2),
 664	0x00000000,
 665	(0x4e00 << 16) | (0xc900 >> 2),
 666	0x00000000,
 667	(0x5e00 << 16) | (0xc900 >> 2),
 668	0x00000000,
 669	(0x6e00 << 16) | (0xc900 >> 2),
 670	0x00000000,
 671	(0x7e00 << 16) | (0xc900 >> 2),
 672	0x00000000,
 673	(0x4e00 << 16) | (0xc904 >> 2),
 674	0x00000000,
 675	(0x5e00 << 16) | (0xc904 >> 2),
 676	0x00000000,
 677	(0x6e00 << 16) | (0xc904 >> 2),
 678	0x00000000,
 679	(0x7e00 << 16) | (0xc904 >> 2),
 680	0x00000000,
 681	(0x4e00 << 16) | (0xc908 >> 2),
 682	0x00000000,
 683	(0x5e00 << 16) | (0xc908 >> 2),
 684	0x00000000,
 685	(0x6e00 << 16) | (0xc908 >> 2),
 686	0x00000000,
 687	(0x7e00 << 16) | (0xc908 >> 2),
 688	0x00000000,
 689	(0x4e00 << 16) | (0xc90c >> 2),
 690	0x00000000,
 691	(0x5e00 << 16) | (0xc90c >> 2),
 692	0x00000000,
 693	(0x6e00 << 16) | (0xc90c >> 2),
 694	0x00000000,
 695	(0x7e00 << 16) | (0xc90c >> 2),
 696	0x00000000,
 697	(0x4e00 << 16) | (0xc910 >> 2),
 698	0x00000000,
 699	(0x5e00 << 16) | (0xc910 >> 2),
 700	0x00000000,
 701	(0x6e00 << 16) | (0xc910 >> 2),
 702	0x00000000,
 703	(0x7e00 << 16) | (0xc910 >> 2),
 704	0x00000000,
 705	(0x0e00 << 16) | (0xc99c >> 2),
 706	0x00000000,
 707	(0x0e00 << 16) | (0x9834 >> 2),
 708	0x00000000,
 709	(0x0000 << 16) | (0x30f00 >> 2),
 710	0x00000000,
 711	(0x0000 << 16) | (0x30f04 >> 2),
 712	0x00000000,
 713	(0x0000 << 16) | (0x30f08 >> 2),
 714	0x00000000,
 715	(0x0000 << 16) | (0x30f0c >> 2),
 716	0x00000000,
 717	(0x0600 << 16) | (0x9b7c >> 2),
 718	0x00000000,
 719	(0x0e00 << 16) | (0x8a14 >> 2),
 720	0x00000000,
 721	(0x0e00 << 16) | (0x8a18 >> 2),
 722	0x00000000,
 723	(0x0600 << 16) | (0x30a00 >> 2),
 724	0x00000000,
 725	(0x0e00 << 16) | (0x8bf0 >> 2),
 726	0x00000000,
 727	(0x0e00 << 16) | (0x8bcc >> 2),
 728	0x00000000,
 729	(0x0e00 << 16) | (0x8b24 >> 2),
 730	0x00000000,
 731	(0x0e00 << 16) | (0x30a04 >> 2),
 732	0x00000000,
 733	(0x0600 << 16) | (0x30a10 >> 2),
 734	0x00000000,
 735	(0x0600 << 16) | (0x30a14 >> 2),
 736	0x00000000,
 737	(0x0600 << 16) | (0x30a18 >> 2),
 738	0x00000000,
 739	(0x0600 << 16) | (0x30a2c >> 2),
 740	0x00000000,
 741	(0x0e00 << 16) | (0xc700 >> 2),
 742	0x00000000,
 743	(0x0e00 << 16) | (0xc704 >> 2),
 744	0x00000000,
 745	(0x0e00 << 16) | (0xc708 >> 2),
 746	0x00000000,
 747	(0x0e00 << 16) | (0xc768 >> 2),
 748	0x00000000,
 749	(0x0400 << 16) | (0xc770 >> 2),
 750	0x00000000,
 751	(0x0400 << 16) | (0xc774 >> 2),
 752	0x00000000,
 753	(0x0400 << 16) | (0xc798 >> 2),
 754	0x00000000,
 755	(0x0400 << 16) | (0xc79c >> 2),
 756	0x00000000,
 757	(0x0e00 << 16) | (0x9100 >> 2),
 758	0x00000000,
 759	(0x0e00 << 16) | (0x3c010 >> 2),
 760	0x00000000,
 761	(0x0e00 << 16) | (0x8c00 >> 2),
 762	0x00000000,
 763	(0x0e00 << 16) | (0x8c04 >> 2),
 764	0x00000000,
 765	(0x0e00 << 16) | (0x8c20 >> 2),
 766	0x00000000,
 767	(0x0e00 << 16) | (0x8c38 >> 2),
 768	0x00000000,
 769	(0x0e00 << 16) | (0x8c3c >> 2),
 770	0x00000000,
 771	(0x0e00 << 16) | (0xae00 >> 2),
 772	0x00000000,
 773	(0x0e00 << 16) | (0x9604 >> 2),
 774	0x00000000,
 775	(0x0e00 << 16) | (0xac08 >> 2),
 776	0x00000000,
 777	(0x0e00 << 16) | (0xac0c >> 2),
 778	0x00000000,
 779	(0x0e00 << 16) | (0xac10 >> 2),
 780	0x00000000,
 781	(0x0e00 << 16) | (0xac14 >> 2),
 782	0x00000000,
 783	(0x0e00 << 16) | (0xac58 >> 2),
 784	0x00000000,
 785	(0x0e00 << 16) | (0xac68 >> 2),
 786	0x00000000,
 787	(0x0e00 << 16) | (0xac6c >> 2),
 788	0x00000000,
 789	(0x0e00 << 16) | (0xac70 >> 2),
 790	0x00000000,
 791	(0x0e00 << 16) | (0xac74 >> 2),
 792	0x00000000,
 793	(0x0e00 << 16) | (0xac78 >> 2),
 794	0x00000000,
 795	(0x0e00 << 16) | (0xac7c >> 2),
 796	0x00000000,
 797	(0x0e00 << 16) | (0xac80 >> 2),
 798	0x00000000,
 799	(0x0e00 << 16) | (0xac84 >> 2),
 800	0x00000000,
 801	(0x0e00 << 16) | (0xac88 >> 2),
 802	0x00000000,
 803	(0x0e00 << 16) | (0xac8c >> 2),
 804	0x00000000,
 805	(0x0e00 << 16) | (0x970c >> 2),
 806	0x00000000,
 807	(0x0e00 << 16) | (0x9714 >> 2),
 808	0x00000000,
 809	(0x0e00 << 16) | (0x9718 >> 2),
 810	0x00000000,
 811	(0x0e00 << 16) | (0x971c >> 2),
 812	0x00000000,
 813	(0x0e00 << 16) | (0x31068 >> 2),
 814	0x00000000,
 815	(0x4e00 << 16) | (0x31068 >> 2),
 816	0x00000000,
 817	(0x5e00 << 16) | (0x31068 >> 2),
 818	0x00000000,
 819	(0x6e00 << 16) | (0x31068 >> 2),
 820	0x00000000,
 821	(0x7e00 << 16) | (0x31068 >> 2),
 822	0x00000000,
 823	(0x0e00 << 16) | (0xcd10 >> 2),
 824	0x00000000,
 825	(0x0e00 << 16) | (0xcd14 >> 2),
 826	0x00000000,
 827	(0x0e00 << 16) | (0x88b0 >> 2),
 828	0x00000000,
 829	(0x0e00 << 16) | (0x88b4 >> 2),
 830	0x00000000,
 831	(0x0e00 << 16) | (0x88b8 >> 2),
 832	0x00000000,
 833	(0x0e00 << 16) | (0x88bc >> 2),
 834	0x00000000,
 835	(0x0400 << 16) | (0x89c0 >> 2),
 836	0x00000000,
 837	(0x0e00 << 16) | (0x88c4 >> 2),
 838	0x00000000,
 839	(0x0e00 << 16) | (0x88c8 >> 2),
 840	0x00000000,
 841	(0x0e00 << 16) | (0x88d0 >> 2),
 842	0x00000000,
 843	(0x0e00 << 16) | (0x88d4 >> 2),
 844	0x00000000,
 845	(0x0e00 << 16) | (0x88d8 >> 2),
 846	0x00000000,
 847	(0x0e00 << 16) | (0x8980 >> 2),
 848	0x00000000,
 849	(0x0e00 << 16) | (0x30938 >> 2),
 850	0x00000000,
 851	(0x0e00 << 16) | (0x3093c >> 2),
 852	0x00000000,
 853	(0x0e00 << 16) | (0x30940 >> 2),
 854	0x00000000,
 855	(0x0e00 << 16) | (0x89a0 >> 2),
 856	0x00000000,
 857	(0x0e00 << 16) | (0x30900 >> 2),
 858	0x00000000,
 859	(0x0e00 << 16) | (0x30904 >> 2),
 860	0x00000000,
 861	(0x0e00 << 16) | (0x89b4 >> 2),
 862	0x00000000,
 863	(0x0e00 << 16) | (0x3e1fc >> 2),
 864	0x00000000,
 865	(0x0e00 << 16) | (0x3c210 >> 2),
 866	0x00000000,
 867	(0x0e00 << 16) | (0x3c214 >> 2),
 868	0x00000000,
 869	(0x0e00 << 16) | (0x3c218 >> 2),
 870	0x00000000,
 871	(0x0e00 << 16) | (0x8904 >> 2),
 872	0x00000000,
 873	0x5,
 874	(0x0e00 << 16) | (0x8c28 >> 2),
 875	(0x0e00 << 16) | (0x8c2c >> 2),
 876	(0x0e00 << 16) | (0x8c30 >> 2),
 877	(0x0e00 << 16) | (0x8c34 >> 2),
 878	(0x0e00 << 16) | (0x9600 >> 2),
 879};
 880
 881static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev);
 882static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer);
 883static void gfx_v7_0_init_cp_pg_table(struct amdgpu_device *adev);
 884static void gfx_v7_0_init_pg(struct amdgpu_device *adev);
 885static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev);
 886
 887/*
 888 * Core functions
 889 */
 890/**
 891 * gfx_v7_0_init_microcode - load ucode images from disk
 892 *
 893 * @adev: amdgpu_device pointer
 894 *
 895 * Use the firmware interface to load the ucode images into
 896 * the driver (not loaded into hw).
 897 * Returns 0 on success, error on failure.
 898 */
 899static int gfx_v7_0_init_microcode(struct amdgpu_device *adev)
 900{
 901	const char *chip_name;
 902	char fw_name[30];
 903	int err;
 904
 905	DRM_DEBUG("\n");
 906
 907	switch (adev->asic_type) {
 908	case CHIP_BONAIRE:
 909		chip_name = "bonaire";
 910		break;
 911	case CHIP_HAWAII:
 912		chip_name = "hawaii";
 913		break;
 914	case CHIP_KAVERI:
 915		chip_name = "kaveri";
 916		break;
 917	case CHIP_KABINI:
 918		chip_name = "kabini";
 919		break;
 920	case CHIP_MULLINS:
 921		chip_name = "mullins";
 922		break;
 923	default: BUG();
 924	}
 925
 926	snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
 927	err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
 928	if (err)
 929		goto out;
 930	err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
 931	if (err)
 932		goto out;
 933
 934	snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
 935	err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
 936	if (err)
 937		goto out;
 938	err = amdgpu_ucode_validate(adev->gfx.me_fw);
 939	if (err)
 940		goto out;
 941
 942	snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name);
 943	err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
 944	if (err)
 945		goto out;
 946	err = amdgpu_ucode_validate(adev->gfx.ce_fw);
 947	if (err)
 948		goto out;
 949
 950	snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec.bin", chip_name);
 951	err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
 952	if (err)
 953		goto out;
 954	err = amdgpu_ucode_validate(adev->gfx.mec_fw);
 955	if (err)
 956		goto out;
 957
 958	if (adev->asic_type == CHIP_KAVERI) {
 959		snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec2.bin", chip_name);
 960		err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
 961		if (err)
 962			goto out;
 963		err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
 964		if (err)
 965			goto out;
 966	}
 967
 968	snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", chip_name);
 969	err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
 970	if (err)
 971		goto out;
 972	err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
 973
 974out:
 975	if (err) {
 976		pr_err("gfx7: Failed to load firmware \"%s\"\n", fw_name);
 977		release_firmware(adev->gfx.pfp_fw);
 978		adev->gfx.pfp_fw = NULL;
 979		release_firmware(adev->gfx.me_fw);
 980		adev->gfx.me_fw = NULL;
 981		release_firmware(adev->gfx.ce_fw);
 982		adev->gfx.ce_fw = NULL;
 983		release_firmware(adev->gfx.mec_fw);
 984		adev->gfx.mec_fw = NULL;
 985		release_firmware(adev->gfx.mec2_fw);
 986		adev->gfx.mec2_fw = NULL;
 987		release_firmware(adev->gfx.rlc_fw);
 988		adev->gfx.rlc_fw = NULL;
 989	}
 990	return err;
 991}
 992
 993static void gfx_v7_0_free_microcode(struct amdgpu_device *adev)
 994{
 995	release_firmware(adev->gfx.pfp_fw);
 996	adev->gfx.pfp_fw = NULL;
 997	release_firmware(adev->gfx.me_fw);
 998	adev->gfx.me_fw = NULL;
 999	release_firmware(adev->gfx.ce_fw);
1000	adev->gfx.ce_fw = NULL;
1001	release_firmware(adev->gfx.mec_fw);
1002	adev->gfx.mec_fw = NULL;
1003	release_firmware(adev->gfx.mec2_fw);
1004	adev->gfx.mec2_fw = NULL;
1005	release_firmware(adev->gfx.rlc_fw);
1006	adev->gfx.rlc_fw = NULL;
1007}
1008
1009/**
1010 * gfx_v7_0_tiling_mode_table_init - init the hw tiling table
1011 *
1012 * @adev: amdgpu_device pointer
1013 *
1014 * Starting with SI, the tiling setup is done globally in a
1015 * set of 32 tiling modes.  Rather than selecting each set of
1016 * parameters per surface as on older asics, we just select
1017 * which index in the tiling table we want to use, and the
1018 * surface uses those parameters (CIK).
1019 */
1020static void gfx_v7_0_tiling_mode_table_init(struct amdgpu_device *adev)
1021{
1022	const u32 num_tile_mode_states =
1023			ARRAY_SIZE(adev->gfx.config.tile_mode_array);
1024	const u32 num_secondary_tile_mode_states =
1025			ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
1026	u32 reg_offset, split_equal_to_row_size;
1027	uint32_t *tile, *macrotile;
1028
1029	tile = adev->gfx.config.tile_mode_array;
1030	macrotile = adev->gfx.config.macrotile_mode_array;
1031
1032	switch (adev->gfx.config.mem_row_size_in_kb) {
1033	case 1:
1034		split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
1035		break;
1036	case 2:
1037	default:
1038		split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
1039		break;
1040	case 4:
1041		split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
1042		break;
1043	}
1044
1045	for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1046		tile[reg_offset] = 0;
1047	for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1048		macrotile[reg_offset] = 0;
1049
1050	switch (adev->asic_type) {
1051	case CHIP_BONAIRE:
1052		tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1053			   PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1054			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1055			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1056		tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1057			   PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1058			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1059			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1060		tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1061			   PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1062			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1063			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1064		tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1065			   PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1066			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1067			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1068		tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1069			   PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1070			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1071			   TILE_SPLIT(split_equal_to_row_size));
1072		tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1073			   PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1074			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1075		tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1076			   PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1077			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1078			   TILE_SPLIT(split_equal_to_row_size));
1079		tile[7] = (TILE_SPLIT(split_equal_to_row_size));
1080		tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1081			   PIPE_CONFIG(ADDR_SURF_P4_16x16));
1082		tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1083			   PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1084			   MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
1085		tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1086			    PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1087			    MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1088			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1089		tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1090			    PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1091			    MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1092			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1093		tile[12] = (TILE_SPLIT(split_equal_to_row_size));
1094		tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1095			    PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1096			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1097		tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1098			    PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1099			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1100			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1101		tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1102			    PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1103			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1104			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1105		tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1106			    PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1107			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1108			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1109		tile[17] = (TILE_SPLIT(split_equal_to_row_size));
1110		tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1111			    PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1112			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1113			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1114		tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1115			    PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1116			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1117		tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1118			    PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1119			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1120			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1121		tile[21] =  (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1122			    PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1123			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1124			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1125		tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1126			    PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1127			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1128			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1129		tile[23] = (TILE_SPLIT(split_equal_to_row_size));
1130		tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1131			    PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1132			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1133			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1134		tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1135			    PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1136			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1137			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1138		tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1139			    PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1140			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1141			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1142		tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1143			    PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1144			    MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
1145		tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1146			    PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1147			    MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1148			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1149		tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1150			    PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1151			    MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1152			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1153		tile[30] = (TILE_SPLIT(split_equal_to_row_size));
1154
1155		macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1156				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1157				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1158				NUM_BANKS(ADDR_SURF_16_BANK));
1159		macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1160				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1161				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1162				NUM_BANKS(ADDR_SURF_16_BANK));
1163		macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1164				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1165				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1166				NUM_BANKS(ADDR_SURF_16_BANK));
1167		macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1168				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1169				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1170				NUM_BANKS(ADDR_SURF_16_BANK));
1171		macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1172				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1173				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1174				NUM_BANKS(ADDR_SURF_16_BANK));
1175		macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1176				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1177				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1178				NUM_BANKS(ADDR_SURF_8_BANK));
1179		macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1180				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1181				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1182				NUM_BANKS(ADDR_SURF_4_BANK));
1183		macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1184				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1185				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1186				NUM_BANKS(ADDR_SURF_16_BANK));
1187		macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1188				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1189				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1190				NUM_BANKS(ADDR_SURF_16_BANK));
1191		macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1192				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1193				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1194				NUM_BANKS(ADDR_SURF_16_BANK));
1195		macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1196				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1197				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1198				NUM_BANKS(ADDR_SURF_16_BANK));
1199		macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1200				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1201				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1202				NUM_BANKS(ADDR_SURF_16_BANK));
1203		macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1204				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1205				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1206				NUM_BANKS(ADDR_SURF_8_BANK));
1207		macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1208				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1209				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1210				NUM_BANKS(ADDR_SURF_4_BANK));
1211
1212		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1213			WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
1214		for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1215			if (reg_offset != 7)
1216				WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);
1217		break;
1218	case CHIP_HAWAII:
1219		tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1220			   PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1221			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1222			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1223		tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1224			   PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1225			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1226			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1227		tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1228			   PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1229			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1230			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1231		tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1232			   PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1233			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1234			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1235		tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1236			   PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1237			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1238			   TILE_SPLIT(split_equal_to_row_size));
1239		tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1240			   PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1241			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1242			   TILE_SPLIT(split_equal_to_row_size));
1243		tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1244			   PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1245			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1246			   TILE_SPLIT(split_equal_to_row_size));
1247		tile[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1248			   PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1249			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1250			   TILE_SPLIT(split_equal_to_row_size));
1251		tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1252			   PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16));
1253		tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1254			   PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1255			   MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
1256		tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1257			    PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1258			    MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1259			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1260		tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1261			    PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1262			    MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1263			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1264		tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
1265			    PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1266			    MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1267			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1268		tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1269			    PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1270			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1271		tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1272			    PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1273			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1274			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1275		tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1276			    PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1277			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1278			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1279		tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1280			    PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1281			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1282			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1283		tile[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1284			    PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1285			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1286			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1287		tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1288			    PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1289			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1290			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1291		tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1292			    PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1293			    MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING));
1294		tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1295			    PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1296			    MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1297			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1298		tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1299			    PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1300			    MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1301			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1302		tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1303			    PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1304			    MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1305			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1306		tile[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1307			    PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1308			    MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1309			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1310		tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1311			    PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1312			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1313			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1314		tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1315			    PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1316			    MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1317			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1318		tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1319			    PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1320			    MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1321			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1322		tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1323			    PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1324			    MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
1325		tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1326			    PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1327			    MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1328			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1329		tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1330			    PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1331			    MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1332			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1333		tile[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1334			    PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1335			    MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1336			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1337
1338		macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1339				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1340				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1341				NUM_BANKS(ADDR_SURF_16_BANK));
1342		macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1343				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1344				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1345				NUM_BANKS(ADDR_SURF_16_BANK));
1346		macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1347				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1348				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1349				NUM_BANKS(ADDR_SURF_16_BANK));
1350		macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1351				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1352				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1353				NUM_BANKS(ADDR_SURF_16_BANK));
1354		macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1355				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1356				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1357				NUM_BANKS(ADDR_SURF_8_BANK));
1358		macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1359				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1360				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1361				NUM_BANKS(ADDR_SURF_4_BANK));
1362		macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1363				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1364				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1365				NUM_BANKS(ADDR_SURF_4_BANK));
1366		macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1367				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1368				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1369				NUM_BANKS(ADDR_SURF_16_BANK));
1370		macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1371				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1372				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1373				NUM_BANKS(ADDR_SURF_16_BANK));
1374		macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1375				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1376				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1377				NUM_BANKS(ADDR_SURF_16_BANK));
1378		macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1379				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1380				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1381				NUM_BANKS(ADDR_SURF_8_BANK));
1382		macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1383				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1384				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1385				NUM_BANKS(ADDR_SURF_16_BANK));
1386		macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1387				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1388				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1389				NUM_BANKS(ADDR_SURF_8_BANK));
1390		macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1391				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1392				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1393				NUM_BANKS(ADDR_SURF_4_BANK));
1394
1395		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1396			WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);
1397		for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
1398			if (reg_offset != 7)
1399				WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);
1400		break;
1401	case CHIP_KABINI:
1402	case CHIP_KAVERI:
1403	case CHIP_MULLINS:
1404	default:
1405		tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1406			   PIPE_CONFIG(ADDR_SURF_P2) |
1407			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1408			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1409		tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1410			   PIPE_CONFIG(ADDR_SURF_P2) |
1411			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1412			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1413		tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1414			   PIPE_CONFIG(ADDR_SURF_P2) |
1415			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1416			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1417		tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1418			   PIPE_CONFIG(ADDR_SURF_P2) |
1419			   TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1420			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1421		tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1422			   PIPE_CONFIG(ADDR_SURF_P2) |
1423			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1424			   TILE_SPLIT(split_equal_to_row_size));
1425		tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1426			   PIPE_CONFIG(ADDR_SURF_P2) |
1427			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1428		tile[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1429			   PIPE_CONFIG(ADDR_SURF_P2) |
1430			   MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1431			   TILE_SPLIT(split_equal_to_row_size));
1432		tile[7] = (TILE_SPLIT(split_equal_to_row_size));
1433		tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1434			   PIPE_CONFIG(ADDR_SURF_P2));
1435		tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1436			   PIPE_CONFIG(ADDR_SURF_P2) |
1437			   MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
1438		tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1439			    PIPE_CONFIG(ADDR_SURF_P2) |
1440			    MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1441			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1442		tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1443			    PIPE_CONFIG(ADDR_SURF_P2) |
1444			    MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1445			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1446		tile[12] = (TILE_SPLIT(split_equal_to_row_size));
1447		tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1448			    PIPE_CONFIG(ADDR_SURF_P2) |
1449			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1450		tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1451			    PIPE_CONFIG(ADDR_SURF_P2) |
1452			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1453			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1454		tile[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1455			    PIPE_CONFIG(ADDR_SURF_P2) |
1456			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1457			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1458		tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1459			    PIPE_CONFIG(ADDR_SURF_P2) |
1460			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1461			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1462		tile[17] = (TILE_SPLIT(split_equal_to_row_size));
1463		tile[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1464			    PIPE_CONFIG(ADDR_SURF_P2) |
1465			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1466			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1467		tile[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1468			    PIPE_CONFIG(ADDR_SURF_P2) |
1469			    MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING));
1470		tile[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1471			    PIPE_CONFIG(ADDR_SURF_P2) |
1472			    MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1473			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1474		tile[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1475			    PIPE_CONFIG(ADDR_SURF_P2) |
1476			    MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1477			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1478		tile[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1479			    PIPE_CONFIG(ADDR_SURF_P2) |
1480			    MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1481			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1482		tile[23] = (TILE_SPLIT(split_equal_to_row_size));
1483		tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1484			    PIPE_CONFIG(ADDR_SURF_P2) |
1485			    MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1486			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1487		tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1488			    PIPE_CONFIG(ADDR_SURF_P2) |
1489			    MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1490			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1491		tile[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1492			    PIPE_CONFIG(ADDR_SURF_P2) |
1493			    MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1494			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1495		tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1496			    PIPE_CONFIG(ADDR_SURF_P2) |
1497			    MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
1498		tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1499			    PIPE_CONFIG(ADDR_SURF_P2) |
1500			    MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1501			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1502		tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1503			    PIPE_CONFIG(ADDR_SURF_P2) |
1504			    MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1505			    SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1506		tile[30] = (TILE_SPLIT(split_equal_to_row_size));
1507
1508		macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1509				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1510				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1511				NUM_BANKS(ADDR_SURF_8_BANK));
1512		macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1513				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1514				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1515				NUM_BANKS(ADDR_SURF_8_BANK));
1516		macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1517				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1518				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1519				NUM_BANKS(ADDR_SURF_8_BANK));
1520		macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1521				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1522				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1523				NUM_BANKS(ADDR_SURF_8_BANK));
1524		macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1525				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1526				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1527				NUM_BANKS(ADDR_SURF_8_BANK));
1528		macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1529				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1530				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1531				NUM_BANKS(ADDR_SURF_8_BANK));
1532		macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1533				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1534				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1535				NUM_BANKS(ADDR_SURF_8_BANK));
1536		macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1537				BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1538				MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1539				NUM_BANKS(ADDR_SURF_16_BANK));
1540		macrotile[9] = (BANK_WIDTH(ADDR_SURF_

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