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/arch/alpha/kernel/sys_sable.c

https://gitlab.com/vogoplayer-tools/xz0032-linux
C | 652 lines | 390 code | 65 blank | 197 comment | 24 complexity | e32a29024ab2d51ae382bc48949db3e7 MD5 | raw file
  1/*
  2 *	linux/arch/alpha/kernel/sys_sable.c
  3 *
  4 *	Copyright (C) 1995 David A Rusling
  5 *	Copyright (C) 1996 Jay A Estabrook
  6 *	Copyright (C) 1998, 1999 Richard Henderson
  7 *
  8 * Code supporting the Sable, Sable-Gamma, and Lynx systems.
  9 */
 10
 11#include <linux/kernel.h>
 12#include <linux/types.h>
 13#include <linux/mm.h>
 14#include <linux/sched.h>
 15#include <linux/pci.h>
 16#include <linux/init.h>
 17
 18#include <asm/ptrace.h>
 19#include <asm/system.h>
 20#include <asm/dma.h>
 21#include <asm/irq.h>
 22#include <asm/mmu_context.h>
 23#include <asm/io.h>
 24#include <asm/pgtable.h>
 25#include <asm/core_t2.h>
 26#include <asm/tlbflush.h>
 27
 28#include "proto.h"
 29#include "irq_impl.h"
 30#include "pci_impl.h"
 31#include "machvec_impl.h"
 32
 33DEFINE_SPINLOCK(sable_lynx_irq_lock);
 34
 35typedef struct irq_swizzle_struct
 36{
 37	char irq_to_mask[64];
 38	char mask_to_irq[64];
 39
 40	/* Note mask bit is true for DISABLED irqs.  */
 41	unsigned long shadow_mask;
 42
 43	void (*update_irq_hw)(unsigned long bit, unsigned long mask);
 44	void (*ack_irq_hw)(unsigned long bit);
 45
 46} irq_swizzle_t;
 47
 48static irq_swizzle_t *sable_lynx_irq_swizzle;
 49
 50static void sable_lynx_init_irq(int nr_of_irqs);
 51
 52#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_SABLE)
 53
 54/***********************************************************************/
 55/*
 56 *   For SABLE, which is really baroque, we manage 40 IRQ's, but the
 57 *   hardware really only supports 24, not via normal ISA PIC,
 58 *   but cascaded custom 8259's, etc.
 59 *	 0-7  (char at 536)
 60 *	 8-15 (char at 53a)
 61 *	16-23 (char at 53c)
 62 *
 63 * Summary Registers (536/53a/53c):
 64 *
 65 * Bit      Meaning               Kernel IRQ
 66 *------------------------------------------
 67 * 0        PCI slot 0			34
 68 * 1        NCR810 (builtin)		33
 69 * 2        TULIP (builtin)		32
 70 * 3        mouse			12
 71 * 4        PCI slot 1			35
 72 * 5        PCI slot 2			36
 73 * 6        keyboard			1
 74 * 7        floppy			6
 75 * 8        COM2			3
 76 * 9        parallel port		7
 77 *10        EISA irq 3			-
 78 *11        EISA irq 4			-
 79 *12        EISA irq 5			5
 80 *13        EISA irq 6			-
 81 *14        EISA irq 7			-
 82 *15        COM1			4
 83 *16        EISA irq 9			9
 84 *17        EISA irq 10			10
 85 *18        EISA irq 11			11
 86 *19        EISA irq 12			-
 87 *20        EISA irq 13			-
 88 *21        EISA irq 14			14
 89 *22        NC				15
 90 *23        IIC				-
 91 */
 92
 93static void
 94sable_update_irq_hw(unsigned long bit, unsigned long mask)
 95{
 96	int port = 0x537;
 97
 98	if (bit >= 16) {
 99		port = 0x53d;
100		mask >>= 16;
101	} else if (bit >= 8) {
102		port = 0x53b;
103		mask >>= 8;
104	}
105
106	outb(mask, port);
107}
108
109static void
110sable_ack_irq_hw(unsigned long bit)
111{
112	int port, val1, val2;
113
114	if (bit >= 16) {
115		port = 0x53c;
116		val1 = 0xE0 | (bit - 16);
117		val2 = 0xE0 | 4;
118	} else if (bit >= 8) {
119		port = 0x53a;
120		val1 = 0xE0 | (bit - 8);
121		val2 = 0xE0 | 3;
122	} else {
123		port = 0x536;
124		val1 = 0xE0 | (bit - 0);
125		val2 = 0xE0 | 1;
126	}
127
128	outb(val1, port);	/* ack the slave */
129	outb(val2, 0x534);	/* ack the master */
130}
131
132static irq_swizzle_t sable_irq_swizzle = {
133	{
134		-1,  6, -1,  8, 15, 12,  7,  9,	/* pseudo PIC  0-7  */
135		-1, 16, 17, 18,  3, -1, 21, 22,	/* pseudo PIC  8-15 */
136		-1, -1, -1, -1, -1, -1, -1, -1,	/* pseudo EISA 0-7  */
137		-1, -1, -1, -1, -1, -1, -1, -1,	/* pseudo EISA 8-15  */
138		 2,  1,  0,  4,  5, -1, -1, -1,	/* pseudo PCI */
139		-1, -1, -1, -1, -1, -1, -1, -1,	/*  */
140		-1, -1, -1, -1, -1, -1, -1, -1,	/*  */
141		-1, -1, -1, -1, -1, -1, -1, -1 	/*  */
142	},
143	{
144		34, 33, 32, 12, 35, 36,  1,  6,	/* mask 0-7  */
145		 3,  7, -1, -1,  5, -1, -1,  4,	/* mask 8-15  */
146		 9, 10, 11, -1, -1, 14, 15, -1,	/* mask 16-23  */
147		-1, -1, -1, -1, -1, -1, -1, -1,	/*  */
148		-1, -1, -1, -1, -1, -1, -1, -1,	/*  */
149		-1, -1, -1, -1, -1, -1, -1, -1,	/*  */
150		-1, -1, -1, -1, -1, -1, -1, -1,	/*  */
151		-1, -1, -1, -1, -1, -1, -1, -1	/*  */
152	},
153	-1,
154	sable_update_irq_hw,
155	sable_ack_irq_hw
156};
157
158static void __init
159sable_init_irq(void)
160{
161	outb(-1, 0x537);	/* slave 0 */
162	outb(-1, 0x53b);	/* slave 1 */
163	outb(-1, 0x53d);	/* slave 2 */
164	outb(0x44, 0x535);	/* enable cascades in master */
165
166	sable_lynx_irq_swizzle = &sable_irq_swizzle;
167	sable_lynx_init_irq(40);
168}
169
170/*
171 * PCI Fixup configuration for ALPHA SABLE (2100).
172 *
173 * The device to slot mapping looks like:
174 *
175 * Slot     Device
176 *  0       TULIP
177 *  1       SCSI
178 *  2       PCI-EISA bridge
179 *  3       none
180 *  4       none
181 *  5       none
182 *  6       PCI on board slot 0
183 *  7       PCI on board slot 1
184 *  8       PCI on board slot 2
185 *   
186 *
187 * This two layered interrupt approach means that we allocate IRQ 16 and 
188 * above for PCI interrupts.  The IRQ relates to which bit the interrupt
189 * comes in on.  This makes interrupt processing much easier.
190 */
191/*
192 * NOTE: the IRQ assignments below are arbitrary, but need to be consistent
193 * with the values in the irq swizzling tables above.
194 */
195
196static int __init
197sable_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
198{
199	static char irq_tab[9][5] __initdata = {
200		/*INT    INTA   INTB   INTC   INTD */
201		{ 32+0,  32+0,  32+0,  32+0,  32+0},  /* IdSel 0,  TULIP  */
202		{ 32+1,  32+1,  32+1,  32+1,  32+1},  /* IdSel 1,  SCSI   */
203		{   -1,    -1,    -1,    -1,    -1},  /* IdSel 2,  SIO   */
204		{   -1,    -1,    -1,    -1,    -1},  /* IdSel 3,  none   */
205		{   -1,    -1,    -1,    -1,    -1},  /* IdSel 4,  none   */
206		{   -1,    -1,    -1,    -1,    -1},  /* IdSel 5,  none   */
207		{ 32+2,  32+2,  32+2,  32+2,  32+2},  /* IdSel 6,  slot 0 */
208		{ 32+3,  32+3,  32+3,  32+3,  32+3},  /* IdSel 7,  slot 1 */
209		{ 32+4,  32+4,  32+4,  32+4,  32+4}   /* IdSel 8,  slot 2 */
210	};
211	long min_idsel = 0, max_idsel = 8, irqs_per_slot = 5;
212	return COMMON_TABLE_LOOKUP;
213}
214#endif /* defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_SABLE) */
215
216#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_LYNX)
217
218/***********************************************************************/
219/* LYNX hardware specifics
220 */
221/*
222 *   For LYNX, which is also baroque, we manage 64 IRQs, via a custom IC.
223 *
224 * Bit      Meaning               Kernel IRQ
225 *------------------------------------------
226 * 0        
227 * 1        
228 * 2        
229 * 3        mouse			12
230 * 4        
231 * 5        
232 * 6        keyboard			1
233 * 7        floppy			6
234 * 8        COM2			3
235 * 9        parallel port		7
236 *10        EISA irq 3			-
237 *11        EISA irq 4			-
238 *12        EISA irq 5			5
239 *13        EISA irq 6			-
240 *14        EISA irq 7			-
241 *15        COM1			4
242 *16        EISA irq 9			9
243 *17        EISA irq 10			10
244 *18        EISA irq 11			11
245 *19        EISA irq 12			-
246 *20        
247 *21        EISA irq 14			14
248 *22        EISA irq 15			15
249 *23        IIC				-
250 *24        VGA (builtin)               -
251 *25
252 *26
253 *27
254 *28        NCR810 (builtin)		28
255 *29
256 *30
257 *31
258 *32        PCI 0 slot 4 A primary bus  32
259 *33        PCI 0 slot 4 B primary bus  33
260 *34        PCI 0 slot 4 C primary bus  34
261 *35        PCI 0 slot 4 D primary bus
262 *36        PCI 0 slot 5 A primary bus
263 *37        PCI 0 slot 5 B primary bus
264 *38        PCI 0 slot 5 C primary bus
265 *39        PCI 0 slot 5 D primary bus
266 *40        PCI 0 slot 6 A primary bus
267 *41        PCI 0 slot 6 B primary bus
268 *42        PCI 0 slot 6 C primary bus
269 *43        PCI 0 slot 6 D primary bus
270 *44        PCI 0 slot 7 A primary bus
271 *45        PCI 0 slot 7 B primary bus
272 *46        PCI 0 slot 7 C primary bus
273 *47        PCI 0 slot 7 D primary bus
274 *48        PCI 0 slot 0 A secondary bus
275 *49        PCI 0 slot 0 B secondary bus
276 *50        PCI 0 slot 0 C secondary bus
277 *51        PCI 0 slot 0 D secondary bus
278 *52        PCI 0 slot 1 A secondary bus
279 *53        PCI 0 slot 1 B secondary bus
280 *54        PCI 0 slot 1 C secondary bus
281 *55        PCI 0 slot 1 D secondary bus
282 *56        PCI 0 slot 2 A secondary bus
283 *57        PCI 0 slot 2 B secondary bus
284 *58        PCI 0 slot 2 C secondary bus
285 *59        PCI 0 slot 2 D secondary bus
286 *60        PCI 0 slot 3 A secondary bus
287 *61        PCI 0 slot 3 B secondary bus
288 *62        PCI 0 slot 3 C secondary bus
289 *63        PCI 0 slot 3 D secondary bus
290 */
291
292static void
293lynx_update_irq_hw(unsigned long bit, unsigned long mask)
294{
295	/*
296	 * Write the AIR register on the T3/T4 with the
297	 * address of the IC mask register (offset 0x40)
298	 */
299	*(vulp)T2_AIR = 0x40;
300	mb();
301	*(vulp)T2_AIR; /* re-read to force write */
302	mb();
303	*(vulp)T2_DIR = mask;    
304	mb();
305	mb();
306}
307
308static void
309lynx_ack_irq_hw(unsigned long bit)
310{
311	*(vulp)T2_VAR = (u_long) bit;
312	mb();
313	mb();
314}
315
316static irq_swizzle_t lynx_irq_swizzle = {
317	{ /* irq_to_mask */
318		-1,  6, -1,  8, 15, 12,  7,  9,	/* pseudo PIC  0-7  */
319		-1, 16, 17, 18,  3, -1, 21, 22,	/* pseudo PIC  8-15 */
320		-1, -1, -1, -1, -1, -1, -1, -1,	/* pseudo */
321		-1, -1, -1, -1, 28, -1, -1, -1,	/* pseudo */
322		32, 33, 34, 35, 36, 37, 38, 39,	/* mask 32-39 */
323		40, 41, 42, 43, 44, 45, 46, 47,	/* mask 40-47 */
324		48, 49, 50, 51, 52, 53, 54, 55,	/* mask 48-55 */
325		56, 57, 58, 59, 60, 61, 62, 63	/* mask 56-63 */
326	},
327	{ /* mask_to_irq */
328		-1, -1, -1, 12, -1, -1,  1,  6,	/* mask 0-7   */
329		 3,  7, -1, -1,  5, -1, -1,  4,	/* mask 8-15  */
330		 9, 10, 11, -1, -1, 14, 15, -1,	/* mask 16-23 */
331		-1, -1, -1, -1, 28, -1, -1, -1,	/* mask 24-31 */
332		32, 33, 34, 35, 36, 37, 38, 39,	/* mask 32-39 */
333		40, 41, 42, 43, 44, 45, 46, 47,	/* mask 40-47 */
334		48, 49, 50, 51, 52, 53, 54, 55,	/* mask 48-55 */
335		56, 57, 58, 59, 60, 61, 62, 63	/* mask 56-63 */
336	},
337	-1,
338	lynx_update_irq_hw,
339	lynx_ack_irq_hw
340};
341
342static void __init
343lynx_init_irq(void)
344{
345	sable_lynx_irq_swizzle = &lynx_irq_swizzle;
346	sable_lynx_init_irq(64);
347}
348
349/*
350 * PCI Fixup configuration for ALPHA LYNX (2100A)
351 *
352 * The device to slot mapping looks like:
353 *
354 * Slot     Device
355 *  0       none
356 *  1       none
357 *  2       PCI-EISA bridge
358 *  3       PCI-PCI bridge
359 *  4       NCR 810 (Demi-Lynx only)
360 *  5       none
361 *  6       PCI on board slot 4
362 *  7       PCI on board slot 5
363 *  8       PCI on board slot 6
364 *  9       PCI on board slot 7
365 *
366 * And behind the PPB we have:
367 *
368 * 11       PCI on board slot 0
369 * 12       PCI on board slot 1
370 * 13       PCI on board slot 2
371 * 14       PCI on board slot 3
372 */
373/*
374 * NOTE: the IRQ assignments below are arbitrary, but need to be consistent
375 * with the values in the irq swizzling tables above.
376 */
377
378static int __init
379lynx_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
380{
381	static char irq_tab[19][5] __initdata = {
382		/*INT    INTA   INTB   INTC   INTD */
383		{   -1,    -1,    -1,    -1,    -1},  /* IdSel 13,  PCEB   */
384		{   -1,    -1,    -1,    -1,    -1},  /* IdSel 14,  PPB    */
385		{   28,    28,    28,    28,    28},  /* IdSel 15,  NCR demi */
386		{   -1,    -1,    -1,    -1,    -1},  /* IdSel 16,  none   */
387		{   32,    32,    33,    34,    35},  /* IdSel 17,  slot 4 */
388		{   36,    36,    37,    38,    39},  /* IdSel 18,  slot 5 */
389		{   40,    40,    41,    42,    43},  /* IdSel 19,  slot 6 */
390		{   44,    44,    45,    46,    47},  /* IdSel 20,  slot 7 */
391		{   -1,    -1,    -1,    -1,    -1},  /* IdSel 22,  none   */
392		/* The following are actually behind the PPB. */
393		{   -1,    -1,    -1,    -1,    -1},  /* IdSel 16   none */
394		{   28,    28,    28,    28,    28},  /* IdSel 17   NCR lynx */
395		{   -1,    -1,    -1,    -1,    -1},  /* IdSel 18   none */
396		{   -1,    -1,    -1,    -1,    -1},  /* IdSel 19   none */
397		{   -1,    -1,    -1,    -1,    -1},  /* IdSel 20   none */
398		{   -1,    -1,    -1,    -1,    -1},  /* IdSel 21   none */
399		{   48,    48,    49,    50,    51},  /* IdSel 22   slot 0 */
400		{   52,    52,    53,    54,    55},  /* IdSel 23   slot 1 */
401		{   56,    56,    57,    58,    59},  /* IdSel 24   slot 2 */
402		{   60,    60,    61,    62,    63}   /* IdSel 25   slot 3 */
403	};
404	const long min_idsel = 2, max_idsel = 20, irqs_per_slot = 5;
405	return COMMON_TABLE_LOOKUP;
406}
407
408static u8 __init
409lynx_swizzle(struct pci_dev *dev, u8 *pinp)
410{
411	int slot, pin = *pinp;
412
413	if (dev->bus->number == 0) {
414		slot = PCI_SLOT(dev->devfn);
415	}
416	/* Check for the built-in bridge */
417	else if (PCI_SLOT(dev->bus->self->devfn) == 3) {
418		slot = PCI_SLOT(dev->devfn) + 11;
419	}
420	else
421	{
422		/* Must be a card-based bridge.  */
423		do {
424			if (PCI_SLOT(dev->bus->self->devfn) == 3) {
425				slot = PCI_SLOT(dev->devfn) + 11;
426				break;
427			}
428			pin = pci_swizzle_interrupt_pin(dev, pin);
429
430			/* Move up the chain of bridges.  */
431			dev = dev->bus->self;
432			/* Slot of the next bridge.  */
433			slot = PCI_SLOT(dev->devfn);
434		} while (dev->bus->self);
435	}
436	*pinp = pin;
437	return slot;
438}
439
440#endif /* defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_LYNX) */
441
442/***********************************************************************/
443/* GENERIC irq routines */
444
445static inline void
446sable_lynx_enable_irq(unsigned int irq)
447{
448	unsigned long bit, mask;
449
450	bit = sable_lynx_irq_swizzle->irq_to_mask[irq];
451	spin_lock(&sable_lynx_irq_lock);
452	mask = sable_lynx_irq_swizzle->shadow_mask &= ~(1UL << bit);
453	sable_lynx_irq_swizzle->update_irq_hw(bit, mask);
454	spin_unlock(&sable_lynx_irq_lock);
455#if 0
456	printk("%s: mask 0x%lx bit 0x%lx irq 0x%x\n",
457	       __func__, mask, bit, irq);
458#endif
459}
460
461static void
462sable_lynx_disable_irq(unsigned int irq)
463{
464	unsigned long bit, mask;
465
466	bit = sable_lynx_irq_swizzle->irq_to_mask[irq];
467	spin_lock(&sable_lynx_irq_lock);
468	mask = sable_lynx_irq_swizzle->shadow_mask |= 1UL << bit;
469	sable_lynx_irq_swizzle->update_irq_hw(bit, mask);
470	spin_unlock(&sable_lynx_irq_lock);
471#if 0
472	printk("%s: mask 0x%lx bit 0x%lx irq 0x%x\n",
473	       __func__, mask, bit, irq);
474#endif
475}
476
477static unsigned int
478sable_lynx_startup_irq(unsigned int irq)
479{
480	sable_lynx_enable_irq(irq);
481	return 0;
482}
483
484static void
485sable_lynx_end_irq(unsigned int irq)
486{
487	if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
488		sable_lynx_enable_irq(irq);
489}
490
491static void
492sable_lynx_mask_and_ack_irq(unsigned int irq)
493{
494	unsigned long bit, mask;
495
496	bit = sable_lynx_irq_swizzle->irq_to_mask[irq];
497	spin_lock(&sable_lynx_irq_lock);
498	mask = sable_lynx_irq_swizzle->shadow_mask |= 1UL << bit;
499	sable_lynx_irq_swizzle->update_irq_hw(bit, mask);
500	sable_lynx_irq_swizzle->ack_irq_hw(bit);
501	spin_unlock(&sable_lynx_irq_lock);
502}
503
504static struct irq_chip sable_lynx_irq_type = {
505	.name		= "SABLE/LYNX",
506	.startup	= sable_lynx_startup_irq,
507	.shutdown	= sable_lynx_disable_irq,
508	.enable		= sable_lynx_enable_irq,
509	.disable	= sable_lynx_disable_irq,
510	.ack		= sable_lynx_mask_and_ack_irq,
511	.end		= sable_lynx_end_irq,
512};
513
514static void 
515sable_lynx_srm_device_interrupt(unsigned long vector)
516{
517	/* Note that the vector reported by the SRM PALcode corresponds
518	   to the interrupt mask bits, but we have to manage via the
519	   so-called legacy IRQs for many common devices.  */
520
521	int bit, irq;
522
523	bit = (vector - 0x800) >> 4;
524	irq = sable_lynx_irq_swizzle->mask_to_irq[bit];
525#if 0
526	printk("%s: vector 0x%lx bit 0x%x irq 0x%x\n",
527	       __func__, vector, bit, irq);
528#endif
529	handle_irq(irq);
530}
531
532static void __init
533sable_lynx_init_irq(int nr_of_irqs)
534{
535	long i;
536
537	for (i = 0; i < nr_of_irqs; ++i) {
538		irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL;
539		irq_desc[i].chip = &sable_lynx_irq_type;
540	}
541
542	common_init_isa_dma();
543}
544
545static void __init
546sable_lynx_init_pci(void)
547{
548	common_init_pci();
549}
550
551/*****************************************************************/
552/*
553 * The System Vectors
554 *
555 * In order that T2_HAE_ADDRESS should be a constant, we play
556 * these games with GAMMA_BIAS.
557 */
558
559#if defined(CONFIG_ALPHA_GENERIC) || \
560    (defined(CONFIG_ALPHA_SABLE) && !defined(CONFIG_ALPHA_GAMMA))
561#undef GAMMA_BIAS
562#define GAMMA_BIAS 0
563struct alpha_machine_vector sable_mv __initmv = {
564	.vector_name		= "Sable",
565	DO_EV4_MMU,
566	DO_DEFAULT_RTC,
567	DO_T2_IO,
568	.machine_check		= t2_machine_check,
569	.max_isa_dma_address	= ALPHA_SABLE_MAX_ISA_DMA_ADDRESS,
570	.min_io_address		= EISA_DEFAULT_IO_BASE,
571	.min_mem_address	= T2_DEFAULT_MEM_BASE,
572
573	.nr_irqs		= 40,
574	.device_interrupt	= sable_lynx_srm_device_interrupt,
575
576	.init_arch		= t2_init_arch,
577	.init_irq		= sable_init_irq,
578	.init_rtc		= common_init_rtc,
579	.init_pci		= sable_lynx_init_pci,
580	.kill_arch		= t2_kill_arch,
581	.pci_map_irq		= sable_map_irq,
582	.pci_swizzle		= common_swizzle,
583
584	.sys = { .t2 = {
585	    .gamma_bias		= 0
586	} }
587};
588ALIAS_MV(sable)
589#endif /* GENERIC || (SABLE && !GAMMA) */
590
591#if defined(CONFIG_ALPHA_GENERIC) || \
592    (defined(CONFIG_ALPHA_SABLE) && defined(CONFIG_ALPHA_GAMMA))
593#undef GAMMA_BIAS
594#define GAMMA_BIAS _GAMMA_BIAS
595struct alpha_machine_vector sable_gamma_mv __initmv = {
596	.vector_name		= "Sable-Gamma",
597	DO_EV5_MMU,
598	DO_DEFAULT_RTC,
599	DO_T2_IO,
600	.machine_check		= t2_machine_check,
601	.max_isa_dma_address	= ALPHA_SABLE_MAX_ISA_DMA_ADDRESS,
602	.min_io_address		= EISA_DEFAULT_IO_BASE,
603	.min_mem_address	= T2_DEFAULT_MEM_BASE,
604
605	.nr_irqs		= 40,
606	.device_interrupt	= sable_lynx_srm_device_interrupt,
607
608	.init_arch		= t2_init_arch,
609	.init_irq		= sable_init_irq,
610	.init_rtc		= common_init_rtc,
611	.init_pci		= sable_lynx_init_pci,
612	.kill_arch		= t2_kill_arch,
613	.pci_map_irq		= sable_map_irq,
614	.pci_swizzle		= common_swizzle,
615
616	.sys = { .t2 = {
617	    .gamma_bias		= _GAMMA_BIAS
618	} }
619};
620ALIAS_MV(sable_gamma)
621#endif /* GENERIC || (SABLE && GAMMA) */
622
623#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_LYNX)
624#undef GAMMA_BIAS
625#define GAMMA_BIAS _GAMMA_BIAS
626struct alpha_machine_vector lynx_mv __initmv = {
627	.vector_name		= "Lynx",
628	DO_EV4_MMU,
629	DO_DEFAULT_RTC,
630	DO_T2_IO,
631	.machine_check		= t2_machine_check,
632	.max_isa_dma_address	= ALPHA_SABLE_MAX_ISA_DMA_ADDRESS,
633	.min_io_address		= EISA_DEFAULT_IO_BASE,
634	.min_mem_address	= T2_DEFAULT_MEM_BASE,
635
636	.nr_irqs		= 64,
637	.device_interrupt	= sable_lynx_srm_device_interrupt,
638
639	.init_arch		= t2_init_arch,
640	.init_irq		= lynx_init_irq,
641	.init_rtc		= common_init_rtc,
642	.init_pci		= sable_lynx_init_pci,
643	.kill_arch		= t2_kill_arch,
644	.pci_map_irq		= lynx_map_irq,
645	.pci_swizzle		= lynx_swizzle,
646
647	.sys = { .t2 = {
648	    .gamma_bias		= _GAMMA_BIAS
649	} }
650};
651ALIAS_MV(lynx)
652#endif /* GENERIC || LYNX */