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/board/espt/lowlevel_init.S

https://gitlab.com/veo-labs/u-boot
Assembly | 319 lines | 233 code | 86 blank | 0 comment | 0 complexity | 046f00ce42b4589c219ae2df774c10e1 MD5 | raw file
  1/*
  2 * Copyright (C) 2009 Renesas Solutions Corp.
  3 * Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
  4 *
  5 * board/espt/lowlevel_init.S
  6 *
  7 * SPDX-License-Identifier:	GPL-2.0+
  8 */
  9
 10#include <config.h>
 11#include <version.h>
 12#include <asm/processor.h>
 13#include <asm/macro.h>
 14
 15	.global	lowlevel_init
 16
 17	.text
 18	.align	2
 19
 20lowlevel_init:
 21
 22	write32 WDTCSR_A, WDTCSR_D
 23
 24	write32 WDTST_A, WDTST_D
 25
 26	write32 WDTBST_A, WDTBST_D
 27
 28	write32 CCR_A, CCR_CACHE_ICI_D
 29
 30	write32 MMUCR_A, MMU_CONTROL_TI_D
 31
 32	write32 MSTPCR0_A, MSTPCR0_D
 33
 34	write32 MSTPCR1_A, MSTPCR1_D
 35
 36	write32 RAMCR_A, RAMCR_D
 37
 38	/*
 39	 * Setting infomation from
 40	 * original ESPT-GIGA bootloader register
 41	 */
 42	write32 MMSEL_A, MMSEL_D
 43
 44	/* dummy */
 45	mov.l   @r1, r2
 46	mov.l   @r1, r2
 47	synco
 48
 49    write32 BCR_A, BCR_D
 50
 51    write32 CS0BCR_A, CS0BCR_D
 52
 53    write32 CS0WCR_A, CS0WCR_D
 54
 55	/*
 56	 * DDR-SDRAM setting
 57	 */
 58
 59	/* set DDR-SDRAM dummy read */
 60	write32 MMSEL_A, MMSEL_D
 61
 62	write32 MMSEL_A, CS0_A
 63
 64	/* set DDR-SDRAM bus/endian etc */
 65	write32 MIM_U_A, MIM_U_D
 66
 67	write32 MIM_L_A, MIM_L_D0
 68
 69	write32 SDR_L_A, SDR_L_A_D0
 70
 71	write32 STR_L_A, STR_L_A_D0
 72
 73	/* DDR-SDRAM access control */
 74	write32 MIM_L_A, MIM_L_D1
 75
 76	write32 SCR_L_A, SCR_L_A_D0
 77
 78	write32 SCR_L_A, SCR_L_A_D1
 79
 80	write32 EMRS_A, EMRS_D
 81
 82	write32 MRS1_A, MRS1_D
 83
 84	write32 MIM_U_A, MIM_U_D
 85
 86	write32 MIM_L_A, MIM_L_A_D2
 87
 88	write32 SCR_L_A, SCR_L_A_D2
 89
 90	write32 SCR_L_A, SCR_L_A_D2
 91
 92	write32 MRS2_A, MRS2_D
 93
 94	/* wait 200us */
 95	wait_timer REPEAT_R3
 96
 97	/* GPIO setting */
 98	write16 PSEL0_A, PSEL0_D
 99
100	write16 PSEL1_A, PSEL1_D
101
102	write16 PSEL2_A, PSEL2_D
103
104	write16 PSEL3_A, PSEL3_D
105
106	write16 PSEL4_A, PSEL4_D
107
108	write8 PADR_A, PADR_D
109
110	write16 PACR_A, PACR_D
111
112	write8 PBDR_A, PBDR_D
113
114	write16 PBCR_A, PBCR_D
115
116	write8 PCDR_A, PCDR_D
117
118	write16 PCCR_A, PCCR_D
119
120	write8	PDDR_A, PDDR_D
121
122	write16 PDCR_A, PDCR_D
123
124	write16 PECR_A, PECR_D
125
126	write16 PFCR_A, PFCR_D
127
128	write16 PGCR_A, PGCR_D
129
130	write16 PHCR_A, PHCR_D
131
132	write16 PICR_A, PICR_D
133
134	write8 PJDR_A, PJDR_D
135
136	write16 PJCR_A, PJCR_D
137
138	/* wait 50us */
139	wait_timer REPEAT_R3
140
141	write8 PKDR_A, PKDR_D
142
143	write16 PKCR_A, PKCR_D
144
145	write16 PLCR_A, PLCR_D
146
147	write16 PMCR_A, PMCR_D
148
149	write16 PNCR_A, PNCR_D
150
151	write16 POCR_A, POCR_D
152
153
154	/* ICR0 ,ICR1 */
155	write32 ICR0_A, ICR0_D
156
157	write32 ICR1_A, ICR1_D
158
159	/* USB Host */
160	write32 USB_USBHSC_A, USB_USBHSC_D
161
162	write32 CCR_A, CCR_CACHE_D_2
163
164	rts
165	nop
166
167	.align	2
168
169/* GPIO Crontrol Register */
170PACR_A:	.long	0xFFEF0000
171PBCR_A:	.long	0xFFEF0002
172PCCR_A:	.long	0xFFEF0004
173PDCR_A:	.long	0xFFEF0006
174PECR_A:	.long	0xFFEF0008
175PFCR_A:	.long	0xFFEF000A
176PGCR_A:	.long	0xFFEF000C
177PHCR_A:	.long	0xFFEF000E
178PICR_A:	.long	0xFFEF0010
179PJCR_A:	.long	0xFFEF0012
180PKCR_A:	.long	0xFFEF0014
181PLCR_A:	.long	0xFFEF0016
182PMCR_A:	.long	0xFFEF0018
183PNCR_A:	.long	0xFFEF001A
184POCR_A:	.long	0xFFEF001C
185
186/* GPIO Data Register */
187PADR_A:	.long	0xFFEF0020
188PBDR_A:	.long	0xFFEF0022
189PCDR_A:	.long	0xFFEF0024
190PDDR_A:	.long	0xFFEF0026
191PJDR_A:	.long	0xFFEF0032
192PKDR_A:	.long	0xFFEF0034
193
194/* GPIO Set data */
195PADR_D:	.long	0x00000000
196PACR_D:	.word 	0x1400
197.align 2
198PBDR_D:	.long	0x00000000
199PBCR_D:	.word	0x555A
200.align 2
201PCDR_D:	.long	0x00000000
202PCCR_D:	.word	0x5555
203.align 2
204PDDR_D:	.long	0x00000000
205PDCR_D:	.word	0x0155
206PECR_D:	.word	0x0000
207PFCR_D:	.word	0x0000
208PGCR_D:	.word	0x0000
209PHCR_D:	.word	0x0000
210PICR_D:	.word	0x0800
211PJDR_D:	.long	0x00000006
212PJCR_D:	.word	0x5A57
213.align 2
214PKDR_D:	.long	0x00000000
215PKCR_D:	.word	0xFFF9
216.align 2
217PLCR_D:	.word 	0xC330
218PMCR_D:	.word	0xFFFF
219PNCR_D:	.word	0x0242
220POCR_D:	.word	0x0000
221
222/* Pin Select */
223PSEL0_A:	.long	0xFFEF0070
224PSEL1_A:	.long	0xFFEF0072
225PSEL2_A:	.long	0xFFEF0074
226PSEL3_A:	.long	0xFFEF0076
227PSEL4_A:	.long	0xFFEF0078
228PSEL0_D:	.word	0x0001
229PSEL1_D:	.word	0x2400
230PSEL2_D:	.word	0x0000
231PSEL3_D:	.word	0x2421
232PSEL4_D:	.word	0x0000
233.align 2
234
235MMSEL_A:	.long	0xFE600020
236BCR_A:		.long	0xFF801000
237CS0BCR_A:	.long	0xFF802000
238CS0WCR_A:	.long	0xFF802008
239ICR0_A:		.long	0xFFD00000
240ICR1_A:		.long	0xFFD0001C
241
242MMSEL_D:	.long	0xA5A50000
243BCR_D:		.long	0x05000000
244CS0BCR_D:	.long	0x232306F0
245CS0WCR_D:	.long	0x00011104
246ICR0_D:		.long	0x80C00000
247ICR1_D:		.long	0x00020000
248
249/* RWBT Address */
250WDTST_A:	.long	0xFFCC0000
251WDTCSR_A:	.long	0xFFCC0004
252WDTBST_A:	.long	0xFFCC0008
253/* RWBT Data */
254WDTST_D:	.long	0x5A000FFF
255WDTCSR_D:	.long	0xA5000000
256WDTBST_D:	.long	0x55000000
257
258/* Cache Address */
259CCR_A:		.long	0xFF00001C
260MMUCR_A:	.long	0xFF000010
261RAMCR_A:	.long	0xFF000074
262
263/* Cache Data */
264CCR_CACHE_ICI_D:.long	0x00000800
265CCR_CACHE_D_2:	.long	0x00000103
266MMU_CONTROL_TI_D:.long	0x00000004
267RAMCR_D:	.long	0x00000200
268
269/* Low power mode control Address */
270MSTPCR0_A:	.long	0xFFC80030
271MSTPCR1_A:	.long	0xFFC80038
272/* Low power mode control Data */
273MSTPCR0_D:	.long	0x00000000
274MSTPCR1_D:	.long	0x00000000
275
276REPEAT0_R3:	.long	0x00002000
277REPEAT_R3:	.long	0x00000200
278CS0_A:		.long	0xA8000000
279
280MIM_U_A:	.long	0xFE800008
281MIM_L_A:	.long	0xFE80000C
282SCR_U_A:	.long	0xFE800010
283SCR_L_A:	.long	0xFE800014
284STR_U_A:	.long	0xFE800018
285STR_L_A:	.long	0xFE80001C
286SDR_U_A:	.long	0xFE800030
287SDR_L_A:	.long	0xFE800034
288EMRS_A:		.long	0xFE902000
289MRS1_A:		.long	0xFE900B08
290MRS2_A:		.long	0xFE900308
291
292MIM_U_D:	.long	0x00000000
293MIM_L_D0:	.long	0x04100008
294MIM_L_D1:	.long	0x02EE0009
295MIM_L_D2:	.long	0x02EE0209
296
297SDR_L_A_D0:	.long	0x00000300
298STR_L_A_D0:	.long	0x00010040
299MIM_L_A_D1:	.long	0x04100009
300SCR_L_A_D0:	.long 	0x00000003
301SCR_L_A_D1:	.long 	0x00000002
302MIM_L_A_D2:	.long	0x04100209
303SCR_L_A_D2:	.long	0x00000004
304
305SCR_L_NORMAL:	.long	0x00000000
306SCR_L_NOP:		.long	0x00000001
307SCR_L_PALL:		.long	0x00000002
308SCR_L_CKE_EN:	.long	0x00000003
309SCR_L_CBR:		.long	0x00000004
310
311STR_L_D:	.long	0x000F3980
312SDR_L_D:	.long	0x00000400
313EMRS_D:		.long	0x00000000
314MRS1_D:		.long	0x00000000
315MRS2_D:		.long	0x00000000
316
317/* USB */
318USB_USBHSC_A:	.long	0xFFEC80F0
319USB_USBHSC_D:	.long	0x00000000