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/drivers/gpu/drm/amd/amdgpu/kv_dpm.c

https://gitlab.com/sunny256/linux
C | 3348 lines | 2791 code | 516 blank | 41 comment | 492 complexity | 2a47ad81d9880f45bc499c8a8b3a5140 MD5 | raw file

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   1/*
   2 * Copyright 2013 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 */
  23
  24#include <drm/drmP.h>
  25#include "amdgpu.h"
  26#include "amdgpu_pm.h"
  27#include "cikd.h"
  28#include "atom.h"
  29#include "amdgpu_atombios.h"
  30#include "amdgpu_dpm.h"
  31#include "kv_dpm.h"
  32#include "gfx_v7_0.h"
  33#include <linux/seq_file.h>
  34
  35#include "smu/smu_7_0_0_d.h"
  36#include "smu/smu_7_0_0_sh_mask.h"
  37
  38#include "gca/gfx_7_2_d.h"
  39#include "gca/gfx_7_2_sh_mask.h"
  40
  41#define KV_MAX_DEEPSLEEP_DIVIDER_ID     5
  42#define KV_MINIMUM_ENGINE_CLOCK         800
  43#define SMC_RAM_END                     0x40000
  44
  45static void kv_dpm_set_irq_funcs(struct amdgpu_device *adev);
  46static int kv_enable_nb_dpm(struct amdgpu_device *adev,
  47			    bool enable);
  48static void kv_init_graphics_levels(struct amdgpu_device *adev);
  49static int kv_calculate_ds_divider(struct amdgpu_device *adev);
  50static int kv_calculate_nbps_level_settings(struct amdgpu_device *adev);
  51static int kv_calculate_dpm_settings(struct amdgpu_device *adev);
  52static void kv_enable_new_levels(struct amdgpu_device *adev);
  53static void kv_program_nbps_index_settings(struct amdgpu_device *adev,
  54					   struct amdgpu_ps *new_rps);
  55static int kv_set_enabled_level(struct amdgpu_device *adev, u32 level);
  56static int kv_set_enabled_levels(struct amdgpu_device *adev);
  57static int kv_force_dpm_highest(struct amdgpu_device *adev);
  58static int kv_force_dpm_lowest(struct amdgpu_device *adev);
  59static void kv_apply_state_adjust_rules(struct amdgpu_device *adev,
  60					struct amdgpu_ps *new_rps,
  61					struct amdgpu_ps *old_rps);
  62static int kv_set_thermal_temperature_range(struct amdgpu_device *adev,
  63					    int min_temp, int max_temp);
  64static int kv_init_fps_limits(struct amdgpu_device *adev);
  65
  66static void kv_dpm_powergate_uvd(void *handle, bool gate);
  67static void kv_dpm_powergate_vce(struct amdgpu_device *adev, bool gate);
  68static void kv_dpm_powergate_samu(struct amdgpu_device *adev, bool gate);
  69static void kv_dpm_powergate_acp(struct amdgpu_device *adev, bool gate);
  70
  71
  72static u32 kv_convert_vid2_to_vid7(struct amdgpu_device *adev,
  73				   struct sumo_vid_mapping_table *vid_mapping_table,
  74				   u32 vid_2bit)
  75{
  76	struct amdgpu_clock_voltage_dependency_table *vddc_sclk_table =
  77		&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
  78	u32 i;
  79
  80	if (vddc_sclk_table && vddc_sclk_table->count) {
  81		if (vid_2bit < vddc_sclk_table->count)
  82			return vddc_sclk_table->entries[vid_2bit].v;
  83		else
  84			return vddc_sclk_table->entries[vddc_sclk_table->count - 1].v;
  85	} else {
  86		for (i = 0; i < vid_mapping_table->num_entries; i++) {
  87			if (vid_mapping_table->entries[i].vid_2bit == vid_2bit)
  88				return vid_mapping_table->entries[i].vid_7bit;
  89		}
  90		return vid_mapping_table->entries[vid_mapping_table->num_entries - 1].vid_7bit;
  91	}
  92}
  93
  94static u32 kv_convert_vid7_to_vid2(struct amdgpu_device *adev,
  95				   struct sumo_vid_mapping_table *vid_mapping_table,
  96				   u32 vid_7bit)
  97{
  98	struct amdgpu_clock_voltage_dependency_table *vddc_sclk_table =
  99		&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
 100	u32 i;
 101
 102	if (vddc_sclk_table && vddc_sclk_table->count) {
 103		for (i = 0; i < vddc_sclk_table->count; i++) {
 104			if (vddc_sclk_table->entries[i].v == vid_7bit)
 105				return i;
 106		}
 107		return vddc_sclk_table->count - 1;
 108	} else {
 109		for (i = 0; i < vid_mapping_table->num_entries; i++) {
 110			if (vid_mapping_table->entries[i].vid_7bit == vid_7bit)
 111				return vid_mapping_table->entries[i].vid_2bit;
 112		}
 113
 114		return vid_mapping_table->entries[vid_mapping_table->num_entries - 1].vid_2bit;
 115	}
 116}
 117
 118static void sumo_take_smu_control(struct amdgpu_device *adev, bool enable)
 119{
 120/* This bit selects who handles display phy powergating.
 121 * Clear the bit to let atom handle it.
 122 * Set it to let the driver handle it.
 123 * For now we just let atom handle it.
 124 */
 125#if 0
 126	u32 v = RREG32(mmDOUT_SCRATCH3);
 127
 128	if (enable)
 129		v |= 0x4;
 130	else
 131		v &= 0xFFFFFFFB;
 132
 133	WREG32(mmDOUT_SCRATCH3, v);
 134#endif
 135}
 136
 137static void sumo_construct_sclk_voltage_mapping_table(struct amdgpu_device *adev,
 138						      struct sumo_sclk_voltage_mapping_table *sclk_voltage_mapping_table,
 139						      ATOM_AVAILABLE_SCLK_LIST *table)
 140{
 141	u32 i;
 142	u32 n = 0;
 143	u32 prev_sclk = 0;
 144
 145	for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++) {
 146		if (table[i].ulSupportedSCLK > prev_sclk) {
 147			sclk_voltage_mapping_table->entries[n].sclk_frequency =
 148				table[i].ulSupportedSCLK;
 149			sclk_voltage_mapping_table->entries[n].vid_2bit =
 150				table[i].usVoltageIndex;
 151			prev_sclk = table[i].ulSupportedSCLK;
 152			n++;
 153		}
 154	}
 155
 156	sclk_voltage_mapping_table->num_max_dpm_entries = n;
 157}
 158
 159static void sumo_construct_vid_mapping_table(struct amdgpu_device *adev,
 160					     struct sumo_vid_mapping_table *vid_mapping_table,
 161					     ATOM_AVAILABLE_SCLK_LIST *table)
 162{
 163	u32 i, j;
 164
 165	for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++) {
 166		if (table[i].ulSupportedSCLK != 0) {
 167			vid_mapping_table->entries[table[i].usVoltageIndex].vid_7bit =
 168				table[i].usVoltageID;
 169			vid_mapping_table->entries[table[i].usVoltageIndex].vid_2bit =
 170				table[i].usVoltageIndex;
 171		}
 172	}
 173
 174	for (i = 0; i < SUMO_MAX_NUMBER_VOLTAGES; i++) {
 175		if (vid_mapping_table->entries[i].vid_7bit == 0) {
 176			for (j = i + 1; j < SUMO_MAX_NUMBER_VOLTAGES; j++) {
 177				if (vid_mapping_table->entries[j].vid_7bit != 0) {
 178					vid_mapping_table->entries[i] =
 179						vid_mapping_table->entries[j];
 180					vid_mapping_table->entries[j].vid_7bit = 0;
 181					break;
 182				}
 183			}
 184
 185			if (j == SUMO_MAX_NUMBER_VOLTAGES)
 186				break;
 187		}
 188	}
 189
 190	vid_mapping_table->num_entries = i;
 191}
 192
 193#if 0
 194static const struct kv_lcac_config_values sx_local_cac_cfg_kv[] =
 195{
 196	{  0,       4,        1    },
 197	{  1,       4,        1    },
 198	{  2,       5,        1    },
 199	{  3,       4,        2    },
 200	{  4,       1,        1    },
 201	{  5,       5,        2    },
 202	{  6,       6,        1    },
 203	{  7,       9,        2    },
 204	{ 0xffffffff }
 205};
 206
 207static const struct kv_lcac_config_values mc0_local_cac_cfg_kv[] =
 208{
 209	{  0,       4,        1    },
 210	{ 0xffffffff }
 211};
 212
 213static const struct kv_lcac_config_values mc1_local_cac_cfg_kv[] =
 214{
 215	{  0,       4,        1    },
 216	{ 0xffffffff }
 217};
 218
 219static const struct kv_lcac_config_values mc2_local_cac_cfg_kv[] =
 220{
 221	{  0,       4,        1    },
 222	{ 0xffffffff }
 223};
 224
 225static const struct kv_lcac_config_values mc3_local_cac_cfg_kv[] =
 226{
 227	{  0,       4,        1    },
 228	{ 0xffffffff }
 229};
 230
 231static const struct kv_lcac_config_values cpl_local_cac_cfg_kv[] =
 232{
 233	{  0,       4,        1    },
 234	{  1,       4,        1    },
 235	{  2,       5,        1    },
 236	{  3,       4,        1    },
 237	{  4,       1,        1    },
 238	{  5,       5,        1    },
 239	{  6,       6,        1    },
 240	{  7,       9,        1    },
 241	{  8,       4,        1    },
 242	{  9,       2,        1    },
 243	{  10,      3,        1    },
 244	{  11,      6,        1    },
 245	{  12,      8,        2    },
 246	{  13,      1,        1    },
 247	{  14,      2,        1    },
 248	{  15,      3,        1    },
 249	{  16,      1,        1    },
 250	{  17,      4,        1    },
 251	{  18,      3,        1    },
 252	{  19,      1,        1    },
 253	{  20,      8,        1    },
 254	{  21,      5,        1    },
 255	{  22,      1,        1    },
 256	{  23,      1,        1    },
 257	{  24,      4,        1    },
 258	{  27,      6,        1    },
 259	{  28,      1,        1    },
 260	{ 0xffffffff }
 261};
 262
 263static const struct kv_lcac_config_reg sx0_cac_config_reg[] =
 264{
 265	{ 0xc0400d00, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
 266};
 267
 268static const struct kv_lcac_config_reg mc0_cac_config_reg[] =
 269{
 270	{ 0xc0400d30, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
 271};
 272
 273static const struct kv_lcac_config_reg mc1_cac_config_reg[] =
 274{
 275	{ 0xc0400d3c, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
 276};
 277
 278static const struct kv_lcac_config_reg mc2_cac_config_reg[] =
 279{
 280	{ 0xc0400d48, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
 281};
 282
 283static const struct kv_lcac_config_reg mc3_cac_config_reg[] =
 284{
 285	{ 0xc0400d54, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
 286};
 287
 288static const struct kv_lcac_config_reg cpl_cac_config_reg[] =
 289{
 290	{ 0xc0400d80, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
 291};
 292#endif
 293
 294static const struct kv_pt_config_reg didt_config_kv[] =
 295{
 296	{ 0x10, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 297	{ 0x10, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 298	{ 0x10, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 299	{ 0x10, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 300	{ 0x11, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 301	{ 0x11, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 302	{ 0x11, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 303	{ 0x11, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 304	{ 0x12, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 305	{ 0x12, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 306	{ 0x12, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 307	{ 0x12, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 308	{ 0x2, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND },
 309	{ 0x2, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND },
 310	{ 0x2, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND },
 311	{ 0x1, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND },
 312	{ 0x1, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND },
 313	{ 0x0, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 314	{ 0x30, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 315	{ 0x30, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 316	{ 0x30, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 317	{ 0x30, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 318	{ 0x31, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 319	{ 0x31, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 320	{ 0x31, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 321	{ 0x31, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 322	{ 0x32, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 323	{ 0x32, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 324	{ 0x32, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 325	{ 0x32, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 326	{ 0x22, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND },
 327	{ 0x22, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND },
 328	{ 0x22, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND },
 329	{ 0x21, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND },
 330	{ 0x21, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND },
 331	{ 0x20, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 332	{ 0x50, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 333	{ 0x50, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 334	{ 0x50, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 335	{ 0x50, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 336	{ 0x51, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 337	{ 0x51, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 338	{ 0x51, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 339	{ 0x51, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 340	{ 0x52, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 341	{ 0x52, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 342	{ 0x52, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 343	{ 0x52, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 344	{ 0x42, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND },
 345	{ 0x42, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND },
 346	{ 0x42, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND },
 347	{ 0x41, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND },
 348	{ 0x41, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND },
 349	{ 0x40, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 350	{ 0x70, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 351	{ 0x70, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 352	{ 0x70, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 353	{ 0x70, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 354	{ 0x71, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 355	{ 0x71, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 356	{ 0x71, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 357	{ 0x71, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 358	{ 0x72, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 359	{ 0x72, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 360	{ 0x72, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 361	{ 0x72, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 362	{ 0x62, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND },
 363	{ 0x62, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND },
 364	{ 0x62, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND },
 365	{ 0x61, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND },
 366	{ 0x61, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND },
 367	{ 0x60, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 368	{ 0xFFFFFFFF }
 369};
 370
 371static struct kv_ps *kv_get_ps(struct amdgpu_ps *rps)
 372{
 373	struct kv_ps *ps = rps->ps_priv;
 374
 375	return ps;
 376}
 377
 378static struct kv_power_info *kv_get_pi(struct amdgpu_device *adev)
 379{
 380	struct kv_power_info *pi = adev->pm.dpm.priv;
 381
 382	return pi;
 383}
 384
 385#if 0
 386static void kv_program_local_cac_table(struct amdgpu_device *adev,
 387				       const struct kv_lcac_config_values *local_cac_table,
 388				       const struct kv_lcac_config_reg *local_cac_reg)
 389{
 390	u32 i, count, data;
 391	const struct kv_lcac_config_values *values = local_cac_table;
 392
 393	while (values->block_id != 0xffffffff) {
 394		count = values->signal_id;
 395		for (i = 0; i < count; i++) {
 396			data = ((values->block_id << local_cac_reg->block_shift) &
 397				local_cac_reg->block_mask);
 398			data |= ((i << local_cac_reg->signal_shift) &
 399				 local_cac_reg->signal_mask);
 400			data |= ((values->t << local_cac_reg->t_shift) &
 401				 local_cac_reg->t_mask);
 402			data |= ((1 << local_cac_reg->enable_shift) &
 403				 local_cac_reg->enable_mask);
 404			WREG32_SMC(local_cac_reg->cntl, data);
 405		}
 406		values++;
 407	}
 408}
 409#endif
 410
 411static int kv_program_pt_config_registers(struct amdgpu_device *adev,
 412					  const struct kv_pt_config_reg *cac_config_regs)
 413{
 414	const struct kv_pt_config_reg *config_regs = cac_config_regs;
 415	u32 data;
 416	u32 cache = 0;
 417
 418	if (config_regs == NULL)
 419		return -EINVAL;
 420
 421	while (config_regs->offset != 0xFFFFFFFF) {
 422		if (config_regs->type == KV_CONFIGREG_CACHE) {
 423			cache |= ((config_regs->value << config_regs->shift) & config_regs->mask);
 424		} else {
 425			switch (config_regs->type) {
 426			case KV_CONFIGREG_SMC_IND:
 427				data = RREG32_SMC(config_regs->offset);
 428				break;
 429			case KV_CONFIGREG_DIDT_IND:
 430				data = RREG32_DIDT(config_regs->offset);
 431				break;
 432			default:
 433				data = RREG32(config_regs->offset);
 434				break;
 435			}
 436
 437			data &= ~config_regs->mask;
 438			data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
 439			data |= cache;
 440			cache = 0;
 441
 442			switch (config_regs->type) {
 443			case KV_CONFIGREG_SMC_IND:
 444				WREG32_SMC(config_regs->offset, data);
 445				break;
 446			case KV_CONFIGREG_DIDT_IND:
 447				WREG32_DIDT(config_regs->offset, data);
 448				break;
 449			default:
 450				WREG32(config_regs->offset, data);
 451				break;
 452			}
 453		}
 454		config_regs++;
 455	}
 456
 457	return 0;
 458}
 459
 460static void kv_do_enable_didt(struct amdgpu_device *adev, bool enable)
 461{
 462	struct kv_power_info *pi = kv_get_pi(adev);
 463	u32 data;
 464
 465	if (pi->caps_sq_ramping) {
 466		data = RREG32_DIDT(ixDIDT_SQ_CTRL0);
 467		if (enable)
 468			data |= DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK;
 469		else
 470			data &= ~DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK;
 471		WREG32_DIDT(ixDIDT_SQ_CTRL0, data);
 472	}
 473
 474	if (pi->caps_db_ramping) {
 475		data = RREG32_DIDT(ixDIDT_DB_CTRL0);
 476		if (enable)
 477			data |= DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK;
 478		else
 479			data &= ~DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK;
 480		WREG32_DIDT(ixDIDT_DB_CTRL0, data);
 481	}
 482
 483	if (pi->caps_td_ramping) {
 484		data = RREG32_DIDT(ixDIDT_TD_CTRL0);
 485		if (enable)
 486			data |= DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK;
 487		else
 488			data &= ~DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK;
 489		WREG32_DIDT(ixDIDT_TD_CTRL0, data);
 490	}
 491
 492	if (pi->caps_tcp_ramping) {
 493		data = RREG32_DIDT(ixDIDT_TCP_CTRL0);
 494		if (enable)
 495			data |= DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK;
 496		else
 497			data &= ~DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK;
 498		WREG32_DIDT(ixDIDT_TCP_CTRL0, data);
 499	}
 500}
 501
 502static int kv_enable_didt(struct amdgpu_device *adev, bool enable)
 503{
 504	struct kv_power_info *pi = kv_get_pi(adev);
 505	int ret;
 506
 507	if (pi->caps_sq_ramping ||
 508	    pi->caps_db_ramping ||
 509	    pi->caps_td_ramping ||
 510	    pi->caps_tcp_ramping) {
 511		adev->gfx.rlc.funcs->enter_safe_mode(adev);
 512
 513		if (enable) {
 514			ret = kv_program_pt_config_registers(adev, didt_config_kv);
 515			if (ret) {
 516				adev->gfx.rlc.funcs->exit_safe_mode(adev);
 517				return ret;
 518			}
 519		}
 520
 521		kv_do_enable_didt(adev, enable);
 522
 523		adev->gfx.rlc.funcs->exit_safe_mode(adev);
 524	}
 525
 526	return 0;
 527}
 528
 529#if 0
 530static void kv_initialize_hardware_cac_manager(struct amdgpu_device *adev)
 531{
 532	struct kv_power_info *pi = kv_get_pi(adev);
 533
 534	if (pi->caps_cac) {
 535		WREG32_SMC(ixLCAC_SX0_OVR_SEL, 0);
 536		WREG32_SMC(ixLCAC_SX0_OVR_VAL, 0);
 537		kv_program_local_cac_table(adev, sx_local_cac_cfg_kv, sx0_cac_config_reg);
 538
 539		WREG32_SMC(ixLCAC_MC0_OVR_SEL, 0);
 540		WREG32_SMC(ixLCAC_MC0_OVR_VAL, 0);
 541		kv_program_local_cac_table(adev, mc0_local_cac_cfg_kv, mc0_cac_config_reg);
 542
 543		WREG32_SMC(ixLCAC_MC1_OVR_SEL, 0);
 544		WREG32_SMC(ixLCAC_MC1_OVR_VAL, 0);
 545		kv_program_local_cac_table(adev, mc1_local_cac_cfg_kv, mc1_cac_config_reg);
 546
 547		WREG32_SMC(ixLCAC_MC2_OVR_SEL, 0);
 548		WREG32_SMC(ixLCAC_MC2_OVR_VAL, 0);
 549		kv_program_local_cac_table(adev, mc2_local_cac_cfg_kv, mc2_cac_config_reg);
 550
 551		WREG32_SMC(ixLCAC_MC3_OVR_SEL, 0);
 552		WREG32_SMC(ixLCAC_MC3_OVR_VAL, 0);
 553		kv_program_local_cac_table(adev, mc3_local_cac_cfg_kv, mc3_cac_config_reg);
 554
 555		WREG32_SMC(ixLCAC_CPL_OVR_SEL, 0);
 556		WREG32_SMC(ixLCAC_CPL_OVR_VAL, 0);
 557		kv_program_local_cac_table(adev, cpl_local_cac_cfg_kv, cpl_cac_config_reg);
 558	}
 559}
 560#endif
 561
 562static int kv_enable_smc_cac(struct amdgpu_device *adev, bool enable)
 563{
 564	struct kv_power_info *pi = kv_get_pi(adev);
 565	int ret = 0;
 566
 567	if (pi->caps_cac) {
 568		if (enable) {
 569			ret = amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_EnableCac);
 570			if (ret)
 571				pi->cac_enabled = false;
 572			else
 573				pi->cac_enabled = true;
 574		} else if (pi->cac_enabled) {
 575			amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_DisableCac);
 576			pi->cac_enabled = false;
 577		}
 578	}
 579
 580	return ret;
 581}
 582
 583static int kv_process_firmware_header(struct amdgpu_device *adev)
 584{
 585	struct kv_power_info *pi = kv_get_pi(adev);
 586	u32 tmp;
 587	int ret;
 588
 589	ret = amdgpu_kv_read_smc_sram_dword(adev, SMU7_FIRMWARE_HEADER_LOCATION +
 590				     offsetof(SMU7_Firmware_Header, DpmTable),
 591				     &tmp, pi->sram_end);
 592
 593	if (ret == 0)
 594		pi->dpm_table_start = tmp;
 595
 596	ret = amdgpu_kv_read_smc_sram_dword(adev, SMU7_FIRMWARE_HEADER_LOCATION +
 597				     offsetof(SMU7_Firmware_Header, SoftRegisters),
 598				     &tmp, pi->sram_end);
 599
 600	if (ret == 0)
 601		pi->soft_regs_start = tmp;
 602
 603	return ret;
 604}
 605
 606static int kv_enable_dpm_voltage_scaling(struct amdgpu_device *adev)
 607{
 608	struct kv_power_info *pi = kv_get_pi(adev);
 609	int ret;
 610
 611	pi->graphics_voltage_change_enable = 1;
 612
 613	ret = amdgpu_kv_copy_bytes_to_smc(adev,
 614				   pi->dpm_table_start +
 615				   offsetof(SMU7_Fusion_DpmTable, GraphicsVoltageChangeEnable),
 616				   &pi->graphics_voltage_change_enable,
 617				   sizeof(u8), pi->sram_end);
 618
 619	return ret;
 620}
 621
 622static int kv_set_dpm_interval(struct amdgpu_device *adev)
 623{
 624	struct kv_power_info *pi = kv_get_pi(adev);
 625	int ret;
 626
 627	pi->graphics_interval = 1;
 628
 629	ret = amdgpu_kv_copy_bytes_to_smc(adev,
 630				   pi->dpm_table_start +
 631				   offsetof(SMU7_Fusion_DpmTable, GraphicsInterval),
 632				   &pi->graphics_interval,
 633				   sizeof(u8), pi->sram_end);
 634
 635	return ret;
 636}
 637
 638static int kv_set_dpm_boot_state(struct amdgpu_device *adev)
 639{
 640	struct kv_power_info *pi = kv_get_pi(adev);
 641	int ret;
 642
 643	ret = amdgpu_kv_copy_bytes_to_smc(adev,
 644				   pi->dpm_table_start +
 645				   offsetof(SMU7_Fusion_DpmTable, GraphicsBootLevel),
 646				   &pi->graphics_boot_level,
 647				   sizeof(u8), pi->sram_end);
 648
 649	return ret;
 650}
 651
 652static void kv_program_vc(struct amdgpu_device *adev)
 653{
 654	WREG32_SMC(ixCG_FREQ_TRAN_VOTING_0, 0x3FFFC100);
 655}
 656
 657static void kv_clear_vc(struct amdgpu_device *adev)
 658{
 659	WREG32_SMC(ixCG_FREQ_TRAN_VOTING_0, 0);
 660}
 661
 662static int kv_set_divider_value(struct amdgpu_device *adev,
 663				u32 index, u32 sclk)
 664{
 665	struct kv_power_info *pi = kv_get_pi(adev);
 666	struct atom_clock_dividers dividers;
 667	int ret;
 668
 669	ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
 670						 sclk, false, &dividers);
 671	if (ret)
 672		return ret;
 673
 674	pi->graphics_level[index].SclkDid = (u8)dividers.post_div;
 675	pi->graphics_level[index].SclkFrequency = cpu_to_be32(sclk);
 676
 677	return 0;
 678}
 679
 680static u16 kv_convert_8bit_index_to_voltage(struct amdgpu_device *adev,
 681					    u16 voltage)
 682{
 683	return 6200 - (voltage * 25);
 684}
 685
 686static u16 kv_convert_2bit_index_to_voltage(struct amdgpu_device *adev,
 687					    u32 vid_2bit)
 688{
 689	struct kv_power_info *pi = kv_get_pi(adev);
 690	u32 vid_8bit = kv_convert_vid2_to_vid7(adev,
 691					       &pi->sys_info.vid_mapping_table,
 692					       vid_2bit);
 693
 694	return kv_convert_8bit_index_to_voltage(adev, (u16)vid_8bit);
 695}
 696
 697
 698static int kv_set_vid(struct amdgpu_device *adev, u32 index, u32 vid)
 699{
 700	struct kv_power_info *pi = kv_get_pi(adev);
 701
 702	pi->graphics_level[index].VoltageDownH = (u8)pi->voltage_drop_t;
 703	pi->graphics_level[index].MinVddNb =
 704		cpu_to_be32(kv_convert_2bit_index_to_voltage(adev, vid));
 705
 706	return 0;
 707}
 708
 709static int kv_set_at(struct amdgpu_device *adev, u32 index, u32 at)
 710{
 711	struct kv_power_info *pi = kv_get_pi(adev);
 712
 713	pi->graphics_level[index].AT = cpu_to_be16((u16)at);
 714
 715	return 0;
 716}
 717
 718static void kv_dpm_power_level_enable(struct amdgpu_device *adev,
 719				      u32 index, bool enable)
 720{
 721	struct kv_power_info *pi = kv_get_pi(adev);
 722
 723	pi->graphics_level[index].EnabledForActivity = enable ? 1 : 0;
 724}
 725
 726static void kv_start_dpm(struct amdgpu_device *adev)
 727{
 728	u32 tmp = RREG32_SMC(ixGENERAL_PWRMGT);
 729
 730	tmp |= GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK;
 731	WREG32_SMC(ixGENERAL_PWRMGT, tmp);
 732
 733	amdgpu_kv_smc_dpm_enable(adev, true);
 734}
 735
 736static void kv_stop_dpm(struct amdgpu_device *adev)
 737{
 738	amdgpu_kv_smc_dpm_enable(adev, false);
 739}
 740
 741static void kv_start_am(struct amdgpu_device *adev)
 742{
 743	u32 sclk_pwrmgt_cntl = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
 744
 745	sclk_pwrmgt_cntl &= ~(SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK |
 746			SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK);
 747	sclk_pwrmgt_cntl |= SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN_MASK;
 748
 749	WREG32_SMC(ixSCLK_PWRMGT_CNTL, sclk_pwrmgt_cntl);
 750}
 751
 752static void kv_reset_am(struct amdgpu_device *adev)
 753{
 754	u32 sclk_pwrmgt_cntl = RREG32_SMC(ixSCLK_PWRMGT_CNTL);
 755
 756	sclk_pwrmgt_cntl |= (SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK |
 757			SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK);
 758
 759	WREG32_SMC(ixSCLK_PWRMGT_CNTL, sclk_pwrmgt_cntl);
 760}
 761
 762static int kv_freeze_sclk_dpm(struct amdgpu_device *adev, bool freeze)
 763{
 764	return amdgpu_kv_notify_message_to_smu(adev, freeze ?
 765					PPSMC_MSG_SCLKDPM_FreezeLevel : PPSMC_MSG_SCLKDPM_UnfreezeLevel);
 766}
 767
 768static int kv_force_lowest_valid(struct amdgpu_device *adev)
 769{
 770	return kv_force_dpm_lowest(adev);
 771}
 772
 773static int kv_unforce_levels(struct amdgpu_device *adev)
 774{
 775	if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS)
 776		return amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_NoForcedLevel);
 777	else
 778		return kv_set_enabled_levels(adev);
 779}
 780
 781static int kv_update_sclk_t(struct amdgpu_device *adev)
 782{
 783	struct kv_power_info *pi = kv_get_pi(adev);
 784	u32 low_sclk_interrupt_t = 0;
 785	int ret = 0;
 786
 787	if (pi->caps_sclk_throttle_low_notification) {
 788		low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t);
 789
 790		ret = amdgpu_kv_copy_bytes_to_smc(adev,
 791					   pi->dpm_table_start +
 792					   offsetof(SMU7_Fusion_DpmTable, LowSclkInterruptT),
 793					   (u8 *)&low_sclk_interrupt_t,
 794					   sizeof(u32), pi->sram_end);
 795	}
 796	return ret;
 797}
 798
 799static int kv_program_bootup_state(struct amdgpu_device *adev)
 800{
 801	struct kv_power_info *pi = kv_get_pi(adev);
 802	u32 i;
 803	struct amdgpu_clock_voltage_dependency_table *table =
 804		&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
 805
 806	if (table && table->count) {
 807		for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) {
 808			if (table->entries[i].clk == pi->boot_pl.sclk)
 809				break;
 810		}
 811
 812		pi->graphics_boot_level = (u8)i;
 813		kv_dpm_power_level_enable(adev, i, true);
 814	} else {
 815		struct sumo_sclk_voltage_mapping_table *table =
 816			&pi->sys_info.sclk_voltage_mapping_table;
 817
 818		if (table->num_max_dpm_entries == 0)
 819			return -EINVAL;
 820
 821		for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) {
 822			if (table->entries[i].sclk_frequency == pi->boot_pl.sclk)
 823				break;
 824		}
 825
 826		pi->graphics_boot_level = (u8)i;
 827		kv_dpm_power_level_enable(adev, i, true);
 828	}
 829	return 0;
 830}
 831
 832static int kv_enable_auto_thermal_throttling(struct amdgpu_device *adev)
 833{
 834	struct kv_power_info *pi = kv_get_pi(adev);
 835	int ret;
 836
 837	pi->graphics_therm_throttle_enable = 1;
 838
 839	ret = amdgpu_kv_copy_bytes_to_smc(adev,
 840				   pi->dpm_table_start +
 841				   offsetof(SMU7_Fusion_DpmTable, GraphicsThermThrottleEnable),
 842				   &pi->graphics_therm_throttle_enable,
 843				   sizeof(u8), pi->sram_end);
 844
 845	return ret;
 846}
 847
 848static int kv_upload_dpm_settings(struct amdgpu_device *adev)
 849{
 850	struct kv_power_info *pi = kv_get_pi(adev);
 851	int ret;
 852
 853	ret = amdgpu_kv_copy_bytes_to_smc(adev,
 854				   pi->dpm_table_start +
 855				   offsetof(SMU7_Fusion_DpmTable, GraphicsLevel),
 856				   (u8 *)&pi->graphics_level,
 857				   sizeof(SMU7_Fusion_GraphicsLevel) * SMU7_MAX_LEVELS_GRAPHICS,
 858				   pi->sram_end);
 859
 860	if (ret)
 861		return ret;
 862
 863	ret = amdgpu_kv_copy_bytes_to_smc(adev,
 864				   pi->dpm_table_start +
 865				   offsetof(SMU7_Fusion_DpmTable, GraphicsDpmLevelCount),
 866				   &pi->graphics_dpm_level_count,
 867				   sizeof(u8), pi->sram_end);
 868
 869	return ret;
 870}
 871
 872static u32 kv_get_clock_difference(u32 a, u32 b)
 873{
 874	return (a >= b) ? a - b : b - a;
 875}
 876
 877static u32 kv_get_clk_bypass(struct amdgpu_device *adev, u32 clk)
 878{
 879	struct kv_power_info *pi = kv_get_pi(adev);
 880	u32 value;
 881
 882	if (pi->caps_enable_dfs_bypass) {
 883		if (kv_get_clock_difference(clk, 40000) < 200)
 884			value = 3;
 885		else if (kv_get_clock_difference(clk, 30000) < 200)
 886			value = 2;
 887		else if (kv_get_clock_difference(clk, 20000) < 200)
 888			value = 7;
 889		else if (kv_get_clock_difference(clk, 15000) < 200)
 890			value = 6;
 891		else if (kv_get_clock_difference(clk, 10000) < 200)
 892			value = 8;
 893		else
 894			value = 0;
 895	} else {
 896		value = 0;
 897	}
 898
 899	return value;
 900}
 901
 902static int kv_populate_uvd_table(struct amdgpu_device *adev)
 903{
 904	struct kv_power_info *pi = kv_get_pi(adev);
 905	struct amdgpu_uvd_clock_voltage_dependency_table *table =
 906		&adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
 907	struct atom_clock_dividers dividers;
 908	int ret;
 909	u32 i;
 910
 911	if (table == NULL || table->count == 0)
 912		return 0;
 913
 914	pi->uvd_level_count = 0;
 915	for (i = 0; i < table->count; i++) {
 916		if (pi->high_voltage_t &&
 917		    (pi->high_voltage_t < table->entries[i].v))
 918			break;
 919
 920		pi->uvd_level[i].VclkFrequency = cpu_to_be32(table->entries[i].vclk);
 921		pi->uvd_level[i].DclkFrequency = cpu_to_be32(table->entries[i].dclk);
 922		pi->uvd_level[i].MinVddNb = cpu_to_be16(table->entries[i].v);
 923
 924		pi->uvd_level[i].VClkBypassCntl =
 925			(u8)kv_get_clk_bypass(adev, table->entries[i].vclk);
 926		pi->uvd_level[i].DClkBypassCntl =
 927			(u8)kv_get_clk_bypass(adev, table->entries[i].dclk);
 928
 929		ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
 930							 table->entries[i].vclk, false, &dividers);
 931		if (ret)
 932			return ret;
 933		pi->uvd_level[i].VclkDivider = (u8)dividers.post_div;
 934
 935		ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
 936							 table->entries[i].dclk, false, &dividers);
 937		if (ret)
 938			return ret;
 939		pi->uvd_level[i].DclkDivider = (u8)dividers.post_div;
 940
 941		pi->uvd_level_count++;
 942	}
 943
 944	ret = amdgpu_kv_copy_bytes_to_smc(adev,
 945				   pi->dpm_table_start +
 946				   offsetof(SMU7_Fusion_DpmTable, UvdLevelCount),
 947				   (u8 *)&pi->uvd_level_count,
 948				   sizeof(u8), pi->sram_end);
 949	if (ret)
 950		return ret;
 951
 952	pi->uvd_interval = 1;
 953
 954	ret = amdgpu_kv_copy_bytes_to_smc(adev,
 955				   pi->dpm_table_start +
 956				   offsetof(SMU7_Fusion_DpmTable, UVDInterval),
 957				   &pi->uvd_interval,
 958				   sizeof(u8), pi->sram_end);
 959	if (ret)
 960		return ret;
 961
 962	ret = amdgpu_kv_copy_bytes_to_smc(adev,
 963				   pi->dpm_table_start +
 964				   offsetof(SMU7_Fusion_DpmTable, UvdLevel),
 965				   (u8 *)&pi->uvd_level,
 966				   sizeof(SMU7_Fusion_UvdLevel) * SMU7_MAX_LEVELS_UVD,
 967				   pi->sram_end);
 968
 969	return ret;
 970
 971}
 972
 973static int kv_populate_vce_table(struct amdgpu_device *adev)
 974{
 975	struct kv_power_info *pi = kv_get_pi(adev);
 976	int ret;
 977	u32 i;
 978	struct amdgpu_vce_clock_voltage_dependency_table *table =
 979		&adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
 980	struct atom_clock_dividers dividers;
 981
 982	if (table == NULL || table->count == 0)
 983		return 0;
 984
 985	pi->vce_level_count = 0;
 986	for (i = 0; i < table->count; i++) {
 987		if (pi->high_voltage_t &&
 988		    pi->high_voltage_t < table->entries[i].v)
 989			break;
 990
 991		pi->vce_level[i].Frequency = cpu_to_be32(table->entries[i].evclk);
 992		pi->vce_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);
 993
 994		pi->vce_level[i].ClkBypassCntl =
 995			(u8)kv_get_clk_bypass(adev, table->entries[i].evclk);
 996
 997		ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
 998							 table->entries[i].evclk, false, &dividers);
 999		if (ret)
1000			return ret;
1001		pi->vce_level[i].Divider = (u8)dividers.post_div;
1002
1003		pi->vce_level_count++;
1004	}
1005
1006	ret = amdgpu_kv_copy_bytes_to_smc(adev,
1007				   pi->dpm_table_start +
1008				   offsetof(SMU7_Fusion_DpmTable, VceLevelCount),
1009				   (u8 *)&pi->vce_level_count,
1010				   sizeof(u8),
1011				   pi->sram_end);
1012	if (ret)
1013		return ret;
1014
1015	pi->vce_interval = 1;
1016
1017	ret = amdgpu_kv_copy_bytes_to_smc(adev,
1018				   pi->dpm_table_start +
1019				   offsetof(SMU7_Fusion_DpmTable, VCEInterval),
1020				   (u8 *)&pi->vce_interval,
1021				   sizeof(u8),
1022				   pi->sram_end);
1023	if (ret)
1024		return ret;
1025
1026	ret = amdgpu_kv_copy_bytes_to_smc(adev,
1027				   pi->dpm_table_start +
1028				   offsetof(SMU7_Fusion_DpmTable, VceLevel),
1029				   (u8 *)&pi->vce_level,
1030				   sizeof(SMU7_Fusion_ExtClkLevel) * SMU7_MAX_LEVELS_VCE,
1031				   pi->sram_end);
1032
1033	return ret;
1034}
1035
1036static int kv_populate_samu_table(struct amdgpu_device *adev)
1037{
1038	struct kv_power_info *pi = kv_get_pi(adev);
1039	struct amdgpu_clock_voltage_dependency_table *table =
1040		&adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table;
1041	struct atom_clock_dividers dividers;
1042	int ret;
1043	u32 i;
1044
1045	if (table == NULL || table->count == 0)
1046		return 0;
1047
1048	pi->samu_level_count = 0;
1049	for (i = 0; i < table->count; i++) {
1050		if (pi->high_voltage_t &&
1051		    pi->high_voltage_t < table->entries[i].v)
1052			break;
1053
1054		pi->samu_level[i].Frequency = cpu_to_be32(table->entries[i].clk);
1055		pi->samu_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);
1056
1057		pi->samu_level[i].ClkBypassCntl =
1058			(u8)kv_get_clk_bypass(adev, table->entries[i].clk);
1059
1060		ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
1061							 table->entries[i].clk, false, &dividers);
1062		if (ret)
1063			return ret;
1064		pi->samu_level[i].Divider = (u8)dividers.post_div;
1065
1066		pi->samu_level_count++;
1067	}
1068
1069	ret = amdgpu_kv_copy_bytes_to_smc(adev,
1070				   pi->dpm_table_start +
1071				   offsetof(SMU7_Fusion_DpmTable, SamuLevelCount),
1072				   (u8 *)&pi->samu_level_count,
1073				   sizeof(u8),
1074				   pi->sram_end);
1075	if (ret)
1076		return ret;
1077
1078	pi->samu_interval = 1;
1079
1080	ret = amdgpu_kv_copy_bytes_to_smc(adev,
1081				   pi->dpm_table_start +
1082				   offsetof(SMU7_Fusion_DpmTable, SAMUInterval),
1083				   (u8 *)&pi->samu_interval,
1084				   sizeof(u8),
1085				   pi->sram_end);
1086	if (ret)
1087		return ret;
1088
1089	ret = amdgpu_kv_copy_bytes_to_smc(adev,
1090				   pi->dpm_table_start +
1091				   offsetof(SMU7_Fusion_DpmTable, SamuLevel),
1092				   (u8 *)&pi->samu_level,
1093				   sizeof(SMU7_Fusion_ExtClkLevel) * SMU7_MAX_LEVELS_SAMU,
1094				   pi->sram_end);
1095	if (ret)
1096		return ret;
1097
1098	return ret;
1099}
1100
1101
1102static int kv_populate_acp_table(struct amdgpu_device *adev)
1103{
1104	struct kv_power_info *pi = kv_get_pi(adev);
1105	struct amdgpu_clock_voltage_dependency_table *table =
1106		&adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
1107	struct atom_clock_dividers dividers;
1108	int ret;
1109	u32 i;
1110
1111	if (table == NULL || table->count == 0)
1112		return 0;
1113
1114	pi->acp_level_count = 0;
1115	for (i = 0; i < table->count; i++) {
1116		pi->acp_level[i].Frequency = cpu_to_be32(table->entries[i].clk);
1117		pi->acp_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);
1118
1119		ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
1120							 table->entries[i].clk, false, &dividers);
1121		if (ret)
1122			return ret;
1123		pi->acp_level[i].Divider = (u8)dividers.post_div;
1124
1125		pi->acp_level_count++;
1126	}
1127
1128	ret = amdgpu_kv_copy_bytes_to_smc(adev,
1129				   pi->dpm_table_start +
1130				   offsetof(SMU7_Fusion_DpmTable, AcpLevelCount),
1131				   (u8 *)&pi->acp_level_count,
1132				   sizeof(u8),
1133				   pi->sram_end);
1134	if (ret)
1135		return ret;
1136
1137	pi->acp_interval = 1;
1138
1139	ret = amdgpu_kv_copy_bytes_to_smc(adev,
1140				   pi->dpm_table_start +
1141				   offsetof(SMU7_Fusion_DpmTable, ACPInterval),
1142				   (u8 *)&pi->acp_interval,
1143				   sizeof(u8),
1144				   pi->sram_end);
1145	if (ret)
1146		return ret;
1147
1148	ret = amdgpu_kv_copy_bytes_to_smc(adev,
1149				   pi->dpm_table_start +
1150				   offsetof(SMU7_Fusion_DpmTable, AcpLevel),
1151				   (u8 *)&pi->acp_level,
1152				   sizeof(SMU7_Fusion_ExtClkLevel) * SMU7_MAX_LEVELS_ACP,
1153				   pi->sram_end);
1154	if (ret)
1155		return ret;
1156
1157	return ret;
1158}
1159
1160static void kv_calculate_dfs_bypass_settings(struct amdgpu_device *adev)
1161{
1162	struct kv_power_info *pi = kv_get_pi(adev);
1163	u32 i;
1164	struct amdgpu_clock_voltage_dependency_table *table =
1165		&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
1166
1167	if (table && table->count) {
1168		for (i = 0; i < pi->graphics_dpm_level_count; i++) {
1169			if (pi->caps_enable_dfs_bypass) {
1170				if (kv_get_clock_difference(table->entries[i].clk, 40000) < 200)
1171					pi->graphics_level[i].ClkBypassCntl = 3;
1172				else if (kv_get_clock_difference(table->entries[i].clk, 30000) < 200)
1173					pi->graphics_level[i].ClkBypassCntl = 2;
1174				else if (kv_get_clock_difference(table->entries[i].clk, 26600) < 200)
1175					pi->graphics_level[i].ClkBypassCntl = 7;
1176				else if (kv_get_clock_difference(table->entries[i].clk , 20000) < 200)
1177					pi->graphics_level[i].ClkBypassCntl = 6;
1178				else if (kv_get_clock_difference(table->entries[i].clk , 10000) < 200)
1179					pi->graphics_level[i].ClkBypassCntl = 8;
1180				else
1181					pi->graphics_level[i].ClkBypassCntl = 0;
1182			} else {
1183				pi->graphics_level[i].ClkBypassCntl = 0;
1184			}
1185		}
1186	} else {
1187		struct sumo_sclk_voltage_mapping_table *table =
1188			&pi->sys_info.sclk_voltage_mapping_table;
1189		for (i = 0; i < pi->graphics_dpm_level_count; i++) {
1190			if (pi->caps_enable_dfs_bypass) {
1191				if (kv_get_clock_difference(table->entries[i].sclk_frequency, 40000) < 200)
1192					pi->graphics_level[i].ClkBypassCntl = 3;
1193				else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 30000) < 200)
1194					pi->graphics_level[i].ClkBypassCntl = 2;
1195				else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 26600) < 200)
1196					pi->graphics_level[i].ClkBypassCntl = 7;
1197				else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 20000) < 200)
1198					pi->graphics_level[i].ClkBypassCntl = 6;
1199				else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 10000) < 200)
1200					pi->graphics_level[i].ClkBypassCntl = 8;
1201				else
1202					pi->graphics_level[i].ClkBypassCntl = 0;
1203			} else {
1204				pi->graphics_level[i].ClkBypassCntl = 0;
1205			}
1206		}
1207	}
1208}
1209
1210static int kv_enable_ulv(struct amdgpu_device *adev, bool enable)
1211{
1212	return amdgpu_kv_notify_message_to_smu(adev, enable ?
1213					PPSMC_MSG_EnableULV : PPSMC_MSG_DisableULV);
1214}
1215
1216static void kv_reset_acp_boot_level(struct amdgpu_device *adev)
1217{
1218	struct kv_power_info *pi = kv_get_pi(adev);
1219
1220	pi->acp_boot_level = 0xff;
1221}
1222
1223static void kv_update_current_ps(struct amdgpu_device *adev,
1224				 struct amdgpu_ps *rps)
1225{
1226	struct kv_ps *new_ps = kv_get_ps(rps);
1227	struct kv_power_info *pi = kv_get_pi(adev);
1228
1229	pi->current_rps = *rps;
1230	pi->current_ps = *new_ps;
1231	pi->current_rps.ps_priv = &pi->current_ps;
1232	adev->pm.dpm.current_ps = &pi->current_rps;
1233}
1234
1235static void kv_update_requested_ps(struct amdgpu_device *adev,
1236				   struct amdgpu_ps *rps)
1237{
1238	struct kv_ps *new_ps = kv_get_ps(rps);
1239	struct kv_power_info *pi = kv_get_pi(adev);
1240
1241	pi->requested_rps = *rps;
1242	pi->requested_ps = *new_ps;
1243	pi->requested_rps.ps_priv = &pi->requested_ps;
1244	adev->pm.dpm.requested_ps = &pi->requested_rps;
1245}
1246
1247static void kv_dpm_enable_bapm(void *handle, bool enable)
1248{
1249	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1250	struct kv_power_info *pi = kv_get_pi(adev);
1251	int ret;
1252
1253	if (pi->bapm_enable) {
1254		ret = amdgpu_kv_smc_bapm_enable(adev, enable);
1255		if (ret)
1256			DRM_ERROR("amdgpu_kv_smc_bapm_enable failed\n");
1257	}
1258}
1259
1260static int kv_dpm_enable(struct amdgpu_device *adev)
1261{
1262	struct kv_power_info *pi = kv_get_pi(adev);
1263	int ret;
1264
1265	ret = kv_process_firmware_header(adev);
1266	if (ret) {
1267		DRM_ERROR("kv_process_firmware_header failed\n");
1268		return ret;
1269	}
1270	kv_init_fps_limits(adev);
1271	kv_init_graphics_levels(adev);
1272	ret = kv_program_bootup_state(adev);
1273	if (ret) {
1274		DRM_ERROR("kv_program_bootup_state failed\n");
1275		return ret;
1276	}
1277	kv_calculate_dfs_bypass_settings(adev);
1278	ret = kv_upload_dpm_settings(adev);
1279	if (ret) {
1280		DRM_ERROR("kv_upload_dpm_settings failed\n");
1281		return ret;
1282	}
1283	ret = kv_populate_uvd_table(adev);
1284	if (ret) {
1285		DRM_ERROR("kv_populate_uvd_table failed\n");
1286		return ret;
1287	}
1288	ret = kv_populate_vce_table(adev);
1289	if (ret) {
1290		DRM_ERROR("kv_populate_vce_table failed\n");
1291		return ret;
1292	}
1293	ret = kv_populate_samu_table(adev);
1294	if (ret) {
1295		DRM_ERROR("kv_populate_samu_table failed\n");
1296		return ret;
1297	}
1298	ret = kv_populate_acp_table(adev);
1299	if (ret) {
1300		DRM_ERROR("kv_populate_acp_table failed\n");
1301		return ret;
1302	}
1303	kv_program_vc(adev);
1304#if 0
1305	kv_initialize_hardware_cac_manager(adev);
1306#endif
1307	kv_start_am(adev);
1308	if (pi->enable_auto_thermal_throttling) {
1309		ret = kv_enable_auto_thermal_throttling(adev);
1310		if (ret) {
1311			DRM_ERROR("kv_enable_auto_thermal_throttling failed\n");
1312			return ret;
1313		}
1314	}
1315	ret = kv_enable_dpm_voltage_scaling(adev);
1316	if (ret) {
1317		DRM_ERROR("kv_enable_dpm_voltage_scaling failed\n");
1318		return ret;
1319	}
1320	ret = kv_set_dpm_interval(adev);
1321	if (ret) {
1322		DRM_ERROR("kv_set_dpm_interval failed\n");
1323		return ret;
1324	}
1325	ret = kv_set_dpm_boot_state(adev);
1326	if (ret) {
1327		DRM_ERROR("kv_set_dpm_boot_state failed\n");
1328		return ret;
1329	}
1330	ret = kv_enable_ulv(adev, true);
1331	if (ret) {
1332		DRM_ERROR("kv_enable_ulv failed\n");
1333		return ret;
1334	}
1335	kv_start_dpm(adev);
1336	ret = kv_enable_didt(adev, true);
1337	if (ret) {
1338		DRM_ERROR("kv_enable_didt failed\n");
1339		return ret;
1340	}
1341	ret = kv_enable_smc_cac(adev, true);
1342	if (ret) {
1343		DRM_ERROR("kv_enable_smc_cac failed\n");
1344		return ret;
1345	}
1346
1347	kv_reset_acp_boot_level(adev);
1348
1349	ret = amdgpu_kv_smc_bapm_enable(adev, false);
1350	if (ret) {
1351		DRM_ERROR("amdgpu_kv_smc_bapm_enable failed\n");
1352		return ret;
1353	}
1354
1355	kv_update_current_ps(adev, adev->pm.dpm.boot_ps);
1356
1357	if (adev->irq.installed &&
1358	    amdgpu_is_internal_thermal_sensor(adev->pm.int_thermal_type)) {
1359		ret = kv_set_thermal_temperature_range(adev, KV_TEMP_RANGE_MIN, KV_TEMP_RANGE_MAX);
1360		if (ret) {
1361			DRM_ERROR("kv_set_thermal_temperature_range failed\n");
1362			return ret;
1363		}
1364		amdgpu_irq_get(adev, &adev->pm.dpm.thermal.irq,
1365			       AMDGPU_THERMAL_IRQ_LOW_TO_HIGH);
1366		amdgpu_irq_get(adev, &adev->pm.dpm.thermal.irq,
1367			       AMDGPU_THERMAL_IRQ_HIGH_TO_LOW);
1368	}
1369
1370	return ret;
1371}
1372
1373static void kv_dpm_disable(struct amdgpu_device *adev)
1374{
1375	amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq,
1376		       AMDGPU_THERMAL_IRQ_LOW_TO_HIGH);
1377	amdgpu_irq_put(adev, &adev->pm.dpm.thermal.irq,
1378		       AMDGPU_THERMAL_IRQ_HIGH_TO_LOW);
1379
1380	amdgpu_kv_smc_bapm_enable(adev, false);
1381
1382	if (adev->asic_type == CHIP_MULLINS)
1383		kv_enable_nb_dpm(adev, false);
1384
1385	/* powerup blocks */
1386	kv_dpm_powergate_acp(adev, false);
1387	kv_dpm_powergate_samu(adev, false);
1388	kv_dpm_powergate_vce(adev, false);
1389	kv_dpm_powergate_uvd(adev, false);
1390
1391	kv_enable_smc_cac(adev, false);
1392	kv_enable_didt(adev, false);
1393	kv_clear_vc(adev);
1394	kv_stop_dpm(adev);
1395	kv_enable_ulv(adev, false);
1396	kv_reset_am(adev);
1397
1398	kv_update_current_ps(adev, adev->pm.dpm.boot_ps);
1399}
1400
1401#if 0
1402static int kv_write_smc_soft_register(struct amdgpu_device *adev,
1403				      u16 reg_offset, u32 value)
1404{
1405	struct kv_power_info *pi = kv_get_pi(adev);
1406
1407	return amdgpu_kv_copy_bytes_to_smc(adev, pi->soft_regs_start + reg_offset,
1408				    (u8 *)&value, sizeof(u16), pi->sram_end);
1409}
1410
1411static int kv_read_smc_soft_register(struct amdgpu_device *adev,
1412				     u16 reg_offset, u32 *value)
1413{
1414	struct kv_power_info *pi = kv_get_pi(adev);
1415
1416	return amdgpu_kv_read_smc_sram_dword(adev, pi->soft_regs_start + reg_offset,
1417				      value, pi->sram_end);
1418}
1419#endif
1420
1421static void kv_init_sclk_t(struct amdgpu_device *adev)
1422{
1423	struct kv_power_info *pi = kv_get_pi(adev);
1424
1425	pi->low_sclk_interrupt_t = 0;
1426}
1427
1428static int kv_init_fps_limits(struct amdgpu_device *adev)
1429{
1430	struct kv_power_info *pi = kv_get_pi(adev);
1431	int ret = 0;
1432
1433	if (pi->caps_fps) {
1434		u16 tmp;
1435
1436		tmp = 45;
1437		pi->fps_high_t = cpu_to_be16(tmp);
1438		ret = amdgpu_kv_copy_bytes_to_smc(adev,
1439					   pi->dpm_table_start +
1440					   offsetof(SMU7_Fusion_DpmTable, FpsHighT),
1441					   (u8 *)&pi->fps_high_t,
1442					   sizeof(u16), pi->sram_end);
1443
1444		tmp = 30;
1445		pi->fps_low_t = cpu_to_be16(tmp);
1446
1447		ret = amdgpu_kv_copy_bytes_to_smc(adev,
1448					   pi->dpm_table_start +
1449					   offsetof(SMU7_Fusion_DpmTable, FpsLowT),
1450					   (u8 *)&pi->fps_low_t,
1451					   sizeof(u16), pi->sram_end);
1452
1453	}
1454	return ret;
1455}
1456
1457static void kv_init_powergate_state(struct amdgpu_device *adev)
1458{
1459	struct kv_power_info *pi = kv_get_pi(adev);
1460
1461	pi->uvd_power_gated = false;
1462	pi->vce_power_gated = false;
1463	pi->samu_power_gated = false;
1464	pi->acp_power_gated = false;
1465
1466}
1467
1468static int kv_enable_uvd_dpm(struct amdgpu_device *adev, bool enable)
1469{
1470	return amdgpu_kv_notify_message_to_smu(adev, enable ?
1471					PPSMC_MSG_UVDDPM_Enable : PPSMC_MSG_UVDDPM_Disable);
1472}
1473
1474static int kv_enable_vce_dpm(struct amdgpu_device *adev, bool enable)
1475{
1476	return amdgpu_kv_notify_message_to_smu(adev, enable ?
1477					PPSMC_MSG_VCEDPM_Enable : PPSMC_MSG_VCEDPM_Disable);
1478}
1479
1480static int kv_enable_samu_dpm(struct amdgpu_device *adev, bool enable)
1481{
1482	return amdgpu_kv_notify_message_to_smu(adev, enable ?
1483					PPSMC_MSG_SAMUDPM_Enable : PPSMC_MSG_SAMUDPM_Disable);
1484}
1485
1486static int kv_enable_acp_dpm(struct amdgpu_device *adev, bool enable)
1487{
1488	return amdgpu_kv_notify_message_to_smu(adev, enable ?
1489					PPSMC_MSG_ACPDPM_Enable : PPSMC_MSG_ACPDPM_Disable);
1490}
1491
1492static int kv_update_uvd_dpm(struct amdgpu_device *adev, bool gate)
1493{
1494	struct kv_power_info *pi = kv_get_pi(adev);
1495	struct amdgpu_uvd_clock_voltage_dependency_table *table =
1496		&adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
1497	int ret;
1498	u32 mask;
1499
1500	if (!gate) {
1501		if (table->count)
1502			pi->uvd_boot_level = table->count - 1;
1503		else
1504			pi->uvd_boot_level = 0;
1505
1506		if (!pi->caps_uvd_dpm || pi->caps_stable_p_state) {
1507			mask = 1 << pi->uvd_boot_level;
1508		} else {
1509			mask = 0x1f;
1510		}
1511
1512		ret = amdgpu_kv_copy_bytes_to_smc(adev,
1513					   pi->dpm_table_start +
1514					   offsetof(SMU7_Fusion_DpmTable, UvdBootLevel),
1515					   (uint8_t *)&pi->uvd_boot_level,
1516					   sizeof(u8), pi->sram_end);
1517		if (ret)
1518			return ret;
1519
1520		amdgpu_kv_send_msg_to_smc_with_parameter(adev,
1521						  PPSMC_MSG_UVDDPM_SetEnabledMask,
1522						  mask);
1523	}
1524
1525	return kv_enable_uvd_dpm(adev, !gate);
1526}
1527
1528static u8 kv_get_vce_boot_level(struct amdgpu_device *adev, u32 evclk)
1529{
1530	u8 i;
1531	struct amdgpu_vce_clock_voltage_dependency_table *table =
1532		&adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
1533
1534	for (i = 0; i < table->count; i++) {
1535		if (table->entries[i].evclk >= evclk)
1536			break;
1537	}
1538
1539	return i;
1540}
1541
1542static int kv_update_vce_dpm(struct amdgpu_device *adev,
1543			     struct amdgpu_ps *amdgpu_new_state,
1544			     struct amdgpu_ps *amdgpu_current_state)
1545{
1546	struct kv_power_info *pi = kv_get_pi(adev);
1547	struct amdgpu_vce_clock_voltage_dependency_table *table =
1548		&adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
1549	int ret;
1550
1551	if (amdgpu_new_state->evclk > 0 && amdgpu_current_state->evclk == 0) {
1552		kv_dpm_powergate_vce(adev, false);
1553		if (pi->caps_stable_p_state)
1554			pi->vce_boot_level = table->count - 1;
1555		else
1556			pi->vce_boot_level = kv_get_vce_boot_level(adev, amdgpu_new_state->evclk);
1557
1558		ret = amdgpu_kv_copy_bytes_to_smc(adev,
1559					   pi->dpm_table_start +
1560					   offsetof(SMU7_Fusion_DpmTable, VceBootLevel),
1561					   (u8 *)&pi->vce_boot_level,
1562					   sizeof(u8),
1563					   pi->sram_end);
1564		if (ret)
1565			return ret;
1566
1567		if (pi->caps_stable_p_state)
1568			amdgpu_kv_send_msg_to_smc_with_parameter(adev,
1569							  PPSMC_MSG_VCEDPM_SetEnabledMask,
1570							  (1 << pi->vce_boot_level));
1571		kv_enable_vce_dpm(adev, true);
1572	} else if (amdgpu_new_state->evclk == 0 && amdgpu_current_state->evclk > 0) {
1573		kv_enable_vce_dpm(adev, false);
1574		kv_dpm_powergate_vce(adev, true);
1575	}
1576
1577	return 0;
1578}
1579
1580static int kv_update_samu_dpm(struct amdgpu_device *adev, bool gate)
1581{
1582	struct kv_power_info *pi = kv_get_pi(adev);
1583	struct amdgpu_clock_voltage_dependency_table *table =
1584		&adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table;
1585	int ret;
1586
1587	if (!gate) {
1588		if (pi->caps_stable_p_state)
1589			pi->samu_boot_level = table->count - 1;
1590		else
1591			pi->samu_boot_level = 0;
1592
1593		ret = amdgpu_kv_copy_bytes_to_smc(adev,
1594					   pi->dpm_table_start +
1595					   offsetof(SMU7_Fusion_DpmTable, SamuBootLevel),
1596					   (u8 *)&pi->samu_boot_level,
1597					   sizeof(u8),
1598					   pi->sram_end);
1599		if (ret)
1600			return ret;
1601
1602		if (pi->caps_stable_p_state)
1603			amdgpu_kv_send_msg_to_smc_with_parameter(adev,
1604							  PPSMC_MSG_SAMUDPM_SetEnabledMask,
1605							  (1 << pi->samu_boot_level));
1606	}
1607
1608	return kv_enable_samu_dpm(adev, !gate);
1609}
1610
1611static u8 kv_get_acp_boot_level(struct amdgpu_device *adev)
1612{
1613	u8 i;
1614	struct amdgpu_clock_voltage_dependency_table *table =
1615		&adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
1616
1617	for (i = 0; i < table->count; i++) {
1618		if (table->entries[i].clk >= 0) /* XXX */
1619			break;
1620	}
1621
1622	if (i >= table->count)
1623		i = table->count - 1;
1624
1625	return i;
1626}
1627
1628static void kv_update_acp_boot_level(struct amdgpu_device *adev)
1629{
1630	struct kv_power_info *pi = kv_get_pi(adev);
1631	u8 acp_boot_level;
1632
1633	if (!pi->caps_stable_p_state) {
1634		acp_boot_level = kv_get_acp_boot_level(adev);
1635		if (acp_boot_level != pi->acp_boot_level) {
1636			pi->acp_boot_level = acp_boot_level;
1637			amdgpu_kv_send_msg_to_smc_with_parameter(adev,
1638							  PPSMC_MSG_ACPDPM_SetEnabledMask,
1639							  (1 << pi->acp_boot_level));
1640		}
1641	}
1642}
1643
1644static int kv_update_acp_dpm(struct amdgpu_device *adev, bool gate)
1645{
1646	struct kv_power_info *pi = kv_get_pi(adev);
1647	struct amdgpu_clock_voltage_dependency_table *table =
1648		&adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
1649	int ret;
1650
1651	if (!gate) {
1652		if (pi->caps_stable_p_state)
1653			pi->acp_boot_level = table->count - 1;
1654		else
1655			pi->acp_boot_level = kv_get_acp_boot_level(adev);
1656
1657		ret = amdgpu_kv_copy_bytes_to_smc(adev,
1658					   pi->dpm_table_start +
1659					   offsetof(SMU7_Fusion_DpmTable, AcpBootLevel),
1660					   (u8 *)&pi->acp_boot_level,
1661					   sizeof(u8),
1662					   pi->sram_end);
1663		if (ret)
1664			return ret;
1665
1666		if (pi->caps_stable_p_state)
1667			amdgpu_kv_send_msg_to_smc_with_parameter(adev,
1668							  PPSMC_MSG_ACPDPM_SetEnabledMask,
1669							  (1 << pi->acp_boot_level));
1670	}
1671
1672	return kv_enable_acp_dpm(adev, !gate);
1673}
1674
1675static void kv_dpm_powergate_uvd(void *handle, bool gate)
1676{
1677	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1678	struct kv_power_info *pi = kv_get_pi(adev);
1679	int ret;
1680
1681	pi->uvd_power_gated = gate;
1682
1683	if (gate) {
1684		/* stop the UVD block */
1685		ret = amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1686							AMD_PG_STATE_GATE);
1687		kv_update_uvd_dpm(adev, gate);
1688		if (pi->caps_uvd_pg)
1689			/* power off the UVD block */
1690			amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_UVDPowerOFF);
1691	} else {
1692		if (pi->caps_uvd_pg)
1693			/* power on the UVD block */
1694			amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_UVDPowerON);
1695			/* re-init the UVD block */
1696		kv_update_uvd_dpm(adev, gate);
1697
1698		ret = amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
1699							AMD_PG_STATE_UNGATE);
1700	}
1701}
1702
1703static void kv_dpm_powergate_vce(struct amdgpu_device *adev, bool gate)
1704{
1705	struct kv_power_info *pi = kv_get_pi(adev);
1706
1707	if (pi->vce_power_gated == gate)
1708		return;
1709
1710	pi->vce_power_gated = gate;
1711
1712	if (!pi->caps_vce_pg)
1713		return;
1714
1715	if (gate)
1716		amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_VCEPowerOFF);
1717	else
1718		amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_VCEPowerON);
1719}
1720
1721static void kv_dpm_powergate_samu(struct amdgpu_device *adev, bool gate)
1722{
1723	struct kv_power_info *pi = kv_get_pi(adev);
1724
1725	if (pi->samu_power_gated == gate)
1726		return;
1727
1728	pi->samu_power_gated = gate;
1729
1730	if (gate) {
1731		kv_update_samu_dpm(adev, true);
1732		if (pi->caps_samu_pg)
1733			amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_SAMPowerOFF);
1734	} else {
1735		if (pi->caps_samu_pg)
1736			amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_SAMPowerON);
1737		kv_update_samu_dpm(adev, false);
1738	}
1739}
1740
1741static void kv_dpm_powergate_acp(struct amdgpu_device *adev, bool gate)
1742{
1743	struct kv_power_info *pi = kv_get_pi(adev);
1744
1745	if (pi->acp_power_gated == gate)
1746		return;
1747
1748	if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS)
1749		return;
1750
1751	pi->acp_power_gated = gate;
1752
1753	if (gate) {
1754		kv_update_acp_dpm(adev, true);
1755		if (pi->caps_acp_pg)
1756			amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_ACPPowerOFF);
1757	} else {
1758		if (pi->caps_acp_pg)
1759			amdgpu_kv_notify_message_to_smu(adev, PPSMC_MSG_ACPPowerON);
1760		kv_update_acp_dpm(adev, false);
1761	}
1762}
1763
1764static void kv_set_valid_clock_range(struct amdgpu_device *adev,
1765				     struct amdgpu_ps *new_rps)
1766{
1767	struct kv_ps *new_ps = kv_get_ps(new_rps);
1768	struct kv_power_info *pi = kv_get_pi(adev);
1769	u32 i;
1770	struct amdgpu_clock_voltage_dependency_table *table =
1771		&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
1772
1773	if (table && table->count) {
1774		for (i = 0; i < pi->graphics_dpm_level_count; i++) {
1775			if ((table->entries[i].clk >= new_ps->levels[0].sclk) ||
1776			    (i == (pi->graphics_dpm_level_count - 1))) {
1777				pi->lowest_valid = i;
1778				break;
1779			}
1780		}
1781
1782		for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) {
1783			if

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