/drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h

https://gitlab.com/sunny256/linux · C Header · 144 lines · 104 code · 18 blank · 22 comment · 0 complexity · be3c2243306d64f1b79c9878d75ed37c MD5 · raw file

  1. /*
  2. * Copyright 2017 Advanced Micro Devices, Inc.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20. * OTHER DEALINGS IN THE SOFTWARE.
  21. *
  22. */
  23. #ifndef __MMSCH_V1_0_H__
  24. #define __MMSCH_V1_0_H__
  25. #define MMSCH_VERSION_MAJOR 1
  26. #define MMSCH_VERSION_MINOR 0
  27. #define MMSCH_VERSION (MMSCH_VERSION_MAJOR << 16 | MMSCH_VERSION_MINOR)
  28. enum mmsch_v1_0_command_type {
  29. MMSCH_COMMAND__DIRECT_REG_WRITE = 0,
  30. MMSCH_COMMAND__DIRECT_REG_POLLING = 2,
  31. MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE = 3,
  32. MMSCH_COMMAND__INDIRECT_REG_WRITE = 8,
  33. MMSCH_COMMAND__END = 0xf
  34. };
  35. struct mmsch_v1_0_init_header {
  36. uint32_t version;
  37. uint32_t header_size;
  38. uint32_t vce_init_status;
  39. uint32_t uvd_init_status;
  40. uint32_t vce_table_offset;
  41. uint32_t vce_table_size;
  42. uint32_t uvd_table_offset;
  43. uint32_t uvd_table_size;
  44. };
  45. struct mmsch_v1_0_cmd_direct_reg_header {
  46. uint32_t reg_offset : 28;
  47. uint32_t command_type : 4;
  48. };
  49. struct mmsch_v1_0_cmd_indirect_reg_header {
  50. uint32_t reg_offset : 20;
  51. uint32_t reg_idx_space : 8;
  52. uint32_t command_type : 4;
  53. };
  54. struct mmsch_v1_0_cmd_direct_write {
  55. struct mmsch_v1_0_cmd_direct_reg_header cmd_header;
  56. uint32_t reg_value;
  57. };
  58. struct mmsch_v1_0_cmd_direct_read_modify_write {
  59. struct mmsch_v1_0_cmd_direct_reg_header cmd_header;
  60. uint32_t write_data;
  61. uint32_t mask_value;
  62. };
  63. struct mmsch_v1_0_cmd_direct_polling {
  64. struct mmsch_v1_0_cmd_direct_reg_header cmd_header;
  65. uint32_t mask_value;
  66. uint32_t wait_value;
  67. };
  68. struct mmsch_v1_0_cmd_end {
  69. struct mmsch_v1_0_cmd_direct_reg_header cmd_header;
  70. };
  71. struct mmsch_v1_0_cmd_indirect_write {
  72. struct mmsch_v1_0_cmd_indirect_reg_header cmd_header;
  73. uint32_t reg_value;
  74. };
  75. static inline void mmsch_v1_0_insert_direct_wt(struct mmsch_v1_0_cmd_direct_write *direct_wt,
  76. uint32_t *init_table,
  77. uint32_t reg_offset,
  78. uint32_t value)
  79. {
  80. direct_wt->cmd_header.reg_offset = reg_offset;
  81. direct_wt->reg_value = value;
  82. memcpy((void *)init_table, direct_wt, sizeof(struct mmsch_v1_0_cmd_direct_write));
  83. }
  84. static inline void mmsch_v1_0_insert_direct_rd_mod_wt(struct mmsch_v1_0_cmd_direct_read_modify_write *direct_rd_mod_wt,
  85. uint32_t *init_table,
  86. uint32_t reg_offset,
  87. uint32_t mask, uint32_t data)
  88. {
  89. direct_rd_mod_wt->cmd_header.reg_offset = reg_offset;
  90. direct_rd_mod_wt->mask_value = mask;
  91. direct_rd_mod_wt->write_data = data;
  92. memcpy((void *)init_table, direct_rd_mod_wt,
  93. sizeof(struct mmsch_v1_0_cmd_direct_read_modify_write));
  94. }
  95. static inline void mmsch_v1_0_insert_direct_poll(struct mmsch_v1_0_cmd_direct_polling *direct_poll,
  96. uint32_t *init_table,
  97. uint32_t reg_offset,
  98. uint32_t mask, uint32_t wait)
  99. {
  100. direct_poll->cmd_header.reg_offset = reg_offset;
  101. direct_poll->mask_value = mask;
  102. direct_poll->wait_value = wait;
  103. memcpy((void *)init_table, direct_poll, sizeof(struct mmsch_v1_0_cmd_direct_polling));
  104. }
  105. #define MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(reg, mask, data) { \
  106. mmsch_v1_0_insert_direct_rd_mod_wt(&direct_rd_mod_wt, \
  107. init_table, (reg), \
  108. (mask), (data)); \
  109. init_table += sizeof(struct mmsch_v1_0_cmd_direct_read_modify_write)/4; \
  110. table_size += sizeof(struct mmsch_v1_0_cmd_direct_read_modify_write)/4; \
  111. }
  112. #define MMSCH_V1_0_INSERT_DIRECT_WT(reg, value) { \
  113. mmsch_v1_0_insert_direct_wt(&direct_wt, \
  114. init_table, (reg), \
  115. (value)); \
  116. init_table += sizeof(struct mmsch_v1_0_cmd_direct_write)/4; \
  117. table_size += sizeof(struct mmsch_v1_0_cmd_direct_write)/4; \
  118. }
  119. #define MMSCH_V1_0_INSERT_DIRECT_POLL(reg, mask, wait) { \
  120. mmsch_v1_0_insert_direct_poll(&direct_poll, \
  121. init_table, (reg), \
  122. (mask), (wait)); \
  123. init_table += sizeof(struct mmsch_v1_0_cmd_direct_polling)/4; \
  124. table_size += sizeof(struct mmsch_v1_0_cmd_direct_polling)/4; \
  125. }
  126. #endif