/board/exmeritus/hww1u1a/gpios.h

https://gitlab.com/veo-labs/u-boot · C Header · 56 lines · 41 code · 6 blank · 9 comment · 0 complexity · a9bb0cf03810ab6c7f62167cff7fb930 MD5 · raw file 

    

  1. /*
    2. 

  2.  * Copyright 2010 eXMeritus, A Boeing Company
    3. 

  3.  *
    4. 

  4.  * SPDX-License-Identifier:	GPL-2.0+
    5. 

  5.  */
    6. 

  6. 

  7. #include <asm/mpc85xx_gpio.h>
    8. 

  8. 

  9. /* Common CPU A/B GPIOs (GPIO8-GPIO15 and IRQ4-IRQ6) */
    10. 

  10. #define GPIO_CPU_ID		(1UL << (31 -  8))
    11. 

  11. #define GPIO_BLUE_LED		(1UL << (31 -  9))
    12. 

  12. #define GPIO_DIMM_RESET		(1UL << (31 - 10))
    13. 

  13. #define GPIO_USB_RESET		(1UL << (31 - 11))
    14. 

  14. #define GPIO_UNUSED_12		(1UL << (31 - 12))
    15. 

  15. #define GPIO_GETH0_RESET	(1UL << (31 - 13))
    16. 

  16. #define GPIO_RS422_RE		(1UL << (31 - 14))
    17. 

  17. #define GPIO_RS422_DE		(1UL << (31 - 15))
    18. 

  18. #define IRQ_I2CINT		(1UL << (31 - 20))
    19. 

  19. #define IRQ_FANINT		(1UL << (31 - 21))
    20. 

  20. #define IRQ_DIMM_EVENT		(1UL << (31 - 22))
    21. 

  21. 

  22. #define GPIO_RESETS (GPIO_DIMM_RESET|GPIO_USB_RESET|GPIO_GETH0_RESET)
    23. 

  23. 

  24. /* CPU A GPIOS (GPIO0-GPIO7 and IRQ0-IRQ3) */
    25. 

  25. #define GPIO_CPUA_UNUSED_0	(1UL << (31 -  0))
    26. 

  26. #define GPIO_CPUA_CPU_READY	(1UL << (31 -  1))
    27. 

  27. #define GPIO_CPUA_DEBUG_LED2	(1UL << (31 -  2))
    28. 

  28. #define GPIO_CPUA_DEBUG_LED1	(1UL << (31 -  3))
    29. 

  29. #define GPIO_CPUA_TDIS2B	(1UL << (31 -  4)) /* MAC 2 TX B */
    30. 

  30. #define GPIO_CPUA_TDIS2A	(1UL << (31 -  5)) /* MAC 2 TX A */
    31. 

  31. #define GPIO_CPUA_TDIS1B	(1UL << (31 -  6)) /* MAC 1 TX B */
    32. 

  32. #define GPIO_CPUA_TDIS1A	(1UL << (31 -  7)) /* MAC 1 TX A */
    33. 

  33. #define IRQ_CPUA_UNUSED_0	(1UL << (31 - 16))
    34. 

  34. #define IRQ_CPUA_UNUSED_1	(1UL << (31 - 17))
    35. 

  35. #define IRQ_CPUA_UNUSED_2	(1UL << (31 - 18))
    36. 

  36. #define IRQ_CPUA_UNUSED_3	(1UL << (31 - 19))
    37. 

  37. 

  38. /* CPU B GPIOS (GPIO0-GPIO7 and IRQ0-IRQ3) */
    39. 

  39. #define GPIO_CPUB_RMUX_SEL1B	(1UL << (31 -  0))
    40. 

  40. #define GPIO_CPUB_RMUX_SEL0B	(1UL << (31 -  1))
    41. 

  41. #define GPIO_CPUB_RMUX_SEL1A	(1UL << (31 -  2))
    42. 

  42. #define GPIO_CPUB_RMUX_SEL0A	(1UL << (31 -  3))
    43. 

  43. #define GPIO_CPUB_UNUSED_4	(1UL << (31 -  4))
    44. 

  44. #define GPIO_CPUB_CPU_READY	(1UL << (31 -  5))
    45. 

  45. #define GPIO_CPUB_DEBUG_LED2	(1UL << (31 -  6))
    46. 

  46. #define GPIO_CPUB_DEBUG_LED1	(1UL << (31 -  7))
    47. 

  47. #define IRQ_CPUB_SD_1A		(1UL << (31 - 16))
    48. 

  48. #define IRQ_CPUB_SD_2B		(1UL << (31 - 17))
    49. 

  49. #define IRQ_CPUB_SD_2A		(1UL << (31 - 18))
    50. 

  50. #define IRQ_CPUB_SD_1B		(1UL << (31 - 19))
    51. 

  51. 

  52. /* If it isn't CPU A then it's CPU B */
    53. 

  53. static inline unsigned int hww1u1a_is_cpu_a(void)
    54. 

  54. {
    55. 

  55. 	return !mpc85xx_gpio_get(GPIO_CPU_ID);
    56. 

  56. }
    57.