/drivers/net/niu.c
C | 10280 lines | 8345 code | 1773 blank | 162 comment | 1373 complexity | d9a6bc9cffd37c042abc656e8c81341e MD5 | raw file
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1/* niu.c: Neptune ethernet driver. 2 * 3 * Copyright (C) 2007, 2008 David S. Miller (davem@davemloft.net) 4 */ 5 6#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 7 8#include <linux/module.h> 9#include <linux/init.h> 10#include <linux/pci.h> 11#include <linux/dma-mapping.h> 12#include <linux/netdevice.h> 13#include <linux/ethtool.h> 14#include <linux/etherdevice.h> 15#include <linux/platform_device.h> 16#include <linux/delay.h> 17#include <linux/bitops.h> 18#include <linux/mii.h> 19#include <linux/if_ether.h> 20#include <linux/if_vlan.h> 21#include <linux/ip.h> 22#include <linux/in.h> 23#include <linux/ipv6.h> 24#include <linux/log2.h> 25#include <linux/jiffies.h> 26#include <linux/crc32.h> 27#include <linux/list.h> 28#include <linux/slab.h> 29 30#include <linux/io.h> 31 32#ifdef CONFIG_SPARC64 33#include <linux/of_device.h> 34#endif 35 36#include "niu.h" 37 38#define DRV_MODULE_NAME "niu" 39#define DRV_MODULE_VERSION "1.1" 40#define DRV_MODULE_RELDATE "Apr 22, 2010" 41 42static char version[] __devinitdata = 43 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n"; 44 45MODULE_AUTHOR("David S. Miller (davem@davemloft.net)"); 46MODULE_DESCRIPTION("NIU ethernet driver"); 47MODULE_LICENSE("GPL"); 48MODULE_VERSION(DRV_MODULE_VERSION); 49 50#ifndef readq 51static u64 readq(void __iomem *reg) 52{ 53 return ((u64) readl(reg)) | (((u64) readl(reg + 4UL)) << 32); 54} 55 56static void writeq(u64 val, void __iomem *reg) 57{ 58 writel(val & 0xffffffff, reg); 59 writel(val >> 32, reg + 0x4UL); 60} 61#endif 62 63static DEFINE_PCI_DEVICE_TABLE(niu_pci_tbl) = { 64 {PCI_DEVICE(PCI_VENDOR_ID_SUN, 0xabcd)}, 65 {} 66}; 67 68MODULE_DEVICE_TABLE(pci, niu_pci_tbl); 69 70#define NIU_TX_TIMEOUT (5 * HZ) 71 72#define nr64(reg) readq(np->regs + (reg)) 73#define nw64(reg, val) writeq((val), np->regs + (reg)) 74 75#define nr64_mac(reg) readq(np->mac_regs + (reg)) 76#define nw64_mac(reg, val) writeq((val), np->mac_regs + (reg)) 77 78#define nr64_ipp(reg) readq(np->regs + np->ipp_off + (reg)) 79#define nw64_ipp(reg, val) writeq((val), np->regs + np->ipp_off + (reg)) 80 81#define nr64_pcs(reg) readq(np->regs + np->pcs_off + (reg)) 82#define nw64_pcs(reg, val) writeq((val), np->regs + np->pcs_off + (reg)) 83 84#define nr64_xpcs(reg) readq(np->regs + np->xpcs_off + (reg)) 85#define nw64_xpcs(reg, val) writeq((val), np->regs + np->xpcs_off + (reg)) 86 87#define NIU_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK) 88 89static int niu_debug; 90static int debug = -1; 91module_param(debug, int, 0); 92MODULE_PARM_DESC(debug, "NIU debug level"); 93 94#define niu_lock_parent(np, flags) \ 95 spin_lock_irqsave(&np->parent->lock, flags) 96#define niu_unlock_parent(np, flags) \ 97 spin_unlock_irqrestore(&np->parent->lock, flags) 98 99static int serdes_init_10g_serdes(struct niu *np); 100 101static int __niu_wait_bits_clear_mac(struct niu *np, unsigned long reg, 102 u64 bits, int limit, int delay) 103{ 104 while (--limit >= 0) { 105 u64 val = nr64_mac(reg); 106 107 if (!(val & bits)) 108 break; 109 udelay(delay); 110 } 111 if (limit < 0) 112 return -ENODEV; 113 return 0; 114} 115 116static int __niu_set_and_wait_clear_mac(struct niu *np, unsigned long reg, 117 u64 bits, int limit, int delay, 118 const char *reg_name) 119{ 120 int err; 121 122 nw64_mac(reg, bits); 123 err = __niu_wait_bits_clear_mac(np, reg, bits, limit, delay); 124 if (err) 125 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n", 126 (unsigned long long)bits, reg_name, 127 (unsigned long long)nr64_mac(reg)); 128 return err; 129} 130 131#define niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \ 132({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \ 133 __niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \ 134}) 135 136static int __niu_wait_bits_clear_ipp(struct niu *np, unsigned long reg, 137 u64 bits, int limit, int delay) 138{ 139 while (--limit >= 0) { 140 u64 val = nr64_ipp(reg); 141 142 if (!(val & bits)) 143 break; 144 udelay(delay); 145 } 146 if (limit < 0) 147 return -ENODEV; 148 return 0; 149} 150 151static int __niu_set_and_wait_clear_ipp(struct niu *np, unsigned long reg, 152 u64 bits, int limit, int delay, 153 const char *reg_name) 154{ 155 int err; 156 u64 val; 157 158 val = nr64_ipp(reg); 159 val |= bits; 160 nw64_ipp(reg, val); 161 162 err = __niu_wait_bits_clear_ipp(np, reg, bits, limit, delay); 163 if (err) 164 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n", 165 (unsigned long long)bits, reg_name, 166 (unsigned long long)nr64_ipp(reg)); 167 return err; 168} 169 170#define niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \ 171({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \ 172 __niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \ 173}) 174 175static int __niu_wait_bits_clear(struct niu *np, unsigned long reg, 176 u64 bits, int limit, int delay) 177{ 178 while (--limit >= 0) { 179 u64 val = nr64(reg); 180 181 if (!(val & bits)) 182 break; 183 udelay(delay); 184 } 185 if (limit < 0) 186 return -ENODEV; 187 return 0; 188} 189 190#define niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY) \ 191({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \ 192 __niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY); \ 193}) 194 195static int __niu_set_and_wait_clear(struct niu *np, unsigned long reg, 196 u64 bits, int limit, int delay, 197 const char *reg_name) 198{ 199 int err; 200 201 nw64(reg, bits); 202 err = __niu_wait_bits_clear(np, reg, bits, limit, delay); 203 if (err) 204 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n", 205 (unsigned long long)bits, reg_name, 206 (unsigned long long)nr64(reg)); 207 return err; 208} 209 210#define niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \ 211({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \ 212 __niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \ 213}) 214 215static void niu_ldg_rearm(struct niu *np, struct niu_ldg *lp, int on) 216{ 217 u64 val = (u64) lp->timer; 218 219 if (on) 220 val |= LDG_IMGMT_ARM; 221 222 nw64(LDG_IMGMT(lp->ldg_num), val); 223} 224 225static int niu_ldn_irq_enable(struct niu *np, int ldn, int on) 226{ 227 unsigned long mask_reg, bits; 228 u64 val; 229 230 if (ldn < 0 || ldn > LDN_MAX) 231 return -EINVAL; 232 233 if (ldn < 64) { 234 mask_reg = LD_IM0(ldn); 235 bits = LD_IM0_MASK; 236 } else { 237 mask_reg = LD_IM1(ldn - 64); 238 bits = LD_IM1_MASK; 239 } 240 241 val = nr64(mask_reg); 242 if (on) 243 val &= ~bits; 244 else 245 val |= bits; 246 nw64(mask_reg, val); 247 248 return 0; 249} 250 251static int niu_enable_ldn_in_ldg(struct niu *np, struct niu_ldg *lp, int on) 252{ 253 struct niu_parent *parent = np->parent; 254 int i; 255 256 for (i = 0; i <= LDN_MAX; i++) { 257 int err; 258 259 if (parent->ldg_map[i] != lp->ldg_num) 260 continue; 261 262 err = niu_ldn_irq_enable(np, i, on); 263 if (err) 264 return err; 265 } 266 return 0; 267} 268 269static int niu_enable_interrupts(struct niu *np, int on) 270{ 271 int i; 272 273 for (i = 0; i < np->num_ldg; i++) { 274 struct niu_ldg *lp = &np->ldg[i]; 275 int err; 276 277 err = niu_enable_ldn_in_ldg(np, lp, on); 278 if (err) 279 return err; 280 } 281 for (i = 0; i < np->num_ldg; i++) 282 niu_ldg_rearm(np, &np->ldg[i], on); 283 284 return 0; 285} 286 287static u32 phy_encode(u32 type, int port) 288{ 289 return (type << (port * 2)); 290} 291 292static u32 phy_decode(u32 val, int port) 293{ 294 return (val >> (port * 2)) & PORT_TYPE_MASK; 295} 296 297static int mdio_wait(struct niu *np) 298{ 299 int limit = 1000; 300 u64 val; 301 302 while (--limit > 0) { 303 val = nr64(MIF_FRAME_OUTPUT); 304 if ((val >> MIF_FRAME_OUTPUT_TA_SHIFT) & 0x1) 305 return val & MIF_FRAME_OUTPUT_DATA; 306 307 udelay(10); 308 } 309 310 return -ENODEV; 311} 312 313static int mdio_read(struct niu *np, int port, int dev, int reg) 314{ 315 int err; 316 317 nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg)); 318 err = mdio_wait(np); 319 if (err < 0) 320 return err; 321 322 nw64(MIF_FRAME_OUTPUT, MDIO_READ_OP(port, dev)); 323 return mdio_wait(np); 324} 325 326static int mdio_write(struct niu *np, int port, int dev, int reg, int data) 327{ 328 int err; 329 330 nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg)); 331 err = mdio_wait(np); 332 if (err < 0) 333 return err; 334 335 nw64(MIF_FRAME_OUTPUT, MDIO_WRITE_OP(port, dev, data)); 336 err = mdio_wait(np); 337 if (err < 0) 338 return err; 339 340 return 0; 341} 342 343static int mii_read(struct niu *np, int port, int reg) 344{ 345 nw64(MIF_FRAME_OUTPUT, MII_READ_OP(port, reg)); 346 return mdio_wait(np); 347} 348 349static int mii_write(struct niu *np, int port, int reg, int data) 350{ 351 int err; 352 353 nw64(MIF_FRAME_OUTPUT, MII_WRITE_OP(port, reg, data)); 354 err = mdio_wait(np); 355 if (err < 0) 356 return err; 357 358 return 0; 359} 360 361static int esr2_set_tx_cfg(struct niu *np, unsigned long channel, u32 val) 362{ 363 int err; 364 365 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR, 366 ESR2_TI_PLL_TX_CFG_L(channel), 367 val & 0xffff); 368 if (!err) 369 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR, 370 ESR2_TI_PLL_TX_CFG_H(channel), 371 val >> 16); 372 return err; 373} 374 375static int esr2_set_rx_cfg(struct niu *np, unsigned long channel, u32 val) 376{ 377 int err; 378 379 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR, 380 ESR2_TI_PLL_RX_CFG_L(channel), 381 val & 0xffff); 382 if (!err) 383 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR, 384 ESR2_TI_PLL_RX_CFG_H(channel), 385 val >> 16); 386 return err; 387} 388 389/* Mode is always 10G fiber. */ 390static int serdes_init_niu_10g_fiber(struct niu *np) 391{ 392 struct niu_link_config *lp = &np->link_config; 393 u32 tx_cfg, rx_cfg; 394 unsigned long i; 395 396 tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV); 397 rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT | 398 PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH | 399 PLL_RX_CFG_EQ_LP_ADAPTIVE); 400 401 if (lp->loopback_mode == LOOPBACK_PHY) { 402 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS; 403 404 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR, 405 ESR2_TI_PLL_TEST_CFG_L, test_cfg); 406 407 tx_cfg |= PLL_TX_CFG_ENTEST; 408 rx_cfg |= PLL_RX_CFG_ENTEST; 409 } 410 411 /* Initialize all 4 lanes of the SERDES. */ 412 for (i = 0; i < 4; i++) { 413 int err = esr2_set_tx_cfg(np, i, tx_cfg); 414 if (err) 415 return err; 416 } 417 418 for (i = 0; i < 4; i++) { 419 int err = esr2_set_rx_cfg(np, i, rx_cfg); 420 if (err) 421 return err; 422 } 423 424 return 0; 425} 426 427static int serdes_init_niu_1g_serdes(struct niu *np) 428{ 429 struct niu_link_config *lp = &np->link_config; 430 u16 pll_cfg, pll_sts; 431 int max_retry = 100; 432 u64 uninitialized_var(sig), mask, val; 433 u32 tx_cfg, rx_cfg; 434 unsigned long i; 435 int err; 436 437 tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV | 438 PLL_TX_CFG_RATE_HALF); 439 rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT | 440 PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH | 441 PLL_RX_CFG_RATE_HALF); 442 443 if (np->port == 0) 444 rx_cfg |= PLL_RX_CFG_EQ_LP_ADAPTIVE; 445 446 if (lp->loopback_mode == LOOPBACK_PHY) { 447 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS; 448 449 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR, 450 ESR2_TI_PLL_TEST_CFG_L, test_cfg); 451 452 tx_cfg |= PLL_TX_CFG_ENTEST; 453 rx_cfg |= PLL_RX_CFG_ENTEST; 454 } 455 456 /* Initialize PLL for 1G */ 457 pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_8X); 458 459 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR, 460 ESR2_TI_PLL_CFG_L, pll_cfg); 461 if (err) { 462 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_CFG_L failed\n", 463 np->port, __func__); 464 return err; 465 } 466 467 pll_sts = PLL_CFG_ENPLL; 468 469 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR, 470 ESR2_TI_PLL_STS_L, pll_sts); 471 if (err) { 472 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_STS_L failed\n", 473 np->port, __func__); 474 return err; 475 } 476 477 udelay(200); 478 479 /* Initialize all 4 lanes of the SERDES. */ 480 for (i = 0; i < 4; i++) { 481 err = esr2_set_tx_cfg(np, i, tx_cfg); 482 if (err) 483 return err; 484 } 485 486 for (i = 0; i < 4; i++) { 487 err = esr2_set_rx_cfg(np, i, rx_cfg); 488 if (err) 489 return err; 490 } 491 492 switch (np->port) { 493 case 0: 494 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0); 495 mask = val; 496 break; 497 498 case 1: 499 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1); 500 mask = val; 501 break; 502 503 default: 504 return -EINVAL; 505 } 506 507 while (max_retry--) { 508 sig = nr64(ESR_INT_SIGNALS); 509 if ((sig & mask) == val) 510 break; 511 512 mdelay(500); 513 } 514 515 if ((sig & mask) != val) { 516 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n", 517 np->port, (int)(sig & mask), (int)val); 518 return -ENODEV; 519 } 520 521 return 0; 522} 523 524static int serdes_init_niu_10g_serdes(struct niu *np) 525{ 526 struct niu_link_config *lp = &np->link_config; 527 u32 tx_cfg, rx_cfg, pll_cfg, pll_sts; 528 int max_retry = 100; 529 u64 uninitialized_var(sig), mask, val; 530 unsigned long i; 531 int err; 532 533 tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV); 534 rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT | 535 PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH | 536 PLL_RX_CFG_EQ_LP_ADAPTIVE); 537 538 if (lp->loopback_mode == LOOPBACK_PHY) { 539 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS; 540 541 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR, 542 ESR2_TI_PLL_TEST_CFG_L, test_cfg); 543 544 tx_cfg |= PLL_TX_CFG_ENTEST; 545 rx_cfg |= PLL_RX_CFG_ENTEST; 546 } 547 548 /* Initialize PLL for 10G */ 549 pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_10X); 550 551 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR, 552 ESR2_TI_PLL_CFG_L, pll_cfg & 0xffff); 553 if (err) { 554 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_CFG_L failed\n", 555 np->port, __func__); 556 return err; 557 } 558 559 pll_sts = PLL_CFG_ENPLL; 560 561 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR, 562 ESR2_TI_PLL_STS_L, pll_sts & 0xffff); 563 if (err) { 564 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_STS_L failed\n", 565 np->port, __func__); 566 return err; 567 } 568 569 udelay(200); 570 571 /* Initialize all 4 lanes of the SERDES. */ 572 for (i = 0; i < 4; i++) { 573 err = esr2_set_tx_cfg(np, i, tx_cfg); 574 if (err) 575 return err; 576 } 577 578 for (i = 0; i < 4; i++) { 579 err = esr2_set_rx_cfg(np, i, rx_cfg); 580 if (err) 581 return err; 582 } 583 584 /* check if serdes is ready */ 585 586 switch (np->port) { 587 case 0: 588 mask = ESR_INT_SIGNALS_P0_BITS; 589 val = (ESR_INT_SRDY0_P0 | 590 ESR_INT_DET0_P0 | 591 ESR_INT_XSRDY_P0 | 592 ESR_INT_XDP_P0_CH3 | 593 ESR_INT_XDP_P0_CH2 | 594 ESR_INT_XDP_P0_CH1 | 595 ESR_INT_XDP_P0_CH0); 596 break; 597 598 case 1: 599 mask = ESR_INT_SIGNALS_P1_BITS; 600 val = (ESR_INT_SRDY0_P1 | 601 ESR_INT_DET0_P1 | 602 ESR_INT_XSRDY_P1 | 603 ESR_INT_XDP_P1_CH3 | 604 ESR_INT_XDP_P1_CH2 | 605 ESR_INT_XDP_P1_CH1 | 606 ESR_INT_XDP_P1_CH0); 607 break; 608 609 default: 610 return -EINVAL; 611 } 612 613 while (max_retry--) { 614 sig = nr64(ESR_INT_SIGNALS); 615 if ((sig & mask) == val) 616 break; 617 618 mdelay(500); 619 } 620 621 if ((sig & mask) != val) { 622 pr_info("NIU Port %u signal bits [%08x] are not [%08x] for 10G...trying 1G\n", 623 np->port, (int)(sig & mask), (int)val); 624 625 /* 10G failed, try initializing at 1G */ 626 err = serdes_init_niu_1g_serdes(np); 627 if (!err) { 628 np->flags &= ~NIU_FLAGS_10G; 629 np->mac_xcvr = MAC_XCVR_PCS; 630 } else { 631 netdev_err(np->dev, "Port %u 10G/1G SERDES Link Failed\n", 632 np->port); 633 return -ENODEV; 634 } 635 } 636 return 0; 637} 638 639static int esr_read_rxtx_ctrl(struct niu *np, unsigned long chan, u32 *val) 640{ 641 int err; 642 643 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, ESR_RXTX_CTRL_L(chan)); 644 if (err >= 0) { 645 *val = (err & 0xffff); 646 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, 647 ESR_RXTX_CTRL_H(chan)); 648 if (err >= 0) 649 *val |= ((err & 0xffff) << 16); 650 err = 0; 651 } 652 return err; 653} 654 655static int esr_read_glue0(struct niu *np, unsigned long chan, u32 *val) 656{ 657 int err; 658 659 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, 660 ESR_GLUE_CTRL0_L(chan)); 661 if (err >= 0) { 662 *val = (err & 0xffff); 663 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, 664 ESR_GLUE_CTRL0_H(chan)); 665 if (err >= 0) { 666 *val |= ((err & 0xffff) << 16); 667 err = 0; 668 } 669 } 670 return err; 671} 672 673static int esr_read_reset(struct niu *np, u32 *val) 674{ 675 int err; 676 677 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, 678 ESR_RXTX_RESET_CTRL_L); 679 if (err >= 0) { 680 *val = (err & 0xffff); 681 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, 682 ESR_RXTX_RESET_CTRL_H); 683 if (err >= 0) { 684 *val |= ((err & 0xffff) << 16); 685 err = 0; 686 } 687 } 688 return err; 689} 690 691static int esr_write_rxtx_ctrl(struct niu *np, unsigned long chan, u32 val) 692{ 693 int err; 694 695 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR, 696 ESR_RXTX_CTRL_L(chan), val & 0xffff); 697 if (!err) 698 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR, 699 ESR_RXTX_CTRL_H(chan), (val >> 16)); 700 return err; 701} 702 703static int esr_write_glue0(struct niu *np, unsigned long chan, u32 val) 704{ 705 int err; 706 707 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR, 708 ESR_GLUE_CTRL0_L(chan), val & 0xffff); 709 if (!err) 710 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR, 711 ESR_GLUE_CTRL0_H(chan), (val >> 16)); 712 return err; 713} 714 715static int esr_reset(struct niu *np) 716{ 717 u32 uninitialized_var(reset); 718 int err; 719 720 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR, 721 ESR_RXTX_RESET_CTRL_L, 0x0000); 722 if (err) 723 return err; 724 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR, 725 ESR_RXTX_RESET_CTRL_H, 0xffff); 726 if (err) 727 return err; 728 udelay(200); 729 730 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR, 731 ESR_RXTX_RESET_CTRL_L, 0xffff); 732 if (err) 733 return err; 734 udelay(200); 735 736 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR, 737 ESR_RXTX_RESET_CTRL_H, 0x0000); 738 if (err) 739 return err; 740 udelay(200); 741 742 err = esr_read_reset(np, &reset); 743 if (err) 744 return err; 745 if (reset != 0) { 746 netdev_err(np->dev, "Port %u ESR_RESET did not clear [%08x]\n", 747 np->port, reset); 748 return -ENODEV; 749 } 750 751 return 0; 752} 753 754static int serdes_init_10g(struct niu *np) 755{ 756 struct niu_link_config *lp = &np->link_config; 757 unsigned long ctrl_reg, test_cfg_reg, i; 758 u64 ctrl_val, test_cfg_val, sig, mask, val; 759 int err; 760 761 switch (np->port) { 762 case 0: 763 ctrl_reg = ENET_SERDES_0_CTRL_CFG; 764 test_cfg_reg = ENET_SERDES_0_TEST_CFG; 765 break; 766 case 1: 767 ctrl_reg = ENET_SERDES_1_CTRL_CFG; 768 test_cfg_reg = ENET_SERDES_1_TEST_CFG; 769 break; 770 771 default: 772 return -EINVAL; 773 } 774 ctrl_val = (ENET_SERDES_CTRL_SDET_0 | 775 ENET_SERDES_CTRL_SDET_1 | 776 ENET_SERDES_CTRL_SDET_2 | 777 ENET_SERDES_CTRL_SDET_3 | 778 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) | 779 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) | 780 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) | 781 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) | 782 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) | 783 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) | 784 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) | 785 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT)); 786 test_cfg_val = 0; 787 788 if (lp->loopback_mode == LOOPBACK_PHY) { 789 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK << 790 ENET_SERDES_TEST_MD_0_SHIFT) | 791 (ENET_TEST_MD_PAD_LOOPBACK << 792 ENET_SERDES_TEST_MD_1_SHIFT) | 793 (ENET_TEST_MD_PAD_LOOPBACK << 794 ENET_SERDES_TEST_MD_2_SHIFT) | 795 (ENET_TEST_MD_PAD_LOOPBACK << 796 ENET_SERDES_TEST_MD_3_SHIFT)); 797 } 798 799 nw64(ctrl_reg, ctrl_val); 800 nw64(test_cfg_reg, test_cfg_val); 801 802 /* Initialize all 4 lanes of the SERDES. */ 803 for (i = 0; i < 4; i++) { 804 u32 rxtx_ctrl, glue0; 805 806 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl); 807 if (err) 808 return err; 809 err = esr_read_glue0(np, i, &glue0); 810 if (err) 811 return err; 812 813 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO); 814 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH | 815 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT)); 816 817 glue0 &= ~(ESR_GLUE_CTRL0_SRATE | 818 ESR_GLUE_CTRL0_THCNT | 819 ESR_GLUE_CTRL0_BLTIME); 820 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB | 821 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) | 822 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) | 823 (BLTIME_300_CYCLES << 824 ESR_GLUE_CTRL0_BLTIME_SHIFT)); 825 826 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl); 827 if (err) 828 return err; 829 err = esr_write_glue0(np, i, glue0); 830 if (err) 831 return err; 832 } 833 834 err = esr_reset(np); 835 if (err) 836 return err; 837 838 sig = nr64(ESR_INT_SIGNALS); 839 switch (np->port) { 840 case 0: 841 mask = ESR_INT_SIGNALS_P0_BITS; 842 val = (ESR_INT_SRDY0_P0 | 843 ESR_INT_DET0_P0 | 844 ESR_INT_XSRDY_P0 | 845 ESR_INT_XDP_P0_CH3 | 846 ESR_INT_XDP_P0_CH2 | 847 ESR_INT_XDP_P0_CH1 | 848 ESR_INT_XDP_P0_CH0); 849 break; 850 851 case 1: 852 mask = ESR_INT_SIGNALS_P1_BITS; 853 val = (ESR_INT_SRDY0_P1 | 854 ESR_INT_DET0_P1 | 855 ESR_INT_XSRDY_P1 | 856 ESR_INT_XDP_P1_CH3 | 857 ESR_INT_XDP_P1_CH2 | 858 ESR_INT_XDP_P1_CH1 | 859 ESR_INT_XDP_P1_CH0); 860 break; 861 862 default: 863 return -EINVAL; 864 } 865 866 if ((sig & mask) != val) { 867 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) { 868 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT; 869 return 0; 870 } 871 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n", 872 np->port, (int)(sig & mask), (int)val); 873 return -ENODEV; 874 } 875 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) 876 np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT; 877 return 0; 878} 879 880static int serdes_init_1g(struct niu *np) 881{ 882 u64 val; 883 884 val = nr64(ENET_SERDES_1_PLL_CFG); 885 val &= ~ENET_SERDES_PLL_FBDIV2; 886 switch (np->port) { 887 case 0: 888 val |= ENET_SERDES_PLL_HRATE0; 889 break; 890 case 1: 891 val |= ENET_SERDES_PLL_HRATE1; 892 break; 893 case 2: 894 val |= ENET_SERDES_PLL_HRATE2; 895 break; 896 case 3: 897 val |= ENET_SERDES_PLL_HRATE3; 898 break; 899 default: 900 return -EINVAL; 901 } 902 nw64(ENET_SERDES_1_PLL_CFG, val); 903 904 return 0; 905} 906 907static int serdes_init_1g_serdes(struct niu *np) 908{ 909 struct niu_link_config *lp = &np->link_config; 910 unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i; 911 u64 ctrl_val, test_cfg_val, sig, mask, val; 912 int err; 913 u64 reset_val, val_rd; 914 915 val = ENET_SERDES_PLL_HRATE0 | ENET_SERDES_PLL_HRATE1 | 916 ENET_SERDES_PLL_HRATE2 | ENET_SERDES_PLL_HRATE3 | 917 ENET_SERDES_PLL_FBDIV0; 918 switch (np->port) { 919 case 0: 920 reset_val = ENET_SERDES_RESET_0; 921 ctrl_reg = ENET_SERDES_0_CTRL_CFG; 922 test_cfg_reg = ENET_SERDES_0_TEST_CFG; 923 pll_cfg = ENET_SERDES_0_PLL_CFG; 924 break; 925 case 1: 926 reset_val = ENET_SERDES_RESET_1; 927 ctrl_reg = ENET_SERDES_1_CTRL_CFG; 928 test_cfg_reg = ENET_SERDES_1_TEST_CFG; 929 pll_cfg = ENET_SERDES_1_PLL_CFG; 930 break; 931 932 default: 933 return -EINVAL; 934 } 935 ctrl_val = (ENET_SERDES_CTRL_SDET_0 | 936 ENET_SERDES_CTRL_SDET_1 | 937 ENET_SERDES_CTRL_SDET_2 | 938 ENET_SERDES_CTRL_SDET_3 | 939 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) | 940 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) | 941 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) | 942 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) | 943 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) | 944 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) | 945 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) | 946 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT)); 947 test_cfg_val = 0; 948 949 if (lp->loopback_mode == LOOPBACK_PHY) { 950 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK << 951 ENET_SERDES_TEST_MD_0_SHIFT) | 952 (ENET_TEST_MD_PAD_LOOPBACK << 953 ENET_SERDES_TEST_MD_1_SHIFT) | 954 (ENET_TEST_MD_PAD_LOOPBACK << 955 ENET_SERDES_TEST_MD_2_SHIFT) | 956 (ENET_TEST_MD_PAD_LOOPBACK << 957 ENET_SERDES_TEST_MD_3_SHIFT)); 958 } 959 960 nw64(ENET_SERDES_RESET, reset_val); 961 mdelay(20); 962 val_rd = nr64(ENET_SERDES_RESET); 963 val_rd &= ~reset_val; 964 nw64(pll_cfg, val); 965 nw64(ctrl_reg, ctrl_val); 966 nw64(test_cfg_reg, test_cfg_val); 967 nw64(ENET_SERDES_RESET, val_rd); 968 mdelay(2000); 969 970 /* Initialize all 4 lanes of the SERDES. */ 971 for (i = 0; i < 4; i++) { 972 u32 rxtx_ctrl, glue0; 973 974 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl); 975 if (err) 976 return err; 977 err = esr_read_glue0(np, i, &glue0); 978 if (err) 979 return err; 980 981 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO); 982 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH | 983 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT)); 984 985 glue0 &= ~(ESR_GLUE_CTRL0_SRATE | 986 ESR_GLUE_CTRL0_THCNT | 987 ESR_GLUE_CTRL0_BLTIME); 988 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB | 989 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) | 990 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) | 991 (BLTIME_300_CYCLES << 992 ESR_GLUE_CTRL0_BLTIME_SHIFT)); 993 994 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl); 995 if (err) 996 return err; 997 err = esr_write_glue0(np, i, glue0); 998 if (err) 999 return err; 1000 } 1001 1002 1003 sig = nr64(ESR_INT_SIGNALS); 1004 switch (np->port) { 1005 case 0: 1006 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0); 1007 mask = val; 1008 break; 1009 1010 case 1: 1011 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1); 1012 mask = val; 1013 break; 1014 1015 default: 1016 return -EINVAL; 1017 } 1018 1019 if ((sig & mask) != val) { 1020 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n", 1021 np->port, (int)(sig & mask), (int)val); 1022 return -ENODEV; 1023 } 1024 1025 return 0; 1026} 1027 1028static int link_status_1g_serdes(struct niu *np, int *link_up_p) 1029{ 1030 struct niu_link_config *lp = &np->link_config; 1031 int link_up; 1032 u64 val; 1033 u16 current_speed; 1034 unsigned long flags; 1035 u8 current_duplex; 1036 1037 link_up = 0; 1038 current_speed = SPEED_INVALID; 1039 current_duplex = DUPLEX_INVALID; 1040 1041 spin_lock_irqsave(&np->lock, flags); 1042 1043 val = nr64_pcs(PCS_MII_STAT); 1044 1045 if (val & PCS_MII_STAT_LINK_STATUS) { 1046 link_up = 1; 1047 current_speed = SPEED_1000; 1048 current_duplex = DUPLEX_FULL; 1049 } 1050 1051 lp->active_speed = current_speed; 1052 lp->active_duplex = current_duplex; 1053 spin_unlock_irqrestore(&np->lock, flags); 1054 1055 *link_up_p = link_up; 1056 return 0; 1057} 1058 1059static int link_status_10g_serdes(struct niu *np, int *link_up_p) 1060{ 1061 unsigned long flags; 1062 struct niu_link_config *lp = &np->link_config; 1063 int link_up = 0; 1064 int link_ok = 1; 1065 u64 val, val2; 1066 u16 current_speed; 1067 u8 current_duplex; 1068 1069 if (!(np->flags & NIU_FLAGS_10G)) 1070 return link_status_1g_serdes(np, link_up_p); 1071 1072 current_speed = SPEED_INVALID; 1073 current_duplex = DUPLEX_INVALID; 1074 spin_lock_irqsave(&np->lock, flags); 1075 1076 val = nr64_xpcs(XPCS_STATUS(0)); 1077 val2 = nr64_mac(XMAC_INTER2); 1078 if (val2 & 0x01000000) 1079 link_ok = 0; 1080 1081 if ((val & 0x1000ULL) && link_ok) { 1082 link_up = 1; 1083 current_speed = SPEED_10000; 1084 current_duplex = DUPLEX_FULL; 1085 } 1086 lp->active_speed = current_speed; 1087 lp->active_duplex = current_duplex; 1088 spin_unlock_irqrestore(&np->lock, flags); 1089 *link_up_p = link_up; 1090 return 0; 1091} 1092 1093static int link_status_mii(struct niu *np, int *link_up_p) 1094{ 1095 struct niu_link_config *lp = &np->link_config; 1096 int err; 1097 int bmsr, advert, ctrl1000, stat1000, lpa, bmcr, estatus; 1098 int supported, advertising, active_speed, active_duplex; 1099 1100 err = mii_read(np, np->phy_addr, MII_BMCR); 1101 if (unlikely(err < 0)) 1102 return err; 1103 bmcr = err; 1104 1105 err = mii_read(np, np->phy_addr, MII_BMSR); 1106 if (unlikely(err < 0)) 1107 return err; 1108 bmsr = err; 1109 1110 err = mii_read(np, np->phy_addr, MII_ADVERTISE); 1111 if (unlikely(err < 0)) 1112 return err; 1113 advert = err; 1114 1115 err = mii_read(np, np->phy_addr, MII_LPA); 1116 if (unlikely(err < 0)) 1117 return err; 1118 lpa = err; 1119 1120 if (likely(bmsr & BMSR_ESTATEN)) { 1121 err = mii_read(np, np->phy_addr, MII_ESTATUS); 1122 if (unlikely(err < 0)) 1123 return err; 1124 estatus = err; 1125 1126 err = mii_read(np, np->phy_addr, MII_CTRL1000); 1127 if (unlikely(err < 0)) 1128 return err; 1129 ctrl1000 = err; 1130 1131 err = mii_read(np, np->phy_addr, MII_STAT1000); 1132 if (unlikely(err < 0)) 1133 return err; 1134 stat1000 = err; 1135 } else 1136 estatus = ctrl1000 = stat1000 = 0; 1137 1138 supported = 0; 1139 if (bmsr & BMSR_ANEGCAPABLE) 1140 supported |= SUPPORTED_Autoneg; 1141 if (bmsr & BMSR_10HALF) 1142 supported |= SUPPORTED_10baseT_Half; 1143 if (bmsr & BMSR_10FULL) 1144 supported |= SUPPORTED_10baseT_Full; 1145 if (bmsr & BMSR_100HALF) 1146 supported |= SUPPORTED_100baseT_Half; 1147 if (bmsr & BMSR_100FULL) 1148 supported |= SUPPORTED_100baseT_Full; 1149 if (estatus & ESTATUS_1000_THALF) 1150 supported |= SUPPORTED_1000baseT_Half; 1151 if (estatus & ESTATUS_1000_TFULL) 1152 supported |= SUPPORTED_1000baseT_Full; 1153 lp->supported = supported; 1154 1155 advertising = 0; 1156 if (advert & ADVERTISE_10HALF) 1157 advertising |= ADVERTISED_10baseT_Half; 1158 if (advert & ADVERTISE_10FULL) 1159 advertising |= ADVERTISED_10baseT_Full; 1160 if (advert & ADVERTISE_100HALF) 1161 advertising |= ADVERTISED_100baseT_Half; 1162 if (advert & ADVERTISE_100FULL) 1163 advertising |= ADVERTISED_100baseT_Full; 1164 if (ctrl1000 & ADVERTISE_1000HALF) 1165 advertising |= ADVERTISED_1000baseT_Half; 1166 if (ctrl1000 & ADVERTISE_1000FULL) 1167 advertising |= ADVERTISED_1000baseT_Full; 1168 1169 if (bmcr & BMCR_ANENABLE) { 1170 int neg, neg1000; 1171 1172 lp->active_autoneg = 1; 1173 advertising |= ADVERTISED_Autoneg; 1174 1175 neg = advert & lpa; 1176 neg1000 = (ctrl1000 << 2) & stat1000; 1177 1178 if (neg1000 & (LPA_1000FULL | LPA_1000HALF)) 1179 active_speed = SPEED_1000; 1180 else if (neg & LPA_100) 1181 active_speed = SPEED_100; 1182 else if (neg & (LPA_10HALF | LPA_10FULL)) 1183 active_speed = SPEED_10; 1184 else 1185 active_speed = SPEED_INVALID; 1186 1187 if ((neg1000 & LPA_1000FULL) || (neg & LPA_DUPLEX)) 1188 active_duplex = DUPLEX_FULL; 1189 else if (active_speed != SPEED_INVALID) 1190 active_duplex = DUPLEX_HALF; 1191 else 1192 active_duplex = DUPLEX_INVALID; 1193 } else { 1194 lp->active_autoneg = 0; 1195 1196 if ((bmcr & BMCR_SPEED1000) && !(bmcr & BMCR_SPEED100)) 1197 active_speed = SPEED_1000; 1198 else if (bmcr & BMCR_SPEED100) 1199 active_speed = SPEED_100; 1200 else 1201 active_speed = SPEED_10; 1202 1203 if (bmcr & BMCR_FULLDPLX) 1204 active_duplex = DUPLEX_FULL; 1205 else 1206 active_duplex = DUPLEX_HALF; 1207 } 1208 1209 lp->active_advertising = advertising; 1210 lp->active_speed = active_speed; 1211 lp->active_duplex = active_duplex; 1212 *link_up_p = !!(bmsr & BMSR_LSTATUS); 1213 1214 return 0; 1215} 1216 1217static int link_status_1g_rgmii(struct niu *np, int *link_up_p) 1218{ 1219 struct niu_link_config *lp = &np->link_config; 1220 u16 current_speed, bmsr; 1221 unsigned long flags; 1222 u8 current_duplex; 1223 int err, link_up; 1224 1225 link_up = 0; 1226 current_speed = SPEED_INVALID; 1227 current_duplex = DUPLEX_INVALID; 1228 1229 spin_lock_irqsave(&np->lock, flags); 1230 1231 err = -EINVAL; 1232 1233 err = mii_read(np, np->phy_addr, MII_BMSR); 1234 if (err < 0) 1235 goto out; 1236 1237 bmsr = err; 1238 if (bmsr & BMSR_LSTATUS) { 1239 u16 adv, lpa, common, estat; 1240 1241 err = mii_read(np, np->phy_addr, MII_ADVERTISE); 1242 if (err < 0) 1243 goto out; 1244 adv = err; 1245 1246 err = mii_read(np, np->phy_addr, MII_LPA); 1247 if (err < 0) 1248 goto out; 1249 lpa = err; 1250 1251 common = adv & lpa; 1252 1253 err = mii_read(np, np->phy_addr, MII_ESTATUS); 1254 if (err < 0) 1255 goto out; 1256 estat = err; 1257 link_up = 1; 1258 current_speed = SPEED_1000; 1259 current_duplex = DUPLEX_FULL; 1260 1261 } 1262 lp->active_speed = current_speed; 1263 lp->active_duplex = current_duplex; 1264 err = 0; 1265 1266out: 1267 spin_unlock_irqrestore(&np->lock, flags); 1268 1269 *link_up_p = link_up; 1270 return err; 1271} 1272 1273static int link_status_1g(struct niu *np, int *link_up_p) 1274{ 1275 struct niu_link_config *lp = &np->link_config; 1276 unsigned long flags; 1277 int err; 1278 1279 spin_lock_irqsave(&np->lock, flags); 1280 1281 err = link_status_mii(np, link_up_p); 1282 lp->supported |= SUPPORTED_TP; 1283 lp->active_advertising |= ADVERTISED_TP; 1284 1285 spin_unlock_irqrestore(&np->lock, flags); 1286 return err; 1287} 1288 1289static int bcm8704_reset(struct niu *np) 1290{ 1291 int err, limit; 1292 1293 err = mdio_read(np, np->phy_addr, 1294 BCM8704_PHYXS_DEV_ADDR, MII_BMCR); 1295 if (err < 0 || err == 0xffff) 1296 return err; 1297 err |= BMCR_RESET; 1298 err = mdio_write(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR, 1299 MII_BMCR, err); 1300 if (err) 1301 return err; 1302 1303 limit = 1000; 1304 while (--limit >= 0) { 1305 err = mdio_read(np, np->phy_addr, 1306 BCM8704_PHYXS_DEV_ADDR, MII_BMCR); 1307 if (err < 0) 1308 return err; 1309 if (!(err & BMCR_RESET)) 1310 break; 1311 } 1312 if (limit < 0) { 1313 netdev_err(np->dev, "Port %u PHY will not reset (bmcr=%04x)\n", 1314 np->port, (err & 0xffff)); 1315 return -ENODEV; 1316 } 1317 return 0; 1318} 1319 1320/* When written, certain PHY registers need to be read back twice 1321 * in order for the bits to settle properly. 1322 */ 1323static int bcm8704_user_dev3_readback(struct niu *np, int reg) 1324{ 1325 int err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg); 1326 if (err < 0) 1327 return err; 1328 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg); 1329 if (err < 0) 1330 return err; 1331 return 0; 1332} 1333 1334static int bcm8706_init_user_dev3(struct niu *np) 1335{ 1336 int err; 1337 1338 1339 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 1340 BCM8704_USER_OPT_DIGITAL_CTRL); 1341 if (err < 0) 1342 return err; 1343 err &= ~USER_ODIG_CTRL_GPIOS; 1344 err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT); 1345 err |= USER_ODIG_CTRL_RESV2; 1346 err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 1347 BCM8704_USER_OPT_DIGITAL_CTRL, err); 1348 if (err) 1349 return err; 1350 1351 mdelay(1000); 1352 1353 return 0; 1354} 1355 1356static int bcm8704_init_user_dev3(struct niu *np) 1357{ 1358 int err; 1359 1360 err = mdio_write(np, np->phy_addr, 1361 BCM8704_USER_DEV3_ADDR, BCM8704_USER_CONTROL, 1362 (USER_CONTROL_OPTXRST_LVL | 1363 USER_CONTROL_OPBIASFLT_LVL | 1364 USER_CONTROL_OBTMPFLT_LVL | 1365 USER_CONTROL_OPPRFLT_LVL | 1366 USER_CONTROL_OPTXFLT_LVL | 1367 USER_CONTROL_OPRXLOS_LVL | 1368 USER_CONTROL_OPRXFLT_LVL | 1369 USER_CONTROL_OPTXON_LVL | 1370 (0x3f << USER_CONTROL_RES1_SHIFT))); 1371 if (err) 1372 return err; 1373 1374 err = mdio_write(np, np->phy_addr, 1375 BCM8704_USER_DEV3_ADDR, BCM8704_USER_PMD_TX_CONTROL, 1376 (USER_PMD_TX_CTL_XFP_CLKEN | 1377 (1 << USER_PMD_TX_CTL_TX_DAC_TXD_SH) | 1378 (2 << USER_PMD_TX_CTL_TX_DAC_TXCK_SH) | 1379 USER_PMD_TX_CTL_TSCK_LPWREN)); 1380 if (err) 1381 return err; 1382 1383 err = bcm8704_user_dev3_readback(np, BCM8704_USER_CONTROL); 1384 if (err) 1385 return err; 1386 err = bcm8704_user_dev3_readback(np, BCM8704_USER_PMD_TX_CONTROL); 1387 if (err) 1388 return err; 1389 1390 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 1391 BCM8704_USER_OPT_DIGITAL_CTRL); 1392 if (err < 0) 1393 return err; 1394 err &= ~USER_ODIG_CTRL_GPIOS; 1395 err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT); 1396 err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 1397 BCM8704_USER_OPT_DIGITAL_CTRL, err); 1398 if (err) 1399 return err; 1400 1401 mdelay(1000); 1402 1403 return 0; 1404} 1405 1406static int mrvl88x2011_act_led(struct niu *np, int val) 1407{ 1408 int err; 1409 1410 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR, 1411 MRVL88X2011_LED_8_TO_11_CTL); 1412 if (err < 0) 1413 return err; 1414 1415 err &= ~MRVL88X2011_LED(MRVL88X2011_LED_ACT,MRVL88X2011_LED_CTL_MASK); 1416 err |= MRVL88X2011_LED(MRVL88X2011_LED_ACT,val); 1417 1418 return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR, 1419 MRVL88X2011_LED_8_TO_11_CTL, err); 1420} 1421 1422static int mrvl88x2011_led_blink_rate(struct niu *np, int rate) 1423{ 1424 int err; 1425 1426 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR, 1427 MRVL88X2011_LED_BLINK_CTL); 1428 if (err >= 0) { 1429 err &= ~MRVL88X2011_LED_BLKRATE_MASK; 1430 err |= (rate << 4); 1431 1432 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR, 1433 MRVL88X2011_LED_BLINK_CTL, err); 1434 } 1435 1436 return err; 1437} 1438 1439static int xcvr_init_10g_mrvl88x2011(struct niu *np) 1440{ 1441 int err; 1442 1443 /* Set LED functions */ 1444 err = mrvl88x2011_led_blink_rate(np, MRVL88X2011_LED_BLKRATE_134MS); 1445 if (err) 1446 return err; 1447 1448 /* led activity */ 1449 err = mrvl88x2011_act_led(np, MRVL88X2011_LED_CTL_OFF); 1450 if (err) 1451 return err; 1452 1453 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR, 1454 MRVL88X2011_GENERAL_CTL); 1455 if (err < 0) 1456 return err; 1457 1458 err |= MRVL88X2011_ENA_XFPREFCLK; 1459 1460 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR, 1461 MRVL88X2011_GENERAL_CTL, err); 1462 if (err < 0) 1463 return err; 1464 1465 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR, 1466 MRVL88X2011_PMA_PMD_CTL_1); 1467 if (err < 0) 1468 return err; 1469 1470 if (np->link_config.loopback_mode == LOOPBACK_MAC) 1471 err |= MRVL88X2011_LOOPBACK; 1472 else 1473 err &= ~MRVL88X2011_LOOPBACK; 1474 1475 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR, 1476 MRVL88X2011_PMA_PMD_CTL_1, err); 1477 if (err < 0) 1478 return err; 1479 1480 /* Enable PMD */ 1481 return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR, 1482 MRVL88X2011_10G_PMD_TX_DIS, MRVL88X2011_ENA_PMDTX); 1483} 1484 1485 1486static int xcvr_diag_bcm870x(struct niu *np) 1487{ 1488 u16 analog_stat0, tx_alarm_status; 1489 int err = 0; 1490 1491#if 1 1492 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR, 1493 MII_STAT1000); 1494 if (err < 0) 1495 return err; 1496 pr_info("Port %u PMA_PMD(MII_STAT1000) [%04x]\n", np->port, err); 1497 1498 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 0x20); 1499 if (err < 0) 1500 return err; 1501 pr_info("Port %u USER_DEV3(0x20) [%04x]\n", np->port, err); 1502 1503 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR, 1504 MII_NWAYTEST); 1505 if (err < 0) 1506 return err; 1507 pr_info("Port %u PHYXS(MII_NWAYTEST) [%04x]\n", np->port, err); 1508#endif 1509 1510 /* XXX dig this out it might not be so useful XXX */ 1511 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 1512 BCM8704_USER_ANALOG_STATUS0); 1513 if (err < 0) 1514 return err; 1515 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 1516 BCM8704_USER_ANALOG_STATUS0); 1517 if (err < 0) 1518 return err; 1519 analog_stat0 = err; 1520 1521 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 1522 BCM8704_USER_TX_ALARM_STATUS); 1523 if (err < 0) 1524 return err; 1525 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 1526 BCM8704_USER_TX_ALARM_STATUS); 1527 if (err < 0) 1528 return err; 1529 tx_alarm_status = err; 1530 1531 if (analog_stat0 != 0x03fc) { 1532 if ((analog_stat0 == 0x43bc) && (tx_alarm_status != 0)) { 1533 pr_info("Port %u cable not connected or bad cable\n", 1534 np->port); 1535 } else if (analog_stat0 == 0x639c) { 1536 pr_info("Port %u optical module is bad or missing\n", 1537 np->port); 1538 } 1539 } 1540 1541 return 0; 1542} 1543 1544static int xcvr_10g_set_lb_bcm870x(struct niu *np) 1545{ 1546 struct niu_link_config *lp = &np->link_config; 1547 int err; 1548 1549 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR, 1550 MII_BMCR); 1551 if (err < 0) 1552 return err; 1553 1554 err &= ~BMCR_LOOPBACK; 1555 1556 if (lp->loopback_mode == LOOPBACK_MAC) 1557 err |= BMCR_LOOPBACK; 1558 1559 err = mdio_write(np, np->phy_addr, BCM8704_PCS_DEV_ADDR, 1560 MII_BMCR, err); 1561 if (err) 1562 return err; 1563 1564 return 0; 1565} 1566 1567static int xcvr_init_10g_bcm8706(struct niu *np) 1568{ 1569 int err = 0; 1570 u64 val; 1571 1572 if ((np->flags & NIU_FLAGS_HOTPLUG_PHY) && 1573 (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) == 0) 1574 return err; 1575 1576 val = nr64_mac(XMAC_CONFIG); 1577 val &= ~XMAC_CONFIG_LED_POLARITY; 1578 val |= XMAC_CONFIG_FORCE_LED_ON; 1579 nw64_mac(XMAC_CONFIG, val); 1580 1581 val = nr64(MIF_CONFIG); 1582 val |= MIF_CONFIG_INDIRECT_MODE; 1583 nw64(MIF_CONFIG, val); 1584 1585 err = bcm8704_reset(np); 1586 if (err) 1587 return err; 1588 1589 err = xcvr_10g_set_lb_bcm870x(np); 1590 if (err) 1591 return err; 1592 1593 err = bcm8706_init_user_dev3(np); 1594 if (err) 1595 return err; 1596 1597 err = xcvr_diag_bcm870x(np); 1598 if (err) 1599 return err; 1600 1601 return 0; 1602} 1603 1604static int xcvr_init_10g_bcm8704(struct niu *np) 1605{ 1606 int err; 1607 1608 err = bcm8704_reset(np); 1609 if (err) 1610 return err; 1611 1612 err = bcm8704_init_user_dev3(np); 1613 if (err) 1614 return err; 1615 1616 err = xcvr_10g_set_lb_bcm870x(np); 1617 if (err) 1618 return err; 1619 1620 err = xcvr_diag_bcm870x(np); 1621 if (err) 1622 return err; 1623 1624 return 0; 1625} 1626 1627static int xcvr_init_10g(struct niu *np) 1628{ 1629 int phy_id, err; 1630 u64 val; 1631 1632 val = nr64_mac(XMAC_CONFIG); 1633 val &= ~XMAC_CONFIG_LED_POLARITY; 1634 val |= XMAC_CONFIG_FORCE_LED_ON; 1635 nw64_mac(XMAC_CONFIG, val); 1636 1637 /* XXX shared resource, lock parent XXX */ 1638 val = nr64(MIF_CONFIG); 1639 val |= MIF_CONFIG_INDIRECT_MODE; 1640 nw64(MIF_CONFIG, val); 1641 1642 phy_id = phy_decode(np->parent->port_phy, np->port); 1643 phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port]; 1644 1645 /* handle different phy types */ 1646 switch (phy_id & NIU_PHY_ID_MASK) { 1647 case NIU_PHY_ID_MRVL88X2011: 1648 err = xcvr_init_10g_mrvl88x2011(np); 1649 break; 1650 1651 default: /* bcom 8704 */ 1652 err = xcvr_init_10g_bcm8704(np); 1653 break; 1654 } 1655 1656 return 0; 1657} 1658 1659static int mii_reset(struct niu *np) 1660{ 1661 int limit, err; 1662 1663 err = mii_write(np, np->phy_addr, MII_BMCR, BMCR_RESET); 1664 if (err) 1665 return err; 1666 1667 limit = 1000; 1668 while (--limit >= 0) { 1669 udelay(500); 1670 err = mii_read(np, np->phy_addr, MII_BMCR); 1671 if (err < 0) 1672 return err; 1673 if (!(err & BMCR_RESET)) 1674 break; 1675 } 1676 if (limit < 0) { 1677 netdev_err(np->dev, "Port %u MII would not reset, bmcr[%04x]\n", 1678 np->port, err); 1679 return -ENODEV; 1680 } 1681 1682 return 0; 1683} 1684 1685static int xcvr_init_1g_rgmii(struct niu *np) 1686{ 1687 int err; 1688 u64 val; 1689 u16 bmcr, bmsr, estat; 1690 1691 val = nr64(MIF_CONFIG); 1692 val &= ~MIF_CONFIG_INDIRECT_MODE; 1693 nw64(MIF_CONFIG, val); 1694 1695 err = mii_reset(np); 1696 if (err) 1697 return err; 1698 1699 err = mii_read(np, np->phy_addr, MII_BMSR); 1700 if (err < 0) 1701 return err; 1702 bmsr = err; 1703 1704 estat = 0; 1705 if (bmsr & BMSR_ESTATEN) { 1706 err = mii_read(np, np->phy_addr, MII_ESTATUS); 1707 if (err < 0) 1708 return err; 1709 estat = err; 1710 } 1711 1712 bmcr = 0; 1713 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr); 1714 if (err) 1715 return err; 1716 1717 if (bmsr & BMSR_ESTATEN) { 1718 u16 ctrl1000 = 0; 1719 1720 if (estat & ESTATUS_1000_TFULL) 1721 ctrl1000 |= ADVERTISE_1000FULL; 1722 err = mii_write(np, np->phy_addr, MII_CTRL1000, ctrl1000); 1723 if (err) 1724 return err; 1725 } 1726 1727 bmcr = (BMCR_SPEED1000 | BMCR_FULLDPLX); 1728 1729 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr); 1730 if (err) 1731 return err; 1732 1733 err = mii_read(np, np->phy_addr, MII_BMCR); 1734 if (err < 0) 1735 return err; 1736 bmcr = mii_read(np, np->phy_addr, MII_BMCR); 1737 1738 err = mii_read(np, np->phy_addr, MII_BMSR); 1739 if (err < 0) 1740 return err; 1741 1742 return 0; 1743} 1744 1745static int mii_init_common(struct niu *np) 1746{ 1747 struct niu_link_config *lp = &np->link_config; 1748 u16 bmcr, bmsr, adv, estat; 1749 int err; 1750 1751 err = mii_reset(np); 1752 if (err) 1753 return err; 1754 1755 err = mii_read(np, np->phy_addr, MII_BMSR); 1756 if (err < 0) 1757 return err; 1758 bmsr = err; 1759 1760 estat = 0; 1761 if (bmsr & BMSR_ESTATEN) { 1762 err = mii_read(np, np->phy_addr, MII_ESTATUS); 1763 if (err < 0) 1764 return err; 1765 estat = err; 1766 } 1767 1768 bmcr = 0; 1769 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr); 1770 if (err) 1771 return err; 1772 1773 if (lp->loopback_mode == LOOPBACK_MAC) { 1774 bmcr |= BMCR_LOOPBACK; 1775 if (lp->active_speed == SPEED_1000) 1776 bmcr |= BMCR_SPEED1000; 1777 if (lp->active_duplex == DUPLEX_FULL) 1778 bmcr |= BMCR_FULLDPLX; 1779 } 1780 1781 if (lp->loopback_mode == LOOPBACK_PHY) { 1782 u16 aux; 1783 1784 aux = (BCM5464R_AUX_CTL_EXT_LB | 1785 BCM5464R_AUX_CTL_WRITE_1); 1786 err = mii_write(np, np->phy_addr, BCM5464R_AUX_CTL, aux); 1787 if (err) 1788 return err; 1789 } 1790 1791 if (lp->autoneg) { 1792 u16 ctrl1000; 1793 1794 adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP; 1795 if ((bmsr & BMSR_10HALF) && 1796 (lp->advertising & ADVERTISED_10baseT_Half)) 1797 adv |= ADVERTISE_10HALF; 1798 if ((bmsr & BMSR_10FULL) && 1799 (lp->advertising & ADVERTISED_10baseT_Full)) 1800 adv |= ADVERTISE_10FULL; 1801 if ((bmsr & BMSR_100HALF) && 1802 (lp->advertising & ADVERTISED_100baseT_Half)) 1803 adv |= ADVERTISE_100HALF; 1804 if ((bmsr & BMSR_100FULL) && 1805 (lp->advertising & ADVERTISED_100baseT_Full)) 1806 adv |= ADVERTISE_100FULL; 1807 err = mii_write(np, np->phy_addr, MII_ADVERTISE, adv); 1808 if (err) 1809 return err; 1810 1811 if (likely(bmsr & BMSR_ESTATEN)) { 1812 ctrl1000 = 0; 1813 if ((estat & ESTATUS_1000_THALF) && 1814 (lp->advertising & ADVERTISED_1000baseT_Half)) 1815 ctrl1000 |= ADVERTISE_1000HALF; 1816 if ((estat & ESTATUS_1000_TFULL) && 1817 (lp->advertising & ADVERTISED_1000baseT_Full)) 1818 ctrl1000 |= ADVERTISE_1000FULL; 1819 err = mii_write(np, np->phy_addr, 1820 MII_CTRL1000, ctrl1000); 1821 if (err) 1822 return err; 1823 } 1824 1825 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART); 1826 } else { 1827 /* !lp->autoneg */ 1828 int fulldpx; 1829 1830 if (lp->duplex == DUPLEX_FULL) { 1831 bmcr |= BMCR_FULLDPLX; 1832 fulldpx = 1; 1833 } else if (lp->duplex == DUPLEX_HALF) 1834 fulldpx = 0; 1835 else 1836 return -EINVAL; 1837 1838 if (lp->speed == SPEED_1000) { 1839 /* if X-full requested while not supported, or 1840 X-half requested while not supported... */ 1841 if ((fulldpx && !(estat & ESTATUS_1000_TFULL)) || 1842 (!fulldpx && !(estat & ESTATUS_1000_THALF))) 1843 return -EINVAL; 1844 bmcr |= BMCR_SPEED1000; 1845 } else if (lp->speed == SPEED_100) { 1846 if ((fulldpx && !(bmsr & BMSR_100FULL)) || 1847 (!fulldpx && !(bmsr & BMSR_100HALF))) 1848 return -EINVAL; 1849 bmcr |= BMCR_SPEED100; 1850 } else if (lp->speed == SPEED_10) { 1851 if ((fulldpx && !(bmsr & BMSR_10FULL)) || 1852 (!fulldpx && !(bmsr & BMSR_10HALF))) 1853 return -EINVAL; 1854 } else 1855 return -EINVAL; 1856 } 1857 1858 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr); 1859 if (err) 1860 return err; 1861 1862#if 0 1863 err = mii_read(np, np->phy_addr, MII_BMCR); 1864 if (err < 0) 1865 return err; 1866 bmcr = err; 1867 1868 err = mii_read(np, np->phy_addr, MII_BMSR); 1869 if (err < 0) 1870 return err; 1871 bmsr = err; 1872 1873 pr_info("Port %u after MII init bmcr[%04x] bmsr[%04x]\n", 1874 np->port, bmcr, bmsr); 1875#endif 1876 1877 return 0; 1878} 1879 1880static int xcvr_init_1g(struct niu *np) 1881{ 1882 u64 val; 1883 1884 /* XXX shared resource, lock parent XXX */ 1885 val = nr64(MIF_CONFIG); 1886 val &= ~MIF_CONFIG_INDIRECT_MODE; 1887 nw64(MIF_CONFIG, val); 1888 1889 return mii_init_common(np); 1890} 1891 1892static int niu_xcvr_init(struct niu *np) 1893{ 1894 const struct niu_phy_ops *ops = np->phy_ops; 1895 int err; 1896 1897 err = 0; 1898 if (ops->xcvr_init) 1899 err = ops->xcvr_init(np); 1900 1901 return err; 1902} 1903 1904static int niu_serdes_init(struct niu *np) 1905{ 1906 const struct niu_phy_ops *ops = np->phy_ops; 1907 int err; 1908 1909 err = 0; 1910 if (ops->serdes_init) 1911 err = ops->serdes_init(np); 1912 1913 return err; 1914} 1915 1916static void niu_init_xif(struct niu *); 1917static void niu_handle_led(struct niu *, int status); 1918 1919static int niu_link_status_common(struct niu *np, int link_up) 1920{ 1921 struct niu_link_config *lp = &np->link_config; 1922 struct net_device *dev = np->dev; 1923 unsigned long flags; 1924 1925 if (!netif_carrier_ok(dev) && link_up) { 1926 netif_info(np, link, dev, "Link is up at %s, %s duplex\n", 1927 lp->active_speed == SPEED_10000 ? "10Gb/sec" : 1928 lp->active_speed == SPEED_1000 ? "1Gb/sec" : 1929 lp->active_speed == SPEED_100 ? "100Mbit/sec" : 1930 "10Mbit/sec", 1931 lp->active_duplex == DUPLEX_FULL ? "full" : "half"); 1932 1933 spin_lock_irqsave(&np->lock, flags); 1934 niu_init_xif(np); 1935 niu_handle_led(np, 1); 1936 spin_unlock_irqrestore(&np->lock, flags); 1937 1938 netif_carrier_on(dev); 1939 } else if (netif_carrier_ok(dev) && !link_up) { 1940 netif_warn(np, link, dev, "Link is down\n"); 1941 spin_lock_irqsave(&np->lock, flags); 1942 niu_handle_led(np, 0); 1943 spin_unlock_irqrestore(&np->lock, flags); 1944 netif_carrier_off(dev); 1945 } 1946 1947 return 0; 1948} 1949 1950static int link_status_10g_mrvl(struct niu *np, int *link_up_p) 1951{ 1952 int err, link_up, pma_status, pcs_status; 1953 1954 link_up = 0; 1955 1956 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR, 1957 MRVL88X2011_10G_PMD_STATUS_2); 1958 if (err < 0) 1959 goto out; 1960 1961 /* Check PMA/PMD Register: 1.0001.2 == 1 */ 1962 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR, 1963 MRVL88X2011_PMA_PMD_STATUS_1); 1964 if (err < 0) 1965 goto out; 1966 1967 pma_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0); 1968 1969 /* Check PMC Register : 3.0001.2 == 1: read twice */ 1970 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR, 1971 MRVL88X2011_PMA_PMD_STATUS_1); 1972 if (err < 0) 1973 goto out; 1974 1975 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR, 1976 MRVL88X2011_PMA_PMD_STATUS_1); 1977 if (err < 0) 1978 goto out; 1979 1980 pcs_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0); 1981 1982 /* Check XGXS Register : 4.0018.[0-3,12] */ 1983 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV4_ADDR, 1984 MRVL88X2011_10G_XGXS_LANE_STAT); 1985 if (err < 0) 1986 goto out; 1987 1988 if (err == (PHYXS_XGXS_LANE_STAT_ALINGED | PHYXS_XGXS_LANE_STAT_LANE3 | 1989 PHYXS_XGXS_LANE_STAT_LANE2 | PHYXS_XGXS_LANE_STAT_LANE1 | 1990 PHYXS_XGXS_LANE_STAT_LANE0 | PHYXS_XGXS_LANE_STAT_MAGIC | 1991 0x800)) 1992 link_up = (pma_status && pcs_status) ? 1 : 0; 1993 1994 np->link_config.active_speed = SPEED_10000; 1995 np->link_config.active_duplex = DUPLEX_FULL; 1996 err = 0; 1997out: 1998 mrvl88x2011_act_led(np, (link_up ? 1999 MRVL88X2011_LED_CTL_PCS_ACT : 2000 MRVL88X2011_LED_CTL_OFF)); 2001 2002 *link_up_p = link_up; 2003 return err; 2004} 2005 2006static int link_status_10g_bcm8706(struct niu *np, int *link_up_p) 2007{ 2008 int err, link_up; 2009 link_up = 0; 2010 2011 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR, 2012 BCM8704_PMD_RCV_SIGDET); 2013 if (err < 0 || err == 0xffff) 2014 goto out; 2015 if (!(err & PMD_RCV_SIGDET_GLOBAL)) { 2016 err = 0; 2017 goto out; 2018 } 2019 2020 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR, 2021 BCM8704_PCS_10G_R_STATUS); 2022 if (err < 0) 2023 goto out; 2024 2025 if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) { 2026 err = 0; 2027 goto out; 2028 } 2029 2030 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR, 2031 BCM8704_PHYXS_XGXS_LANE_STAT); 2032 if (err < 0) 2033 goto out; 2034 if (err != (PHYXS_XGXS_LANE_STAT_ALINGED | 2035 PHYXS_XGXS_LANE_STAT_MAGIC | 2036 PHYXS_XGXS_LANE_STAT_PATTEST | 2037 PHYXS_XGXS_LANE_STAT_LANE3 | 2038 PHYXS_XGXS_LANE_STAT_LANE2 | 2039 PHYXS_XGXS_LANE_STAT_LANE1 | 2040 PHYXS_XGXS_LANE_STAT_LANE0)) { 2041 err = 0; 2042 np->link_config.active_speed = SPEED_INVALID; 2043 np->link_config.active_duplex = DUPLEX_INVALID; 2044 goto out; 2045 } 2046 2047 link_up = 1; 2048 np->link_config.active_speed = SPEED_10000; 2049 np->link_config.active_duplex = DUPLEX_FULL; 2050 err = 0; 2051 2052out: 2053 *link_up_p = link_up; 2054 return err; 2055} 2056 2057static int link_status_10g_bcom(struct niu *np, int *link_up_p) 2058{ 2059 int err, link_up; 2060 2061 link_up = 0; 2062 2063 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR, 2064 BCM8704_PMD_RCV_SIGDET); 2065 if (err < 0) 2066 goto out; 2067 if (!(err & PMD_RCV_SIGDET_GLOBAL)) { 2068 err = 0; 2069 goto out; 2070 } 2071 2072 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR, 2073 BCM8704_PCS_10G_R_STATUS); 2074 if (err < 0) 2075 goto out; 2076 if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) { 2077 err = 0; 2078 goto out; 2079 } 2080 2081 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR, 2082 BCM8704_PHYXS_XGXS_LANE_STAT); 2083 if (err < 0) 2084 goto out; 2085 2086 if (err != (PHYXS_XGXS_LANE_STAT_ALINGED | 2087 PHYXS_XGXS_LANE_STAT_MAGIC | 2088 PHYXS_XGXS_LANE_STAT_LANE3 | 2089 PHYXS_XGXS_LANE_STAT_LANE2 | 2090 PHYXS_XGXS_LANE_STAT_LANE1 | 2091 PHYXS_XGXS_LANE_STAT_LANE0)) { 2092 err = 0; 2093 goto out; 2094 } 2095 2096 link_up = 1; 2097 np->link_config.active_speed = SPEED_10000; 2098 np->link_config.active_duplex = DUPLEX_FULL; 2099 err = 0; 2100 2101out: 2102 *link_up_p = link_up; 2103 return err; 2104} 2105 2106static int link_status_10g(struct niu *np, int *link_up_p) 2107{ 2108 unsigned long flags; 2109 int err = -EINVAL; 2110 2111 spin_lock_irqsave(&np->lock, flags); 2112 2113 if (np->link_config.loopback_mode == LOOPBACK_DISABLED) { 2114 int phy_id; 2115 2116 phy_id = phy_decode(np->parent->port_phy, np->port); 2117 phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port]; 2118 2119 /* handle different phy types */ 2120 switch (phy_id & NIU_PHY_ID_MASK) { 2121 case NIU_PHY_ID_MRVL88X2011: 2122 err = link_status_10g_mrvl(np, link_up_p); 2123 break; 2124 2125 default: /* bcom 8704 */ 2126 err = link_status_10g_bcom(np, link_up_p); 2127 break; 2128 } 2129 } 2130 2131 spin_unlock_irqrestore(&np->lock, flags); 2132 2133 return err; 2134} 2135 2136static int niu_10g_phy_present(struct niu *np) 2137{ 2138 u64 sig, mask, val; 2139 2140 sig = nr64(ESR_INT_SIGNALS); 2141 switch (np->port) { 2142 case 0: 2143 mask = ESR_INT_SIGNALS_P0_BITS; 2144 val = (ESR_INT_SRDY0_P0 | 2145 ESR_INT_DET0_P0 | 2146 ESR_INT_XSRDY_P0 | 2147 ESR_INT_XDP_P0_CH3 | 2148 ESR_INT_XDP_P0_CH2 | 2149 ESR_INT_XDP_P0_CH1 | 2150 ESR_INT_XDP_P0_CH0); 2151 break; 2152 2153 case 1: 2154 mask = ESR_INT_SIGNALS_P1_BITS; 2155 val = (ESR_INT_SRDY0_P1 | 2156 ESR_INT_DET0_P1 | 2157 ESR_INT_XSRDY_P1 | 2158 ESR_INT_XDP_P1_CH3 | 2159 ESR_INT_XDP_P1_CH2 | 2160 ESR_INT_XDP_P1_CH1 | 2161 ESR_INT_XDP_P1_CH0); 2162 break; 2163 2164 default: 2165 return 0; 2166 } 2167 2168 if ((sig & mask) != val) 2169 return 0; 2170 return 1; 2171} 2172 2173static int link_status_10g_hotplug(struct niu *np, int *link_up_p) 2174{ 2175 unsigned long flags; 2176 int err = 0; 2177 int phy_present; 2178 int phy_present_prev; 2179 2180 spin_lock_irqsave(&np->lock, flags); 2181 2182 if (np->link_config.loopback_mode == LOOPBACK_DISABLED) { 2183 phy_present_prev = (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) ? 2184 1 : 0; 2185 phy_present = niu_10g_phy_present(np); 2186 if (phy_present != phy_present_prev) { 2187 /* state change */ 2188 if (phy_present) { 2189 /* A NEM was just plugged in */ 2190 np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT; 2191 if (np->phy_ops->xcvr_init) 2192 err = np->phy_ops->xcvr_init(np); 2193 if (err) { 2194 err = mdio_read(np, np->phy_addr, 2195 BCM8704_PHYXS_DEV_ADDR, MII_BMCR); 2196 if (err == 0xffff) { 2197 /* No mdio, back-to-back XAUI */ 2198 goto out; 2199 } 2200 /* debounce */ 2201 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT; 2202 } 2203 } else { 2204 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT; 2205 *link_up_p = 0; 2206 netif_warn(np, link, np->dev, 2207 "Hotplug PHY Removed\n"); 2208 } 2209 } 2210out: 2211 if (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) { 2212 err = link_status_10g_bcm8706(np, link_up_p); 2213 if (err == …
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