/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c

https://gitlab.com/sunny256/linux · C · 915 lines · 618 code · 141 blank · 156 comment · 44 complexity · 3a96b372f4ee3e7cc22c054989d85cbb MD5 · raw file

  1. /*
  2. * Copyright 2014 Advanced Micro Devices, Inc.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20. * OTHER DEALINGS IN THE SOFTWARE.
  21. *
  22. * Authors: Christian König <christian.koenig@amd.com>
  23. */
  24. #include <linux/firmware.h>
  25. #include <drm/drmP.h>
  26. #include "amdgpu.h"
  27. #include "amdgpu_uvd.h"
  28. #include "vid.h"
  29. #include "uvd/uvd_5_0_d.h"
  30. #include "uvd/uvd_5_0_sh_mask.h"
  31. #include "oss/oss_2_0_d.h"
  32. #include "oss/oss_2_0_sh_mask.h"
  33. #include "bif/bif_5_0_d.h"
  34. #include "vi.h"
  35. #include "smu/smu_7_1_2_d.h"
  36. #include "smu/smu_7_1_2_sh_mask.h"
  37. static void uvd_v5_0_set_ring_funcs(struct amdgpu_device *adev);
  38. static void uvd_v5_0_set_irq_funcs(struct amdgpu_device *adev);
  39. static int uvd_v5_0_start(struct amdgpu_device *adev);
  40. static void uvd_v5_0_stop(struct amdgpu_device *adev);
  41. static int uvd_v5_0_set_clockgating_state(void *handle,
  42. enum amd_clockgating_state state);
  43. static void uvd_v5_0_enable_mgcg(struct amdgpu_device *adev,
  44. bool enable);
  45. /**
  46. * uvd_v5_0_ring_get_rptr - get read pointer
  47. *
  48. * @ring: amdgpu_ring pointer
  49. *
  50. * Returns the current hardware read pointer
  51. */
  52. static uint64_t uvd_v5_0_ring_get_rptr(struct amdgpu_ring *ring)
  53. {
  54. struct amdgpu_device *adev = ring->adev;
  55. return RREG32(mmUVD_RBC_RB_RPTR);
  56. }
  57. /**
  58. * uvd_v5_0_ring_get_wptr - get write pointer
  59. *
  60. * @ring: amdgpu_ring pointer
  61. *
  62. * Returns the current hardware write pointer
  63. */
  64. static uint64_t uvd_v5_0_ring_get_wptr(struct amdgpu_ring *ring)
  65. {
  66. struct amdgpu_device *adev = ring->adev;
  67. return RREG32(mmUVD_RBC_RB_WPTR);
  68. }
  69. /**
  70. * uvd_v5_0_ring_set_wptr - set write pointer
  71. *
  72. * @ring: amdgpu_ring pointer
  73. *
  74. * Commits the write pointer to the hardware
  75. */
  76. static void uvd_v5_0_ring_set_wptr(struct amdgpu_ring *ring)
  77. {
  78. struct amdgpu_device *adev = ring->adev;
  79. WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
  80. }
  81. static int uvd_v5_0_early_init(void *handle)
  82. {
  83. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  84. uvd_v5_0_set_ring_funcs(adev);
  85. uvd_v5_0_set_irq_funcs(adev);
  86. return 0;
  87. }
  88. static int uvd_v5_0_sw_init(void *handle)
  89. {
  90. struct amdgpu_ring *ring;
  91. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  92. int r;
  93. /* UVD TRAP */
  94. r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 124, &adev->uvd.irq);
  95. if (r)
  96. return r;
  97. r = amdgpu_uvd_sw_init(adev);
  98. if (r)
  99. return r;
  100. r = amdgpu_uvd_resume(adev);
  101. if (r)
  102. return r;
  103. ring = &adev->uvd.ring;
  104. sprintf(ring->name, "uvd");
  105. r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0);
  106. return r;
  107. }
  108. static int uvd_v5_0_sw_fini(void *handle)
  109. {
  110. int r;
  111. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  112. r = amdgpu_uvd_suspend(adev);
  113. if (r)
  114. return r;
  115. return amdgpu_uvd_sw_fini(adev);
  116. }
  117. /**
  118. * uvd_v5_0_hw_init - start and test UVD block
  119. *
  120. * @adev: amdgpu_device pointer
  121. *
  122. * Initialize the hardware, boot up the VCPU and do some testing
  123. */
  124. static int uvd_v5_0_hw_init(void *handle)
  125. {
  126. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  127. struct amdgpu_ring *ring = &adev->uvd.ring;
  128. uint32_t tmp;
  129. int r;
  130. amdgpu_asic_set_uvd_clocks(adev, 10000, 10000);
  131. uvd_v5_0_set_clockgating_state(adev, AMD_CG_STATE_UNGATE);
  132. uvd_v5_0_enable_mgcg(adev, true);
  133. ring->ready = true;
  134. r = amdgpu_ring_test_ring(ring);
  135. if (r) {
  136. ring->ready = false;
  137. goto done;
  138. }
  139. r = amdgpu_ring_alloc(ring, 10);
  140. if (r) {
  141. DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r);
  142. goto done;
  143. }
  144. tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0);
  145. amdgpu_ring_write(ring, tmp);
  146. amdgpu_ring_write(ring, 0xFFFFF);
  147. tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0);
  148. amdgpu_ring_write(ring, tmp);
  149. amdgpu_ring_write(ring, 0xFFFFF);
  150. tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0);
  151. amdgpu_ring_write(ring, tmp);
  152. amdgpu_ring_write(ring, 0xFFFFF);
  153. /* Clear timeout status bits */
  154. amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0));
  155. amdgpu_ring_write(ring, 0x8);
  156. amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0));
  157. amdgpu_ring_write(ring, 3);
  158. amdgpu_ring_commit(ring);
  159. done:
  160. if (!r)
  161. DRM_INFO("UVD initialized successfully.\n");
  162. return r;
  163. }
  164. /**
  165. * uvd_v5_0_hw_fini - stop the hardware block
  166. *
  167. * @adev: amdgpu_device pointer
  168. *
  169. * Stop the UVD block, mark ring as not ready any more
  170. */
  171. static int uvd_v5_0_hw_fini(void *handle)
  172. {
  173. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  174. struct amdgpu_ring *ring = &adev->uvd.ring;
  175. if (RREG32(mmUVD_STATUS) != 0)
  176. uvd_v5_0_stop(adev);
  177. ring->ready = false;
  178. return 0;
  179. }
  180. static int uvd_v5_0_suspend(void *handle)
  181. {
  182. int r;
  183. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  184. r = uvd_v5_0_hw_fini(adev);
  185. if (r)
  186. return r;
  187. uvd_v5_0_set_clockgating_state(adev, AMD_CG_STATE_GATE);
  188. return amdgpu_uvd_suspend(adev);
  189. }
  190. static int uvd_v5_0_resume(void *handle)
  191. {
  192. int r;
  193. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  194. r = amdgpu_uvd_resume(adev);
  195. if (r)
  196. return r;
  197. return uvd_v5_0_hw_init(adev);
  198. }
  199. /**
  200. * uvd_v5_0_mc_resume - memory controller programming
  201. *
  202. * @adev: amdgpu_device pointer
  203. *
  204. * Let the UVD memory controller know it's offsets
  205. */
  206. static void uvd_v5_0_mc_resume(struct amdgpu_device *adev)
  207. {
  208. uint64_t offset;
  209. uint32_t size;
  210. /* programm memory controller bits 0-27 */
  211. WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
  212. lower_32_bits(adev->uvd.gpu_addr));
  213. WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
  214. upper_32_bits(adev->uvd.gpu_addr));
  215. offset = AMDGPU_UVD_FIRMWARE_OFFSET;
  216. size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4);
  217. WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3);
  218. WREG32(mmUVD_VCPU_CACHE_SIZE0, size);
  219. offset += size;
  220. size = AMDGPU_UVD_HEAP_SIZE;
  221. WREG32(mmUVD_VCPU_CACHE_OFFSET1, offset >> 3);
  222. WREG32(mmUVD_VCPU_CACHE_SIZE1, size);
  223. offset += size;
  224. size = AMDGPU_UVD_STACK_SIZE +
  225. (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles);
  226. WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3);
  227. WREG32(mmUVD_VCPU_CACHE_SIZE2, size);
  228. WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
  229. WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
  230. WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
  231. }
  232. /**
  233. * uvd_v5_0_start - start UVD block
  234. *
  235. * @adev: amdgpu_device pointer
  236. *
  237. * Setup and start the UVD block
  238. */
  239. static int uvd_v5_0_start(struct amdgpu_device *adev)
  240. {
  241. struct amdgpu_ring *ring = &adev->uvd.ring;
  242. uint32_t rb_bufsz, tmp;
  243. uint32_t lmi_swap_cntl;
  244. uint32_t mp_swap_cntl;
  245. int i, j, r;
  246. /*disable DPG */
  247. WREG32_P(mmUVD_POWER_STATUS, 0, ~(1 << 2));
  248. /* disable byte swapping */
  249. lmi_swap_cntl = 0;
  250. mp_swap_cntl = 0;
  251. uvd_v5_0_mc_resume(adev);
  252. /* disable interupt */
  253. WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1));
  254. /* stall UMC and register bus before resetting VCPU */
  255. WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
  256. mdelay(1);
  257. /* put LMI, VCPU, RBC etc... into reset */
  258. WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
  259. UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |
  260. UVD_SOFT_RESET__RBC_SOFT_RESET_MASK | UVD_SOFT_RESET__CSM_SOFT_RESET_MASK |
  261. UVD_SOFT_RESET__CXW_SOFT_RESET_MASK | UVD_SOFT_RESET__TAP_SOFT_RESET_MASK |
  262. UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
  263. mdelay(5);
  264. /* take UVD block out of reset */
  265. WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK);
  266. mdelay(5);
  267. /* initialize UVD memory controller */
  268. WREG32(mmUVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) |
  269. (1 << 21) | (1 << 9) | (1 << 20));
  270. #ifdef __BIG_ENDIAN
  271. /* swap (8 in 32) RB and IB */
  272. lmi_swap_cntl = 0xa;
  273. mp_swap_cntl = 0;
  274. #endif
  275. WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
  276. WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl);
  277. WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040);
  278. WREG32(mmUVD_MPC_SET_MUXA1, 0x0);
  279. WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040);
  280. WREG32(mmUVD_MPC_SET_MUXB1, 0x0);
  281. WREG32(mmUVD_MPC_SET_ALU, 0);
  282. WREG32(mmUVD_MPC_SET_MUX, 0x88);
  283. /* take all subblocks out of reset, except VCPU */
  284. WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
  285. mdelay(5);
  286. /* enable VCPU clock */
  287. WREG32(mmUVD_VCPU_CNTL, 1 << 9);
  288. /* enable UMC */
  289. WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8));
  290. /* boot up the VCPU */
  291. WREG32(mmUVD_SOFT_RESET, 0);
  292. mdelay(10);
  293. for (i = 0; i < 10; ++i) {
  294. uint32_t status;
  295. for (j = 0; j < 100; ++j) {
  296. status = RREG32(mmUVD_STATUS);
  297. if (status & 2)
  298. break;
  299. mdelay(10);
  300. }
  301. r = 0;
  302. if (status & 2)
  303. break;
  304. DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n");
  305. WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
  306. ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
  307. mdelay(10);
  308. WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
  309. mdelay(10);
  310. r = -1;
  311. }
  312. if (r) {
  313. DRM_ERROR("UVD not responding, giving up!!!\n");
  314. return r;
  315. }
  316. /* enable master interrupt */
  317. WREG32_P(mmUVD_MASTINT_EN, 3 << 1, ~(3 << 1));
  318. /* clear the bit 4 of UVD_STATUS */
  319. WREG32_P(mmUVD_STATUS, 0, ~(2 << 1));
  320. rb_bufsz = order_base_2(ring->ring_size);
  321. tmp = 0;
  322. tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
  323. tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
  324. tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
  325. tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);
  326. tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
  327. tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
  328. /* force RBC into idle state */
  329. WREG32(mmUVD_RBC_RB_CNTL, tmp);
  330. /* set the write pointer delay */
  331. WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0);
  332. /* set the wb address */
  333. WREG32(mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2));
  334. /* programm the RB_BASE for ring buffer */
  335. WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
  336. lower_32_bits(ring->gpu_addr));
  337. WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
  338. upper_32_bits(ring->gpu_addr));
  339. /* Initialize the ring buffer's read and write pointers */
  340. WREG32(mmUVD_RBC_RB_RPTR, 0);
  341. ring->wptr = RREG32(mmUVD_RBC_RB_RPTR);
  342. WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
  343. WREG32_P(mmUVD_RBC_RB_CNTL, 0, ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK);
  344. return 0;
  345. }
  346. /**
  347. * uvd_v5_0_stop - stop UVD block
  348. *
  349. * @adev: amdgpu_device pointer
  350. *
  351. * stop the UVD block
  352. */
  353. static void uvd_v5_0_stop(struct amdgpu_device *adev)
  354. {
  355. /* force RBC into idle state */
  356. WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);
  357. /* Stall UMC and register bus before resetting VCPU */
  358. WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
  359. mdelay(1);
  360. /* put VCPU into reset */
  361. WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
  362. mdelay(5);
  363. /* disable VCPU clock */
  364. WREG32(mmUVD_VCPU_CNTL, 0x0);
  365. /* Unstall UMC and register bus */
  366. WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8));
  367. WREG32(mmUVD_STATUS, 0);
  368. }
  369. /**
  370. * uvd_v5_0_ring_emit_fence - emit an fence & trap command
  371. *
  372. * @ring: amdgpu_ring pointer
  373. * @fence: fence to emit
  374. *
  375. * Write a fence and a trap command to the ring.
  376. */
  377. static void uvd_v5_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
  378. unsigned flags)
  379. {
  380. WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
  381. amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
  382. amdgpu_ring_write(ring, seq);
  383. amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
  384. amdgpu_ring_write(ring, addr & 0xffffffff);
  385. amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
  386. amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
  387. amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
  388. amdgpu_ring_write(ring, 0);
  389. amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
  390. amdgpu_ring_write(ring, 0);
  391. amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
  392. amdgpu_ring_write(ring, 0);
  393. amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
  394. amdgpu_ring_write(ring, 2);
  395. }
  396. /**
  397. * uvd_v5_0_ring_emit_hdp_flush - emit an hdp flush
  398. *
  399. * @ring: amdgpu_ring pointer
  400. *
  401. * Emits an hdp flush.
  402. */
  403. static void uvd_v5_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
  404. {
  405. amdgpu_ring_write(ring, PACKET0(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0));
  406. amdgpu_ring_write(ring, 0);
  407. }
  408. /**
  409. * uvd_v5_0_ring_hdp_invalidate - emit an hdp invalidate
  410. *
  411. * @ring: amdgpu_ring pointer
  412. *
  413. * Emits an hdp invalidate.
  414. */
  415. static void uvd_v5_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
  416. {
  417. amdgpu_ring_write(ring, PACKET0(mmHDP_DEBUG0, 0));
  418. amdgpu_ring_write(ring, 1);
  419. }
  420. /**
  421. * uvd_v5_0_ring_test_ring - register write test
  422. *
  423. * @ring: amdgpu_ring pointer
  424. *
  425. * Test if we can successfully write to the context register
  426. */
  427. static int uvd_v5_0_ring_test_ring(struct amdgpu_ring *ring)
  428. {
  429. struct amdgpu_device *adev = ring->adev;
  430. uint32_t tmp = 0;
  431. unsigned i;
  432. int r;
  433. WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD);
  434. r = amdgpu_ring_alloc(ring, 3);
  435. if (r) {
  436. DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
  437. ring->idx, r);
  438. return r;
  439. }
  440. amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
  441. amdgpu_ring_write(ring, 0xDEADBEEF);
  442. amdgpu_ring_commit(ring);
  443. for (i = 0; i < adev->usec_timeout; i++) {
  444. tmp = RREG32(mmUVD_CONTEXT_ID);
  445. if (tmp == 0xDEADBEEF)
  446. break;
  447. DRM_UDELAY(1);
  448. }
  449. if (i < adev->usec_timeout) {
  450. DRM_INFO("ring test on %d succeeded in %d usecs\n",
  451. ring->idx, i);
  452. } else {
  453. DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
  454. ring->idx, tmp);
  455. r = -EINVAL;
  456. }
  457. return r;
  458. }
  459. /**
  460. * uvd_v5_0_ring_emit_ib - execute indirect buffer
  461. *
  462. * @ring: amdgpu_ring pointer
  463. * @ib: indirect buffer to execute
  464. *
  465. * Write ring commands to execute the indirect buffer
  466. */
  467. static void uvd_v5_0_ring_emit_ib(struct amdgpu_ring *ring,
  468. struct amdgpu_ib *ib,
  469. unsigned vm_id, bool ctx_switch)
  470. {
  471. amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW, 0));
  472. amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
  473. amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH, 0));
  474. amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
  475. amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0));
  476. amdgpu_ring_write(ring, ib->length_dw);
  477. }
  478. static bool uvd_v5_0_is_idle(void *handle)
  479. {
  480. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  481. return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
  482. }
  483. static int uvd_v5_0_wait_for_idle(void *handle)
  484. {
  485. unsigned i;
  486. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  487. for (i = 0; i < adev->usec_timeout; i++) {
  488. if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK))
  489. return 0;
  490. }
  491. return -ETIMEDOUT;
  492. }
  493. static int uvd_v5_0_soft_reset(void *handle)
  494. {
  495. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  496. uvd_v5_0_stop(adev);
  497. WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK,
  498. ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK);
  499. mdelay(5);
  500. return uvd_v5_0_start(adev);
  501. }
  502. static int uvd_v5_0_set_interrupt_state(struct amdgpu_device *adev,
  503. struct amdgpu_irq_src *source,
  504. unsigned type,
  505. enum amdgpu_interrupt_state state)
  506. {
  507. // TODO
  508. return 0;
  509. }
  510. static int uvd_v5_0_process_interrupt(struct amdgpu_device *adev,
  511. struct amdgpu_irq_src *source,
  512. struct amdgpu_iv_entry *entry)
  513. {
  514. DRM_DEBUG("IH: UVD TRAP\n");
  515. amdgpu_fence_process(&adev->uvd.ring);
  516. return 0;
  517. }
  518. static void uvd_v5_0_enable_clock_gating(struct amdgpu_device *adev, bool enable)
  519. {
  520. uint32_t data1, data3, suvd_flags;
  521. data1 = RREG32(mmUVD_SUVD_CGC_GATE);
  522. data3 = RREG32(mmUVD_CGC_GATE);
  523. suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |
  524. UVD_SUVD_CGC_GATE__SIT_MASK |
  525. UVD_SUVD_CGC_GATE__SMP_MASK |
  526. UVD_SUVD_CGC_GATE__SCM_MASK |
  527. UVD_SUVD_CGC_GATE__SDB_MASK;
  528. if (enable) {
  529. data3 |= (UVD_CGC_GATE__SYS_MASK |
  530. UVD_CGC_GATE__UDEC_MASK |
  531. UVD_CGC_GATE__MPEG2_MASK |
  532. UVD_CGC_GATE__RBC_MASK |
  533. UVD_CGC_GATE__LMI_MC_MASK |
  534. UVD_CGC_GATE__IDCT_MASK |
  535. UVD_CGC_GATE__MPRD_MASK |
  536. UVD_CGC_GATE__MPC_MASK |
  537. UVD_CGC_GATE__LBSI_MASK |
  538. UVD_CGC_GATE__LRBBM_MASK |
  539. UVD_CGC_GATE__UDEC_RE_MASK |
  540. UVD_CGC_GATE__UDEC_CM_MASK |
  541. UVD_CGC_GATE__UDEC_IT_MASK |
  542. UVD_CGC_GATE__UDEC_DB_MASK |
  543. UVD_CGC_GATE__UDEC_MP_MASK |
  544. UVD_CGC_GATE__WCB_MASK |
  545. UVD_CGC_GATE__JPEG_MASK |
  546. UVD_CGC_GATE__SCPU_MASK);
  547. /* only in pg enabled, we can gate clock to vcpu*/
  548. if (adev->pg_flags & AMD_PG_SUPPORT_UVD)
  549. data3 |= UVD_CGC_GATE__VCPU_MASK;
  550. data3 &= ~UVD_CGC_GATE__REGS_MASK;
  551. data1 |= suvd_flags;
  552. } else {
  553. data3 = 0;
  554. data1 = 0;
  555. }
  556. WREG32(mmUVD_SUVD_CGC_GATE, data1);
  557. WREG32(mmUVD_CGC_GATE, data3);
  558. }
  559. static void uvd_v5_0_set_sw_clock_gating(struct amdgpu_device *adev)
  560. {
  561. uint32_t data, data2;
  562. data = RREG32(mmUVD_CGC_CTRL);
  563. data2 = RREG32(mmUVD_SUVD_CGC_CTRL);
  564. data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK |
  565. UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK);
  566. data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK |
  567. (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) |
  568. (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY));
  569. data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
  570. UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
  571. UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
  572. UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
  573. UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
  574. UVD_CGC_CTRL__SYS_MODE_MASK |
  575. UVD_CGC_CTRL__UDEC_MODE_MASK |
  576. UVD_CGC_CTRL__MPEG2_MODE_MASK |
  577. UVD_CGC_CTRL__REGS_MODE_MASK |
  578. UVD_CGC_CTRL__RBC_MODE_MASK |
  579. UVD_CGC_CTRL__LMI_MC_MODE_MASK |
  580. UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
  581. UVD_CGC_CTRL__IDCT_MODE_MASK |
  582. UVD_CGC_CTRL__MPRD_MODE_MASK |
  583. UVD_CGC_CTRL__MPC_MODE_MASK |
  584. UVD_CGC_CTRL__LBSI_MODE_MASK |
  585. UVD_CGC_CTRL__LRBBM_MODE_MASK |
  586. UVD_CGC_CTRL__WCB_MODE_MASK |
  587. UVD_CGC_CTRL__VCPU_MODE_MASK |
  588. UVD_CGC_CTRL__JPEG_MODE_MASK |
  589. UVD_CGC_CTRL__SCPU_MODE_MASK);
  590. data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK |
  591. UVD_SUVD_CGC_CTRL__SIT_MODE_MASK |
  592. UVD_SUVD_CGC_CTRL__SMP_MODE_MASK |
  593. UVD_SUVD_CGC_CTRL__SCM_MODE_MASK |
  594. UVD_SUVD_CGC_CTRL__SDB_MODE_MASK);
  595. WREG32(mmUVD_CGC_CTRL, data);
  596. WREG32(mmUVD_SUVD_CGC_CTRL, data2);
  597. }
  598. #if 0
  599. static void uvd_v5_0_set_hw_clock_gating(struct amdgpu_device *adev)
  600. {
  601. uint32_t data, data1, cgc_flags, suvd_flags;
  602. data = RREG32(mmUVD_CGC_GATE);
  603. data1 = RREG32(mmUVD_SUVD_CGC_GATE);
  604. cgc_flags = UVD_CGC_GATE__SYS_MASK |
  605. UVD_CGC_GATE__UDEC_MASK |
  606. UVD_CGC_GATE__MPEG2_MASK |
  607. UVD_CGC_GATE__RBC_MASK |
  608. UVD_CGC_GATE__LMI_MC_MASK |
  609. UVD_CGC_GATE__IDCT_MASK |
  610. UVD_CGC_GATE__MPRD_MASK |
  611. UVD_CGC_GATE__MPC_MASK |
  612. UVD_CGC_GATE__LBSI_MASK |
  613. UVD_CGC_GATE__LRBBM_MASK |
  614. UVD_CGC_GATE__UDEC_RE_MASK |
  615. UVD_CGC_GATE__UDEC_CM_MASK |
  616. UVD_CGC_GATE__UDEC_IT_MASK |
  617. UVD_CGC_GATE__UDEC_DB_MASK |
  618. UVD_CGC_GATE__UDEC_MP_MASK |
  619. UVD_CGC_GATE__WCB_MASK |
  620. UVD_CGC_GATE__VCPU_MASK |
  621. UVD_CGC_GATE__SCPU_MASK;
  622. suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |
  623. UVD_SUVD_CGC_GATE__SIT_MASK |
  624. UVD_SUVD_CGC_GATE__SMP_MASK |
  625. UVD_SUVD_CGC_GATE__SCM_MASK |
  626. UVD_SUVD_CGC_GATE__SDB_MASK;
  627. data |= cgc_flags;
  628. data1 |= suvd_flags;
  629. WREG32(mmUVD_CGC_GATE, data);
  630. WREG32(mmUVD_SUVD_CGC_GATE, data1);
  631. }
  632. #endif
  633. static void uvd_v5_0_enable_mgcg(struct amdgpu_device *adev,
  634. bool enable)
  635. {
  636. u32 orig, data;
  637. if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) {
  638. data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL);
  639. data |= 0xfff;
  640. WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data);
  641. orig = data = RREG32(mmUVD_CGC_CTRL);
  642. data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
  643. if (orig != data)
  644. WREG32(mmUVD_CGC_CTRL, data);
  645. } else {
  646. data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL);
  647. data &= ~0xfff;
  648. WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data);
  649. orig = data = RREG32(mmUVD_CGC_CTRL);
  650. data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
  651. if (orig != data)
  652. WREG32(mmUVD_CGC_CTRL, data);
  653. }
  654. }
  655. static int uvd_v5_0_set_clockgating_state(void *handle,
  656. enum amd_clockgating_state state)
  657. {
  658. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  659. bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
  660. if (enable) {
  661. /* wait for STATUS to clear */
  662. if (uvd_v5_0_wait_for_idle(handle))
  663. return -EBUSY;
  664. uvd_v5_0_enable_clock_gating(adev, true);
  665. /* enable HW gates because UVD is idle */
  666. /* uvd_v5_0_set_hw_clock_gating(adev); */
  667. } else {
  668. uvd_v5_0_enable_clock_gating(adev, false);
  669. }
  670. uvd_v5_0_set_sw_clock_gating(adev);
  671. return 0;
  672. }
  673. static int uvd_v5_0_set_powergating_state(void *handle,
  674. enum amd_powergating_state state)
  675. {
  676. /* This doesn't actually powergate the UVD block.
  677. * That's done in the dpm code via the SMC. This
  678. * just re-inits the block as necessary. The actual
  679. * gating still happens in the dpm code. We should
  680. * revisit this when there is a cleaner line between
  681. * the smc and the hw blocks
  682. */
  683. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  684. int ret = 0;
  685. if (state == AMD_PG_STATE_GATE) {
  686. uvd_v5_0_stop(adev);
  687. } else {
  688. ret = uvd_v5_0_start(adev);
  689. if (ret)
  690. goto out;
  691. }
  692. out:
  693. return ret;
  694. }
  695. static void uvd_v5_0_get_clockgating_state(void *handle, u32 *flags)
  696. {
  697. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  698. int data;
  699. mutex_lock(&adev->pm.mutex);
  700. if (RREG32_SMC(ixCURRENT_PG_STATUS) &
  701. CURRENT_PG_STATUS__UVD_PG_STATUS_MASK) {
  702. DRM_INFO("Cannot get clockgating state when UVD is powergated.\n");
  703. goto out;
  704. }
  705. /* AMD_CG_SUPPORT_UVD_MGCG */
  706. data = RREG32(mmUVD_CGC_CTRL);
  707. if (data & UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK)
  708. *flags |= AMD_CG_SUPPORT_UVD_MGCG;
  709. out:
  710. mutex_unlock(&adev->pm.mutex);
  711. }
  712. static const struct amd_ip_funcs uvd_v5_0_ip_funcs = {
  713. .name = "uvd_v5_0",
  714. .early_init = uvd_v5_0_early_init,
  715. .late_init = NULL,
  716. .sw_init = uvd_v5_0_sw_init,
  717. .sw_fini = uvd_v5_0_sw_fini,
  718. .hw_init = uvd_v5_0_hw_init,
  719. .hw_fini = uvd_v5_0_hw_fini,
  720. .suspend = uvd_v5_0_suspend,
  721. .resume = uvd_v5_0_resume,
  722. .is_idle = uvd_v5_0_is_idle,
  723. .wait_for_idle = uvd_v5_0_wait_for_idle,
  724. .soft_reset = uvd_v5_0_soft_reset,
  725. .set_clockgating_state = uvd_v5_0_set_clockgating_state,
  726. .set_powergating_state = uvd_v5_0_set_powergating_state,
  727. .get_clockgating_state = uvd_v5_0_get_clockgating_state,
  728. };
  729. static const struct amdgpu_ring_funcs uvd_v5_0_ring_funcs = {
  730. .type = AMDGPU_RING_TYPE_UVD,
  731. .align_mask = 0xf,
  732. .nop = PACKET0(mmUVD_NO_OP, 0),
  733. .support_64bit_ptrs = false,
  734. .get_rptr = uvd_v5_0_ring_get_rptr,
  735. .get_wptr = uvd_v5_0_ring_get_wptr,
  736. .set_wptr = uvd_v5_0_ring_set_wptr,
  737. .parse_cs = amdgpu_uvd_ring_parse_cs,
  738. .emit_frame_size =
  739. 2 + /* uvd_v5_0_ring_emit_hdp_flush */
  740. 2 + /* uvd_v5_0_ring_emit_hdp_invalidate */
  741. 14, /* uvd_v5_0_ring_emit_fence x1 no user fence */
  742. .emit_ib_size = 6, /* uvd_v5_0_ring_emit_ib */
  743. .emit_ib = uvd_v5_0_ring_emit_ib,
  744. .emit_fence = uvd_v5_0_ring_emit_fence,
  745. .emit_hdp_flush = uvd_v5_0_ring_emit_hdp_flush,
  746. .emit_hdp_invalidate = uvd_v5_0_ring_emit_hdp_invalidate,
  747. .test_ring = uvd_v5_0_ring_test_ring,
  748. .test_ib = amdgpu_uvd_ring_test_ib,
  749. .insert_nop = amdgpu_ring_insert_nop,
  750. .pad_ib = amdgpu_ring_generic_pad_ib,
  751. .begin_use = amdgpu_uvd_ring_begin_use,
  752. .end_use = amdgpu_uvd_ring_end_use,
  753. };
  754. static void uvd_v5_0_set_ring_funcs(struct amdgpu_device *adev)
  755. {
  756. adev->uvd.ring.funcs = &uvd_v5_0_ring_funcs;
  757. }
  758. static const struct amdgpu_irq_src_funcs uvd_v5_0_irq_funcs = {
  759. .set = uvd_v5_0_set_interrupt_state,
  760. .process = uvd_v5_0_process_interrupt,
  761. };
  762. static void uvd_v5_0_set_irq_funcs(struct amdgpu_device *adev)
  763. {
  764. adev->uvd.irq.num_types = 1;
  765. adev->uvd.irq.funcs = &uvd_v5_0_irq_funcs;
  766. }
  767. const struct amdgpu_ip_block_version uvd_v5_0_ip_block =
  768. {
  769. .type = AMD_IP_BLOCK_TYPE_UVD,
  770. .major = 5,
  771. .minor = 0,
  772. .rev = 0,
  773. .funcs = &uvd_v5_0_ip_funcs,
  774. };