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/drivers/usb/host/xhci.c

https://gitlab.com/stalker-android/linux-omap3
C | 2719 lines | 1852 code | 284 blank | 583 comment | 252 complexity | e6c12914f80fc38e019d70a1ad08850c MD5 | raw file

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   1/*
   2 * xHCI host controller driver
   3 *
   4 * Copyright (C) 2008 Intel Corp.
   5 *
   6 * Author: Sarah Sharp
   7 * Some code borrowed from the Linux EHCI driver.
   8 *
   9 * This program is free software; you can redistribute it and/or modify
  10 * it under the terms of the GNU General Public License version 2 as
  11 * published by the Free Software Foundation.
  12 *
  13 * This program is distributed in the hope that it will be useful, but
  14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15 * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16 * for more details.
  17 *
  18 * You should have received a copy of the GNU General Public License
  19 * along with this program; if not, write to the Free Software Foundation,
  20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21 */
  22
  23#include <linux/pci.h>
  24#include <linux/irq.h>
  25#include <linux/log2.h>
  26#include <linux/module.h>
  27#include <linux/moduleparam.h>
  28#include <linux/slab.h>
  29
  30#include "xhci.h"
  31
  32#define DRIVER_AUTHOR "Sarah Sharp"
  33#define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
  34
  35/* Some 0.95 hardware can't handle the chain bit on a Link TRB being cleared */
  36static int link_quirk;
  37module_param(link_quirk, int, S_IRUGO | S_IWUSR);
  38MODULE_PARM_DESC(link_quirk, "Don't clear the chain bit on a link TRB");
  39
  40/* TODO: copied from ehci-hcd.c - can this be refactored? */
  41/*
  42 * handshake - spin reading hc until handshake completes or fails
  43 * @ptr: address of hc register to be read
  44 * @mask: bits to look at in result of read
  45 * @done: value of those bits when handshake succeeds
  46 * @usec: timeout in microseconds
  47 *
  48 * Returns negative errno, or zero on success
  49 *
  50 * Success happens when the "mask" bits have the specified value (hardware
  51 * handshake done).  There are two failure modes:  "usec" have passed (major
  52 * hardware flakeout), or the register reads as all-ones (hardware removed).
  53 */
  54static int handshake(struct xhci_hcd *xhci, void __iomem *ptr,
  55		      u32 mask, u32 done, int usec)
  56{
  57	u32	result;
  58
  59	do {
  60		result = xhci_readl(xhci, ptr);
  61		if (result == ~(u32)0)		/* card removed */
  62			return -ENODEV;
  63		result &= mask;
  64		if (result == done)
  65			return 0;
  66		udelay(1);
  67		usec--;
  68	} while (usec > 0);
  69	return -ETIMEDOUT;
  70}
  71
  72/*
  73 * Disable interrupts and begin the xHCI halting process.
  74 */
  75void xhci_quiesce(struct xhci_hcd *xhci)
  76{
  77	u32 halted;
  78	u32 cmd;
  79	u32 mask;
  80
  81	mask = ~(XHCI_IRQS);
  82	halted = xhci_readl(xhci, &xhci->op_regs->status) & STS_HALT;
  83	if (!halted)
  84		mask &= ~CMD_RUN;
  85
  86	cmd = xhci_readl(xhci, &xhci->op_regs->command);
  87	cmd &= mask;
  88	xhci_writel(xhci, cmd, &xhci->op_regs->command);
  89}
  90
  91/*
  92 * Force HC into halt state.
  93 *
  94 * Disable any IRQs and clear the run/stop bit.
  95 * HC will complete any current and actively pipelined transactions, and
  96 * should halt within 16 microframes of the run/stop bit being cleared.
  97 * Read HC Halted bit in the status register to see when the HC is finished.
  98 * XXX: shouldn't we set HC_STATE_HALT here somewhere?
  99 */
 100int xhci_halt(struct xhci_hcd *xhci)
 101{
 102	xhci_dbg(xhci, "// Halt the HC\n");
 103	xhci_quiesce(xhci);
 104
 105	return handshake(xhci, &xhci->op_regs->status,
 106			STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);
 107}
 108
 109/*
 110 * Set the run bit and wait for the host to be running.
 111 */
 112int xhci_start(struct xhci_hcd *xhci)
 113{
 114	u32 temp;
 115	int ret;
 116
 117	temp = xhci_readl(xhci, &xhci->op_regs->command);
 118	temp |= (CMD_RUN);
 119	xhci_dbg(xhci, "// Turn on HC, cmd = 0x%x.\n",
 120			temp);
 121	xhci_writel(xhci, temp, &xhci->op_regs->command);
 122
 123	/*
 124	 * Wait for the HCHalted Status bit to be 0 to indicate the host is
 125	 * running.
 126	 */
 127	ret = handshake(xhci, &xhci->op_regs->status,
 128			STS_HALT, 0, XHCI_MAX_HALT_USEC);
 129	if (ret == -ETIMEDOUT)
 130		xhci_err(xhci, "Host took too long to start, "
 131				"waited %u microseconds.\n",
 132				XHCI_MAX_HALT_USEC);
 133	return ret;
 134}
 135
 136/*
 137 * Reset a halted HC, and set the internal HC state to HC_STATE_HALT.
 138 *
 139 * This resets pipelines, timers, counters, state machines, etc.
 140 * Transactions will be terminated immediately, and operational registers
 141 * will be set to their defaults.
 142 */
 143int xhci_reset(struct xhci_hcd *xhci)
 144{
 145	u32 command;
 146	u32 state;
 147	int ret;
 148
 149	state = xhci_readl(xhci, &xhci->op_regs->status);
 150	if ((state & STS_HALT) == 0) {
 151		xhci_warn(xhci, "Host controller not halted, aborting reset.\n");
 152		return 0;
 153	}
 154
 155	xhci_dbg(xhci, "// Reset the HC\n");
 156	command = xhci_readl(xhci, &xhci->op_regs->command);
 157	command |= CMD_RESET;
 158	xhci_writel(xhci, command, &xhci->op_regs->command);
 159	/* XXX: Why does EHCI set this here?  Shouldn't other code do this? */
 160	xhci_to_hcd(xhci)->state = HC_STATE_HALT;
 161
 162	ret = handshake(xhci, &xhci->op_regs->command,
 163			CMD_RESET, 0, 250 * 1000);
 164	if (ret)
 165		return ret;
 166
 167	xhci_dbg(xhci, "Wait for controller to be ready for doorbell rings\n");
 168	/*
 169	 * xHCI cannot write to any doorbells or operational registers other
 170	 * than status until the "Controller Not Ready" flag is cleared.
 171	 */
 172	return handshake(xhci, &xhci->op_regs->status, STS_CNR, 0, 250 * 1000);
 173}
 174
 175/*
 176 * Free IRQs
 177 * free all IRQs request
 178 */
 179static void xhci_free_irq(struct xhci_hcd *xhci)
 180{
 181	int i;
 182	struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
 183
 184	/* return if using legacy interrupt */
 185	if (xhci_to_hcd(xhci)->irq >= 0)
 186		return;
 187
 188	if (xhci->msix_entries) {
 189		for (i = 0; i < xhci->msix_count; i++)
 190			if (xhci->msix_entries[i].vector)
 191				free_irq(xhci->msix_entries[i].vector,
 192						xhci_to_hcd(xhci));
 193	} else if (pdev->irq >= 0)
 194		free_irq(pdev->irq, xhci_to_hcd(xhci));
 195
 196	return;
 197}
 198
 199/*
 200 * Set up MSI
 201 */
 202static int xhci_setup_msi(struct xhci_hcd *xhci)
 203{
 204	int ret;
 205	struct pci_dev  *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
 206
 207	ret = pci_enable_msi(pdev);
 208	if (ret) {
 209		xhci_err(xhci, "failed to allocate MSI entry\n");
 210		return ret;
 211	}
 212
 213	ret = request_irq(pdev->irq, (irq_handler_t)xhci_msi_irq,
 214				0, "xhci_hcd", xhci_to_hcd(xhci));
 215	if (ret) {
 216		xhci_err(xhci, "disable MSI interrupt\n");
 217		pci_disable_msi(pdev);
 218	}
 219
 220	return ret;
 221}
 222
 223/*
 224 * Set up MSI-X
 225 */
 226static int xhci_setup_msix(struct xhci_hcd *xhci)
 227{
 228	int i, ret = 0;
 229	struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
 230
 231	/*
 232	 * calculate number of msi-x vectors supported.
 233	 * - HCS_MAX_INTRS: the max number of interrupts the host can handle,
 234	 *   with max number of interrupters based on the xhci HCSPARAMS1.
 235	 * - num_online_cpus: maximum msi-x vectors per CPUs core.
 236	 *   Add additional 1 vector to ensure always available interrupt.
 237	 */
 238	xhci->msix_count = min(num_online_cpus() + 1,
 239				HCS_MAX_INTRS(xhci->hcs_params1));
 240
 241	xhci->msix_entries =
 242		kmalloc((sizeof(struct msix_entry))*xhci->msix_count,
 243				GFP_KERNEL);
 244	if (!xhci->msix_entries) {
 245		xhci_err(xhci, "Failed to allocate MSI-X entries\n");
 246		return -ENOMEM;
 247	}
 248
 249	for (i = 0; i < xhci->msix_count; i++) {
 250		xhci->msix_entries[i].entry = i;
 251		xhci->msix_entries[i].vector = 0;
 252	}
 253
 254	ret = pci_enable_msix(pdev, xhci->msix_entries, xhci->msix_count);
 255	if (ret) {
 256		xhci_err(xhci, "Failed to enable MSI-X\n");
 257		goto free_entries;
 258	}
 259
 260	for (i = 0; i < xhci->msix_count; i++) {
 261		ret = request_irq(xhci->msix_entries[i].vector,
 262				(irq_handler_t)xhci_msi_irq,
 263				0, "xhci_hcd", xhci_to_hcd(xhci));
 264		if (ret)
 265			goto disable_msix;
 266	}
 267
 268	return ret;
 269
 270disable_msix:
 271	xhci_err(xhci, "disable MSI-X interrupt\n");
 272	xhci_free_irq(xhci);
 273	pci_disable_msix(pdev);
 274free_entries:
 275	kfree(xhci->msix_entries);
 276	xhci->msix_entries = NULL;
 277	return ret;
 278}
 279
 280/* Free any IRQs and disable MSI-X */
 281static void xhci_cleanup_msix(struct xhci_hcd *xhci)
 282{
 283	struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
 284
 285	xhci_free_irq(xhci);
 286
 287	if (xhci->msix_entries) {
 288		pci_disable_msix(pdev);
 289		kfree(xhci->msix_entries);
 290		xhci->msix_entries = NULL;
 291	} else {
 292		pci_disable_msi(pdev);
 293	}
 294
 295	return;
 296}
 297
 298/*
 299 * Initialize memory for HCD and xHC (one-time init).
 300 *
 301 * Program the PAGESIZE register, initialize the device context array, create
 302 * device contexts (?), set up a command ring segment (or two?), create event
 303 * ring (one for now).
 304 */
 305int xhci_init(struct usb_hcd *hcd)
 306{
 307	struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 308	int retval = 0;
 309
 310	xhci_dbg(xhci, "xhci_init\n");
 311	spin_lock_init(&xhci->lock);
 312	if (link_quirk) {
 313		xhci_dbg(xhci, "QUIRK: Not clearing Link TRB chain bits.\n");
 314		xhci->quirks |= XHCI_LINK_TRB_QUIRK;
 315	} else {
 316		xhci_dbg(xhci, "xHCI doesn't need link TRB QUIRK\n");
 317	}
 318	retval = xhci_mem_init(xhci, GFP_KERNEL);
 319	xhci_dbg(xhci, "Finished xhci_init\n");
 320
 321	return retval;
 322}
 323
 324/*-------------------------------------------------------------------------*/
 325
 326
 327#ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
 328void xhci_event_ring_work(unsigned long arg)
 329{
 330	unsigned long flags;
 331	int temp;
 332	u64 temp_64;
 333	struct xhci_hcd *xhci = (struct xhci_hcd *) arg;
 334	int i, j;
 335
 336	xhci_dbg(xhci, "Poll event ring: %lu\n", jiffies);
 337
 338	spin_lock_irqsave(&xhci->lock, flags);
 339	temp = xhci_readl(xhci, &xhci->op_regs->status);
 340	xhci_dbg(xhci, "op reg status = 0x%x\n", temp);
 341	if (temp == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING)) {
 342		xhci_dbg(xhci, "HW died, polling stopped.\n");
 343		spin_unlock_irqrestore(&xhci->lock, flags);
 344		return;
 345	}
 346
 347	temp = xhci_readl(xhci, &xhci->ir_set->irq_pending);
 348	xhci_dbg(xhci, "ir_set 0 pending = 0x%x\n", temp);
 349	xhci_dbg(xhci, "No-op commands handled = %d\n", xhci->noops_handled);
 350	xhci_dbg(xhci, "HC error bitmask = 0x%x\n", xhci->error_bitmask);
 351	xhci->error_bitmask = 0;
 352	xhci_dbg(xhci, "Event ring:\n");
 353	xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
 354	xhci_dbg_ring_ptrs(xhci, xhci->event_ring);
 355	temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
 356	temp_64 &= ~ERST_PTR_MASK;
 357	xhci_dbg(xhci, "ERST deq = 64'h%0lx\n", (long unsigned int) temp_64);
 358	xhci_dbg(xhci, "Command ring:\n");
 359	xhci_debug_segment(xhci, xhci->cmd_ring->deq_seg);
 360	xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring);
 361	xhci_dbg_cmd_ptrs(xhci);
 362	for (i = 0; i < MAX_HC_SLOTS; ++i) {
 363		if (!xhci->devs[i])
 364			continue;
 365		for (j = 0; j < 31; ++j) {
 366			xhci_dbg_ep_rings(xhci, i, j, &xhci->devs[i]->eps[j]);
 367		}
 368	}
 369
 370	if (xhci->noops_submitted != NUM_TEST_NOOPS)
 371		if (xhci_setup_one_noop(xhci))
 372			xhci_ring_cmd_db(xhci);
 373	spin_unlock_irqrestore(&xhci->lock, flags);
 374
 375	if (!xhci->zombie)
 376		mod_timer(&xhci->event_ring_timer, jiffies + POLL_TIMEOUT * HZ);
 377	else
 378		xhci_dbg(xhci, "Quit polling the event ring.\n");
 379}
 380#endif
 381
 382/*
 383 * Start the HC after it was halted.
 384 *
 385 * This function is called by the USB core when the HC driver is added.
 386 * Its opposite is xhci_stop().
 387 *
 388 * xhci_init() must be called once before this function can be called.
 389 * Reset the HC, enable device slot contexts, program DCBAAP, and
 390 * set command ring pointer and event ring pointer.
 391 *
 392 * Setup MSI-X vectors and enable interrupts.
 393 */
 394int xhci_run(struct usb_hcd *hcd)
 395{
 396	u32 temp;
 397	u64 temp_64;
 398	u32 ret;
 399	struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 400	struct pci_dev  *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
 401	void (*doorbell)(struct xhci_hcd *) = NULL;
 402
 403	hcd->uses_new_polling = 1;
 404
 405	xhci_dbg(xhci, "xhci_run\n");
 406	/* unregister the legacy interrupt */
 407	if (hcd->irq)
 408		free_irq(hcd->irq, hcd);
 409	hcd->irq = -1;
 410
 411	ret = xhci_setup_msix(xhci);
 412	if (ret)
 413		/* fall back to msi*/
 414		ret = xhci_setup_msi(xhci);
 415
 416	if (ret) {
 417		/* fall back to legacy interrupt*/
 418		ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED,
 419					hcd->irq_descr, hcd);
 420		if (ret) {
 421			xhci_err(xhci, "request interrupt %d failed\n",
 422					pdev->irq);
 423			return ret;
 424		}
 425		hcd->irq = pdev->irq;
 426	}
 427
 428#ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
 429	init_timer(&xhci->event_ring_timer);
 430	xhci->event_ring_timer.data = (unsigned long) xhci;
 431	xhci->event_ring_timer.function = xhci_event_ring_work;
 432	/* Poll the event ring */
 433	xhci->event_ring_timer.expires = jiffies + POLL_TIMEOUT * HZ;
 434	xhci->zombie = 0;
 435	xhci_dbg(xhci, "Setting event ring polling timer\n");
 436	add_timer(&xhci->event_ring_timer);
 437#endif
 438
 439	xhci_dbg(xhci, "Command ring memory map follows:\n");
 440	xhci_debug_ring(xhci, xhci->cmd_ring);
 441	xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring);
 442	xhci_dbg_cmd_ptrs(xhci);
 443
 444	xhci_dbg(xhci, "ERST memory map follows:\n");
 445	xhci_dbg_erst(xhci, &xhci->erst);
 446	xhci_dbg(xhci, "Event ring:\n");
 447	xhci_debug_ring(xhci, xhci->event_ring);
 448	xhci_dbg_ring_ptrs(xhci, xhci->event_ring);
 449	temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
 450	temp_64 &= ~ERST_PTR_MASK;
 451	xhci_dbg(xhci, "ERST deq = 64'h%0lx\n", (long unsigned int) temp_64);
 452
 453	xhci_dbg(xhci, "// Set the interrupt modulation register\n");
 454	temp = xhci_readl(xhci, &xhci->ir_set->irq_control);
 455	temp &= ~ER_IRQ_INTERVAL_MASK;
 456	temp |= (u32) 160;
 457	xhci_writel(xhci, temp, &xhci->ir_set->irq_control);
 458
 459	/* Set the HCD state before we enable the irqs */
 460	hcd->state = HC_STATE_RUNNING;
 461	temp = xhci_readl(xhci, &xhci->op_regs->command);
 462	temp |= (CMD_EIE);
 463	xhci_dbg(xhci, "// Enable interrupts, cmd = 0x%x.\n",
 464			temp);
 465	xhci_writel(xhci, temp, &xhci->op_regs->command);
 466
 467	temp = xhci_readl(xhci, &xhci->ir_set->irq_pending);
 468	xhci_dbg(xhci, "// Enabling event ring interrupter %p by writing 0x%x to irq_pending\n",
 469			xhci->ir_set, (unsigned int) ER_IRQ_ENABLE(temp));
 470	xhci_writel(xhci, ER_IRQ_ENABLE(temp),
 471			&xhci->ir_set->irq_pending);
 472	xhci_print_ir_set(xhci, xhci->ir_set, 0);
 473
 474	if (NUM_TEST_NOOPS > 0)
 475		doorbell = xhci_setup_one_noop(xhci);
 476	if (xhci->quirks & XHCI_NEC_HOST)
 477		xhci_queue_vendor_command(xhci, 0, 0, 0,
 478				TRB_TYPE(TRB_NEC_GET_FW));
 479
 480	if (xhci_start(xhci)) {
 481		xhci_halt(xhci);
 482		return -ENODEV;
 483	}
 484
 485	if (doorbell)
 486		(*doorbell)(xhci);
 487	if (xhci->quirks & XHCI_NEC_HOST)
 488		xhci_ring_cmd_db(xhci);
 489
 490	xhci_dbg(xhci, "Finished xhci_run\n");
 491	return 0;
 492}
 493
 494/*
 495 * Stop xHCI driver.
 496 *
 497 * This function is called by the USB core when the HC driver is removed.
 498 * Its opposite is xhci_run().
 499 *
 500 * Disable device contexts, disable IRQs, and quiesce the HC.
 501 * Reset the HC, finish any completed transactions, and cleanup memory.
 502 */
 503void xhci_stop(struct usb_hcd *hcd)
 504{
 505	u32 temp;
 506	struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 507
 508	spin_lock_irq(&xhci->lock);
 509	xhci_halt(xhci);
 510	xhci_reset(xhci);
 511	xhci_cleanup_msix(xhci);
 512	spin_unlock_irq(&xhci->lock);
 513
 514#ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
 515	/* Tell the event ring poll function not to reschedule */
 516	xhci->zombie = 1;
 517	del_timer_sync(&xhci->event_ring_timer);
 518#endif
 519
 520	xhci_dbg(xhci, "// Disabling event ring interrupts\n");
 521	temp = xhci_readl(xhci, &xhci->op_regs->status);
 522	xhci_writel(xhci, temp & ~STS_EINT, &xhci->op_regs->status);
 523	temp = xhci_readl(xhci, &xhci->ir_set->irq_pending);
 524	xhci_writel(xhci, ER_IRQ_DISABLE(temp),
 525			&xhci->ir_set->irq_pending);
 526	xhci_print_ir_set(xhci, xhci->ir_set, 0);
 527
 528	xhci_dbg(xhci, "cleaning up memory\n");
 529	xhci_mem_cleanup(xhci);
 530	xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
 531		    xhci_readl(xhci, &xhci->op_regs->status));
 532}
 533
 534/*
 535 * Shutdown HC (not bus-specific)
 536 *
 537 * This is called when the machine is rebooting or halting.  We assume that the
 538 * machine will be powered off, and the HC's internal state will be reset.
 539 * Don't bother to free memory.
 540 */
 541void xhci_shutdown(struct usb_hcd *hcd)
 542{
 543	struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 544
 545	spin_lock_irq(&xhci->lock);
 546	xhci_halt(xhci);
 547	xhci_cleanup_msix(xhci);
 548	spin_unlock_irq(&xhci->lock);
 549
 550	xhci_dbg(xhci, "xhci_shutdown completed - status = %x\n",
 551		    xhci_readl(xhci, &xhci->op_regs->status));
 552}
 553
 554#ifdef CONFIG_PM
 555static void xhci_save_registers(struct xhci_hcd *xhci)
 556{
 557	xhci->s3.command = xhci_readl(xhci, &xhci->op_regs->command);
 558	xhci->s3.dev_nt = xhci_readl(xhci, &xhci->op_regs->dev_notification);
 559	xhci->s3.dcbaa_ptr = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
 560	xhci->s3.config_reg = xhci_readl(xhci, &xhci->op_regs->config_reg);
 561	xhci->s3.irq_pending = xhci_readl(xhci, &xhci->ir_set->irq_pending);
 562	xhci->s3.irq_control = xhci_readl(xhci, &xhci->ir_set->irq_control);
 563	xhci->s3.erst_size = xhci_readl(xhci, &xhci->ir_set->erst_size);
 564	xhci->s3.erst_base = xhci_read_64(xhci, &xhci->ir_set->erst_base);
 565	xhci->s3.erst_dequeue = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
 566}
 567
 568static void xhci_restore_registers(struct xhci_hcd *xhci)
 569{
 570	xhci_writel(xhci, xhci->s3.command, &xhci->op_regs->command);
 571	xhci_writel(xhci, xhci->s3.dev_nt, &xhci->op_regs->dev_notification);
 572	xhci_write_64(xhci, xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr);
 573	xhci_writel(xhci, xhci->s3.config_reg, &xhci->op_regs->config_reg);
 574	xhci_writel(xhci, xhci->s3.irq_pending, &xhci->ir_set->irq_pending);
 575	xhci_writel(xhci, xhci->s3.irq_control, &xhci->ir_set->irq_control);
 576	xhci_writel(xhci, xhci->s3.erst_size, &xhci->ir_set->erst_size);
 577	xhci_write_64(xhci, xhci->s3.erst_base, &xhci->ir_set->erst_base);
 578}
 579
 580static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci)
 581{
 582	u64	val_64;
 583
 584	/* step 2: initialize command ring buffer */
 585	val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
 586	val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
 587		(xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
 588				      xhci->cmd_ring->dequeue) &
 589		 (u64) ~CMD_RING_RSVD_BITS) |
 590		xhci->cmd_ring->cycle_state;
 591	xhci_dbg(xhci, "// Setting command ring address to 0x%llx\n",
 592			(long unsigned long) val_64);
 593	xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
 594}
 595
 596/*
 597 * The whole command ring must be cleared to zero when we suspend the host.
 598 *
 599 * The host doesn't save the command ring pointer in the suspend well, so we
 600 * need to re-program it on resume.  Unfortunately, the pointer must be 64-byte
 601 * aligned, because of the reserved bits in the command ring dequeue pointer
 602 * register.  Therefore, we can't just set the dequeue pointer back in the
 603 * middle of the ring (TRBs are 16-byte aligned).
 604 */
 605static void xhci_clear_command_ring(struct xhci_hcd *xhci)
 606{
 607	struct xhci_ring *ring;
 608	struct xhci_segment *seg;
 609
 610	ring = xhci->cmd_ring;
 611	seg = ring->deq_seg;
 612	do {
 613		memset(seg->trbs, 0, SEGMENT_SIZE);
 614		seg = seg->next;
 615	} while (seg != ring->deq_seg);
 616
 617	/* Reset the software enqueue and dequeue pointers */
 618	ring->deq_seg = ring->first_seg;
 619	ring->dequeue = ring->first_seg->trbs;
 620	ring->enq_seg = ring->deq_seg;
 621	ring->enqueue = ring->dequeue;
 622
 623	/*
 624	 * Ring is now zeroed, so the HW should look for change of ownership
 625	 * when the cycle bit is set to 1.
 626	 */
 627	ring->cycle_state = 1;
 628
 629	/*
 630	 * Reset the hardware dequeue pointer.
 631	 * Yes, this will need to be re-written after resume, but we're paranoid
 632	 * and want to make sure the hardware doesn't access bogus memory
 633	 * because, say, the BIOS or an SMI started the host without changing
 634	 * the command ring pointers.
 635	 */
 636	xhci_set_cmd_ring_deq(xhci);
 637}
 638
 639/*
 640 * Stop HC (not bus-specific)
 641 *
 642 * This is called when the machine transition into S3/S4 mode.
 643 *
 644 */
 645int xhci_suspend(struct xhci_hcd *xhci)
 646{
 647	int			rc = 0;
 648	struct usb_hcd		*hcd = xhci_to_hcd(xhci);
 649	u32			command;
 650
 651	spin_lock_irq(&xhci->lock);
 652	clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
 653	/* step 1: stop endpoint */
 654	/* skipped assuming that port suspend has done */
 655
 656	/* step 2: clear Run/Stop bit */
 657	command = xhci_readl(xhci, &xhci->op_regs->command);
 658	command &= ~CMD_RUN;
 659	xhci_writel(xhci, command, &xhci->op_regs->command);
 660	if (handshake(xhci, &xhci->op_regs->status,
 661		      STS_HALT, STS_HALT, 100*100)) {
 662		xhci_warn(xhci, "WARN: xHC CMD_RUN timeout\n");
 663		spin_unlock_irq(&xhci->lock);
 664		return -ETIMEDOUT;
 665	}
 666	xhci_clear_command_ring(xhci);
 667
 668	/* step 3: save registers */
 669	xhci_save_registers(xhci);
 670
 671	/* step 4: set CSS flag */
 672	command = xhci_readl(xhci, &xhci->op_regs->command);
 673	command |= CMD_CSS;
 674	xhci_writel(xhci, command, &xhci->op_regs->command);
 675	if (handshake(xhci, &xhci->op_regs->status, STS_SAVE, 0, 10*100)) {
 676		xhci_warn(xhci, "WARN: xHC CMD_CSS timeout\n");
 677		spin_unlock_irq(&xhci->lock);
 678		return -ETIMEDOUT;
 679	}
 680	/* step 5: remove core well power */
 681	xhci_cleanup_msix(xhci);
 682	spin_unlock_irq(&xhci->lock);
 683
 684	return rc;
 685}
 686
 687/*
 688 * start xHC (not bus-specific)
 689 *
 690 * This is called when the machine transition from S3/S4 mode.
 691 *
 692 */
 693int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
 694{
 695	u32			command, temp = 0;
 696	struct usb_hcd		*hcd = xhci_to_hcd(xhci);
 697	struct pci_dev		*pdev = to_pci_dev(hcd->self.controller);
 698	int	old_state, retval;
 699
 700	old_state = hcd->state;
 701	if (time_before(jiffies, xhci->next_statechange))
 702		msleep(100);
 703
 704	spin_lock_irq(&xhci->lock);
 705
 706	if (!hibernated) {
 707		/* step 1: restore register */
 708		xhci_restore_registers(xhci);
 709		/* step 2: initialize command ring buffer */
 710		xhci_set_cmd_ring_deq(xhci);
 711		/* step 3: restore state and start state*/
 712		/* step 3: set CRS flag */
 713		command = xhci_readl(xhci, &xhci->op_regs->command);
 714		command |= CMD_CRS;
 715		xhci_writel(xhci, command, &xhci->op_regs->command);
 716		if (handshake(xhci, &xhci->op_regs->status,
 717			      STS_RESTORE, 0, 10*100)) {
 718			xhci_dbg(xhci, "WARN: xHC CMD_CSS timeout\n");
 719			spin_unlock_irq(&xhci->lock);
 720			return -ETIMEDOUT;
 721		}
 722		temp = xhci_readl(xhci, &xhci->op_regs->status);
 723	}
 724
 725	/* If restore operation fails, re-initialize the HC during resume */
 726	if ((temp & STS_SRE) || hibernated) {
 727		usb_root_hub_lost_power(hcd->self.root_hub);
 728
 729		xhci_dbg(xhci, "Stop HCD\n");
 730		xhci_halt(xhci);
 731		xhci_reset(xhci);
 732		if (hibernated)
 733			xhci_cleanup_msix(xhci);
 734		spin_unlock_irq(&xhci->lock);
 735
 736#ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
 737		/* Tell the event ring poll function not to reschedule */
 738		xhci->zombie = 1;
 739		del_timer_sync(&xhci->event_ring_timer);
 740#endif
 741
 742		xhci_dbg(xhci, "// Disabling event ring interrupts\n");
 743		temp = xhci_readl(xhci, &xhci->op_regs->status);
 744		xhci_writel(xhci, temp & ~STS_EINT, &xhci->op_regs->status);
 745		temp = xhci_readl(xhci, &xhci->ir_set->irq_pending);
 746		xhci_writel(xhci, ER_IRQ_DISABLE(temp),
 747				&xhci->ir_set->irq_pending);
 748		xhci_print_ir_set(xhci, xhci->ir_set, 0);
 749
 750		xhci_dbg(xhci, "cleaning up memory\n");
 751		xhci_mem_cleanup(xhci);
 752		xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
 753			    xhci_readl(xhci, &xhci->op_regs->status));
 754
 755		xhci_dbg(xhci, "Initialize the HCD\n");
 756		retval = xhci_init(hcd);
 757		if (retval)
 758			return retval;
 759
 760		xhci_dbg(xhci, "Start the HCD\n");
 761		retval = xhci_run(hcd);
 762		if (!retval)
 763			set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
 764		hcd->state = HC_STATE_SUSPENDED;
 765		return retval;
 766	}
 767
 768	spin_unlock_irq(&xhci->lock);
 769	/* Re-setup MSI-X */
 770	if (hcd->irq)
 771		free_irq(hcd->irq, hcd);
 772	hcd->irq = -1;
 773
 774	retval = xhci_setup_msix(xhci);
 775	if (retval)
 776		/* fall back to msi*/
 777		retval = xhci_setup_msi(xhci);
 778
 779	if (retval) {
 780		/* fall back to legacy interrupt*/
 781		retval = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED,
 782					hcd->irq_descr, hcd);
 783		if (retval) {
 784			xhci_err(xhci, "request interrupt %d failed\n",
 785					pdev->irq);
 786			return retval;
 787		}
 788		hcd->irq = pdev->irq;
 789	}
 790
 791	spin_lock_irq(&xhci->lock);
 792	/* step 4: set Run/Stop bit */
 793	command = xhci_readl(xhci, &xhci->op_regs->command);
 794	command |= CMD_RUN;
 795	xhci_writel(xhci, command, &xhci->op_regs->command);
 796	handshake(xhci, &xhci->op_regs->status, STS_HALT,
 797		  0, 250 * 1000);
 798
 799	/* step 5: walk topology and initialize portsc,
 800	 * portpmsc and portli
 801	 */
 802	/* this is done in bus_resume */
 803
 804	/* step 6: restart each of the previously
 805	 * Running endpoints by ringing their doorbells
 806	 */
 807
 808	set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
 809	if (!hibernated)
 810		hcd->state = old_state;
 811	else
 812		hcd->state = HC_STATE_SUSPENDED;
 813
 814	spin_unlock_irq(&xhci->lock);
 815	return 0;
 816}
 817#endif	/* CONFIG_PM */
 818
 819/*-------------------------------------------------------------------------*/
 820
 821/**
 822 * xhci_get_endpoint_index - Used for passing endpoint bitmasks between the core and
 823 * HCDs.  Find the index for an endpoint given its descriptor.  Use the return
 824 * value to right shift 1 for the bitmask.
 825 *
 826 * Index  = (epnum * 2) + direction - 1,
 827 * where direction = 0 for OUT, 1 for IN.
 828 * For control endpoints, the IN index is used (OUT index is unused), so
 829 * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
 830 */
 831unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc)
 832{
 833	unsigned int index;
 834	if (usb_endpoint_xfer_control(desc))
 835		index = (unsigned int) (usb_endpoint_num(desc)*2);
 836	else
 837		index = (unsigned int) (usb_endpoint_num(desc)*2) +
 838			(usb_endpoint_dir_in(desc) ? 1 : 0) - 1;
 839	return index;
 840}
 841
 842/* Find the flag for this endpoint (for use in the control context).  Use the
 843 * endpoint index to create a bitmask.  The slot context is bit 0, endpoint 0 is
 844 * bit 1, etc.
 845 */
 846unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc)
 847{
 848	return 1 << (xhci_get_endpoint_index(desc) + 1);
 849}
 850
 851/* Find the flag for this endpoint (for use in the control context).  Use the
 852 * endpoint index to create a bitmask.  The slot context is bit 0, endpoint 0 is
 853 * bit 1, etc.
 854 */
 855unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index)
 856{
 857	return 1 << (ep_index + 1);
 858}
 859
 860/* Compute the last valid endpoint context index.  Basically, this is the
 861 * endpoint index plus one.  For slot contexts with more than valid endpoint,
 862 * we find the most significant bit set in the added contexts flags.
 863 * e.g. ep 1 IN (with epnum 0x81) => added_ctxs = 0b1000
 864 * fls(0b1000) = 4, but the endpoint context index is 3, so subtract one.
 865 */
 866unsigned int xhci_last_valid_endpoint(u32 added_ctxs)
 867{
 868	return fls(added_ctxs) - 1;
 869}
 870
 871/* Returns 1 if the arguments are OK;
 872 * returns 0 this is a root hub; returns -EINVAL for NULL pointers.
 873 */
 874int xhci_check_args(struct usb_hcd *hcd, struct usb_device *udev,
 875		struct usb_host_endpoint *ep, int check_ep, bool check_virt_dev,
 876		const char *func) {
 877	struct xhci_hcd	*xhci;
 878	struct xhci_virt_device	*virt_dev;
 879
 880	if (!hcd || (check_ep && !ep) || !udev) {
 881		printk(KERN_DEBUG "xHCI %s called with invalid args\n",
 882				func);
 883		return -EINVAL;
 884	}
 885	if (!udev->parent) {
 886		printk(KERN_DEBUG "xHCI %s called for root hub\n",
 887				func);
 888		return 0;
 889	}
 890
 891	if (check_virt_dev) {
 892		xhci = hcd_to_xhci(hcd);
 893		if (!udev->slot_id || !xhci->devs
 894			|| !xhci->devs[udev->slot_id]) {
 895			printk(KERN_DEBUG "xHCI %s called with unaddressed "
 896						"device\n", func);
 897			return -EINVAL;
 898		}
 899
 900		virt_dev = xhci->devs[udev->slot_id];
 901		if (virt_dev->udev != udev) {
 902			printk(KERN_DEBUG "xHCI %s called with udev and "
 903					  "virt_dev does not match\n", func);
 904			return -EINVAL;
 905		}
 906	}
 907
 908	return 1;
 909}
 910
 911static int xhci_configure_endpoint(struct xhci_hcd *xhci,
 912		struct usb_device *udev, struct xhci_command *command,
 913		bool ctx_change, bool must_succeed);
 914
 915/*
 916 * Full speed devices may have a max packet size greater than 8 bytes, but the
 917 * USB core doesn't know that until it reads the first 8 bytes of the
 918 * descriptor.  If the usb_device's max packet size changes after that point,
 919 * we need to issue an evaluate context command and wait on it.
 920 */
 921static int xhci_check_maxpacket(struct xhci_hcd *xhci, unsigned int slot_id,
 922		unsigned int ep_index, struct urb *urb)
 923{
 924	struct xhci_container_ctx *in_ctx;
 925	struct xhci_container_ctx *out_ctx;
 926	struct xhci_input_control_ctx *ctrl_ctx;
 927	struct xhci_ep_ctx *ep_ctx;
 928	int max_packet_size;
 929	int hw_max_packet_size;
 930	int ret = 0;
 931
 932	out_ctx = xhci->devs[slot_id]->out_ctx;
 933	ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
 934	hw_max_packet_size = MAX_PACKET_DECODED(ep_ctx->ep_info2);
 935	max_packet_size = urb->dev->ep0.desc.wMaxPacketSize;
 936	if (hw_max_packet_size != max_packet_size) {
 937		xhci_dbg(xhci, "Max Packet Size for ep 0 changed.\n");
 938		xhci_dbg(xhci, "Max packet size in usb_device = %d\n",
 939				max_packet_size);
 940		xhci_dbg(xhci, "Max packet size in xHCI HW = %d\n",
 941				hw_max_packet_size);
 942		xhci_dbg(xhci, "Issuing evaluate context command.\n");
 943
 944		/* Set up the modified control endpoint 0 */
 945		xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
 946				xhci->devs[slot_id]->out_ctx, ep_index);
 947		in_ctx = xhci->devs[slot_id]->in_ctx;
 948		ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
 949		ep_ctx->ep_info2 &= ~MAX_PACKET_MASK;
 950		ep_ctx->ep_info2 |= MAX_PACKET(max_packet_size);
 951
 952		/* Set up the input context flags for the command */
 953		/* FIXME: This won't work if a non-default control endpoint
 954		 * changes max packet sizes.
 955		 */
 956		ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
 957		ctrl_ctx->add_flags = EP0_FLAG;
 958		ctrl_ctx->drop_flags = 0;
 959
 960		xhci_dbg(xhci, "Slot %d input context\n", slot_id);
 961		xhci_dbg_ctx(xhci, in_ctx, ep_index);
 962		xhci_dbg(xhci, "Slot %d output context\n", slot_id);
 963		xhci_dbg_ctx(xhci, out_ctx, ep_index);
 964
 965		ret = xhci_configure_endpoint(xhci, urb->dev, NULL,
 966				true, false);
 967
 968		/* Clean up the input context for later use by bandwidth
 969		 * functions.
 970		 */
 971		ctrl_ctx->add_flags = SLOT_FLAG;
 972	}
 973	return ret;
 974}
 975
 976/*
 977 * non-error returns are a promise to giveback() the urb later
 978 * we drop ownership so next owner (or urb unlink) can get it
 979 */
 980int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags)
 981{
 982	struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 983	unsigned long flags;
 984	int ret = 0;
 985	unsigned int slot_id, ep_index;
 986	struct urb_priv	*urb_priv;
 987	int size, i;
 988
 989	if (!urb || xhci_check_args(hcd, urb->dev, urb->ep,
 990					true, true, __func__) <= 0)
 991		return -EINVAL;
 992
 993	slot_id = urb->dev->slot_id;
 994	ep_index = xhci_get_endpoint_index(&urb->ep->desc);
 995
 996	if (!HCD_HW_ACCESSIBLE(hcd)) {
 997		if (!in_interrupt())
 998			xhci_dbg(xhci, "urb submitted during PCI suspend\n");
 999		ret = -ESHUTDOWN;
1000		goto exit;
1001	}
1002
1003	if (usb_endpoint_xfer_isoc(&urb->ep->desc))
1004		size = urb->number_of_packets;
1005	else
1006		size = 1;
1007
1008	urb_priv = kzalloc(sizeof(struct urb_priv) +
1009				  size * sizeof(struct xhci_td *), mem_flags);
1010	if (!urb_priv)
1011		return -ENOMEM;
1012
1013	for (i = 0; i < size; i++) {
1014		urb_priv->td[i] = kzalloc(sizeof(struct xhci_td), mem_flags);
1015		if (!urb_priv->td[i]) {
1016			urb_priv->length = i;
1017			xhci_urb_free_priv(xhci, urb_priv);
1018			return -ENOMEM;
1019		}
1020	}
1021
1022	urb_priv->length = size;
1023	urb_priv->td_cnt = 0;
1024	urb->hcpriv = urb_priv;
1025
1026	if (usb_endpoint_xfer_control(&urb->ep->desc)) {
1027		/* Check to see if the max packet size for the default control
1028		 * endpoint changed during FS device enumeration
1029		 */
1030		if (urb->dev->speed == USB_SPEED_FULL) {
1031			ret = xhci_check_maxpacket(xhci, slot_id,
1032					ep_index, urb);
1033			if (ret < 0)
1034				return ret;
1035		}
1036
1037		/* We have a spinlock and interrupts disabled, so we must pass
1038		 * atomic context to this function, which may allocate memory.
1039		 */
1040		spin_lock_irqsave(&xhci->lock, flags);
1041		if (xhci->xhc_state & XHCI_STATE_DYING)
1042			goto dying;
1043		ret = xhci_queue_ctrl_tx(xhci, GFP_ATOMIC, urb,
1044				slot_id, ep_index);
1045		spin_unlock_irqrestore(&xhci->lock, flags);
1046	} else if (usb_endpoint_xfer_bulk(&urb->ep->desc)) {
1047		spin_lock_irqsave(&xhci->lock, flags);
1048		if (xhci->xhc_state & XHCI_STATE_DYING)
1049			goto dying;
1050		if (xhci->devs[slot_id]->eps[ep_index].ep_state &
1051				EP_GETTING_STREAMS) {
1052			xhci_warn(xhci, "WARN: Can't enqueue URB while bulk ep "
1053					"is transitioning to using streams.\n");
1054			ret = -EINVAL;
1055		} else if (xhci->devs[slot_id]->eps[ep_index].ep_state &
1056				EP_GETTING_NO_STREAMS) {
1057			xhci_warn(xhci, "WARN: Can't enqueue URB while bulk ep "
1058					"is transitioning to "
1059					"not having streams.\n");
1060			ret = -EINVAL;
1061		} else {
1062			ret = xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb,
1063					slot_id, ep_index);
1064		}
1065		spin_unlock_irqrestore(&xhci->lock, flags);
1066	} else if (usb_endpoint_xfer_int(&urb->ep->desc)) {
1067		spin_lock_irqsave(&xhci->lock, flags);
1068		if (xhci->xhc_state & XHCI_STATE_DYING)
1069			goto dying;
1070		ret = xhci_queue_intr_tx(xhci, GFP_ATOMIC, urb,
1071				slot_id, ep_index);
1072		spin_unlock_irqrestore(&xhci->lock, flags);
1073	} else {
1074		spin_lock_irqsave(&xhci->lock, flags);
1075		if (xhci->xhc_state & XHCI_STATE_DYING)
1076			goto dying;
1077		ret = xhci_queue_isoc_tx_prepare(xhci, GFP_ATOMIC, urb,
1078				slot_id, ep_index);
1079		spin_unlock_irqrestore(&xhci->lock, flags);
1080	}
1081exit:
1082	return ret;
1083dying:
1084	xhci_urb_free_priv(xhci, urb_priv);
1085	urb->hcpriv = NULL;
1086	xhci_dbg(xhci, "Ep 0x%x: URB %p submitted for "
1087			"non-responsive xHCI host.\n",
1088			urb->ep->desc.bEndpointAddress, urb);
1089	spin_unlock_irqrestore(&xhci->lock, flags);
1090	return -ESHUTDOWN;
1091}
1092
1093/* Get the right ring for the given URB.
1094 * If the endpoint supports streams, boundary check the URB's stream ID.
1095 * If the endpoint doesn't support streams, return the singular endpoint ring.
1096 */
1097static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
1098		struct urb *urb)
1099{
1100	unsigned int slot_id;
1101	unsigned int ep_index;
1102	unsigned int stream_id;
1103	struct xhci_virt_ep *ep;
1104
1105	slot_id = urb->dev->slot_id;
1106	ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1107	stream_id = urb->stream_id;
1108	ep = &xhci->devs[slot_id]->eps[ep_index];
1109	/* Common case: no streams */
1110	if (!(ep->ep_state & EP_HAS_STREAMS))
1111		return ep->ring;
1112
1113	if (stream_id == 0) {
1114		xhci_warn(xhci,
1115				"WARN: Slot ID %u, ep index %u has streams, "
1116				"but URB has no stream ID.\n",
1117				slot_id, ep_index);
1118		return NULL;
1119	}
1120
1121	if (stream_id < ep->stream_info->num_streams)
1122		return ep->stream_info->stream_rings[stream_id];
1123
1124	xhci_warn(xhci,
1125			"WARN: Slot ID %u, ep index %u has "
1126			"stream IDs 1 to %u allocated, "
1127			"but stream ID %u is requested.\n",
1128			slot_id, ep_index,
1129			ep->stream_info->num_streams - 1,
1130			stream_id);
1131	return NULL;
1132}
1133
1134/*
1135 * Remove the URB's TD from the endpoint ring.  This may cause the HC to stop
1136 * USB transfers, potentially stopping in the middle of a TRB buffer.  The HC
1137 * should pick up where it left off in the TD, unless a Set Transfer Ring
1138 * Dequeue Pointer is issued.
1139 *
1140 * The TRBs that make up the buffers for the canceled URB will be "removed" from
1141 * the ring.  Since the ring is a contiguous structure, they can't be physically
1142 * removed.  Instead, there are two options:
1143 *
1144 *  1) If the HC is in the middle of processing the URB to be canceled, we
1145 *     simply move the ring's dequeue pointer past those TRBs using the Set
1146 *     Transfer Ring Dequeue Pointer command.  This will be the common case,
1147 *     when drivers timeout on the last submitted URB and attempt to cancel.
1148 *
1149 *  2) If the HC is in the middle of a different TD, we turn the TRBs into a
1150 *     series of 1-TRB transfer no-op TDs.  (No-ops shouldn't be chained.)  The
1151 *     HC will need to invalidate the any TRBs it has cached after the stop
1152 *     endpoint command, as noted in the xHCI 0.95 errata.
1153 *
1154 *  3) The TD may have completed by the time the Stop Endpoint Command
1155 *     completes, so software needs to handle that case too.
1156 *
1157 * This function should protect against the TD enqueueing code ringing the
1158 * doorbell while this code is waiting for a Stop Endpoint command to complete.
1159 * It also needs to account for multiple cancellations on happening at the same
1160 * time for the same endpoint.
1161 *
1162 * Note that this function can be called in any context, or so says
1163 * usb_hcd_unlink_urb()
1164 */
1165int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
1166{
1167	unsigned long flags;
1168	int ret, i;
1169	u32 temp;
1170	struct xhci_hcd *xhci;
1171	struct urb_priv	*urb_priv;
1172	struct xhci_td *td;
1173	unsigned int ep_index;
1174	struct xhci_ring *ep_ring;
1175	struct xhci_virt_ep *ep;
1176
1177	xhci = hcd_to_xhci(hcd);
1178	spin_lock_irqsave(&xhci->lock, flags);
1179	/* Make sure the URB hasn't completed or been unlinked already */
1180	ret = usb_hcd_check_unlink_urb(hcd, urb, status);
1181	if (ret || !urb->hcpriv)
1182		goto done;
1183	temp = xhci_readl(xhci, &xhci->op_regs->status);
1184	if (temp == 0xffffffff) {
1185		xhci_dbg(xhci, "HW died, freeing TD.\n");
1186		urb_priv = urb->hcpriv;
1187
1188		usb_hcd_unlink_urb_from_ep(hcd, urb);
1189		spin_unlock_irqrestore(&xhci->lock, flags);
1190		usb_hcd_giveback_urb(xhci_to_hcd(xhci), urb, -ESHUTDOWN);
1191		xhci_urb_free_priv(xhci, urb_priv);
1192		return ret;
1193	}
1194	if (xhci->xhc_state & XHCI_STATE_DYING) {
1195		xhci_dbg(xhci, "Ep 0x%x: URB %p to be canceled on "
1196				"non-responsive xHCI host.\n",
1197				urb->ep->desc.bEndpointAddress, urb);
1198		/* Let the stop endpoint command watchdog timer (which set this
1199		 * state) finish cleaning up the endpoint TD lists.  We must
1200		 * have caught it in the middle of dropping a lock and giving
1201		 * back an URB.
1202		 */
1203		goto done;
1204	}
1205
1206	xhci_dbg(xhci, "Cancel URB %p\n", urb);
1207	xhci_dbg(xhci, "Event ring:\n");
1208	xhci_debug_ring(xhci, xhci->event_ring);
1209	ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1210	ep = &xhci->devs[urb->dev->slot_id]->eps[ep_index];
1211	ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
1212	if (!ep_ring) {
1213		ret = -EINVAL;
1214		goto done;
1215	}
1216
1217	xhci_dbg(xhci, "Endpoint ring:\n");
1218	xhci_debug_ring(xhci, ep_ring);
1219
1220	urb_priv = urb->hcpriv;
1221
1222	for (i = urb_priv->td_cnt; i < urb_priv->length; i++) {
1223		td = urb_priv->td[i];
1224		list_add_tail(&td->cancelled_td_list, &ep->cancelled_td_list);
1225	}
1226
1227	/* Queue a stop endpoint command, but only if this is
1228	 * the first cancellation to be handled.
1229	 */
1230	if (!(ep->ep_state & EP_HALT_PENDING)) {
1231		ep->ep_state |= EP_HALT_PENDING;
1232		ep->stop_cmds_pending++;
1233		ep->stop_cmd_timer.expires = jiffies +
1234			XHCI_STOP_EP_CMD_TIMEOUT * HZ;
1235		add_timer(&ep->stop_cmd_timer);
1236		xhci_queue_stop_endpoint(xhci, urb->dev->slot_id, ep_index, 0);
1237		xhci_ring_cmd_db(xhci);
1238	}
1239done:
1240	spin_unlock_irqrestore(&xhci->lock, flags);
1241	return ret;
1242}
1243
1244/* Drop an endpoint from a new bandwidth configuration for this device.
1245 * Only one call to this function is allowed per endpoint before
1246 * check_bandwidth() or reset_bandwidth() must be called.
1247 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1248 * add the endpoint to the schedule with possibly new parameters denoted by a
1249 * different endpoint descriptor in usb_host_endpoint.
1250 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1251 * not allowed.
1252 *
1253 * The USB core will not allow URBs to be queued to an endpoint that is being
1254 * disabled, so there's no need for mutual exclusion to protect
1255 * the xhci->devs[slot_id] structure.
1256 */
1257int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1258		struct usb_host_endpoint *ep)
1259{
1260	struct xhci_hcd *xhci;
1261	struct xhci_container_ctx *in_ctx, *out_ctx;
1262	struct xhci_input_control_ctx *ctrl_ctx;
1263	struct xhci_slot_ctx *slot_ctx;
1264	unsigned int last_ctx;
1265	unsigned int ep_index;
1266	struct xhci_ep_ctx *ep_ctx;
1267	u32 drop_flag;
1268	u32 new_add_flags, new_drop_flags, new_slot_info;
1269	int ret;
1270
1271	ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1272	if (ret <= 0)
1273		return ret;
1274	xhci = hcd_to_xhci(hcd);
1275	xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
1276
1277	drop_flag = xhci_get_endpoint_flag(&ep->desc);
1278	if (drop_flag == SLOT_FLAG || drop_flag == EP0_FLAG) {
1279		xhci_dbg(xhci, "xHCI %s - can't drop slot or ep 0 %#x\n",
1280				__func__, drop_flag);
1281		return 0;
1282	}
1283
1284	in_ctx = xhci->devs[udev->slot_id]->in_ctx;
1285	out_ctx = xhci->devs[udev->slot_id]->out_ctx;
1286	ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
1287	ep_index = xhci_get_endpoint_index(&ep->desc);
1288	ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1289	/* If the HC already knows the endpoint is disabled,
1290	 * or the HCD has noted it is disabled, ignore this request
1291	 */
1292	if ((ep_ctx->ep_info & EP_STATE_MASK) == EP_STATE_DISABLED ||
1293			ctrl_ctx->drop_flags & xhci_get_endpoint_flag(&ep->desc)) {
1294		xhci_warn(xhci, "xHCI %s called with disabled ep %p\n",
1295				__func__, ep);
1296		return 0;
1297	}
1298
1299	ctrl_ctx->drop_flags |= drop_flag;
1300	new_drop_flags = ctrl_ctx->drop_flags;
1301
1302	ctrl_ctx->add_flags &= ~drop_flag;
1303	new_add_flags = ctrl_ctx->add_flags;
1304
1305	last_ctx = xhci_last_valid_endpoint(ctrl_ctx->add_flags);
1306	slot_ctx = xhci_get_slot_ctx(xhci, in_ctx);
1307	/* Update the last valid endpoint context, if we deleted the last one */
1308	if ((slot_ctx->dev_info & LAST_CTX_MASK) > LAST_CTX(last_ctx)) {
1309		slot_ctx->dev_info &= ~LAST_CTX_MASK;
1310		slot_ctx->dev_info |= LAST_CTX(last_ctx);
1311	}
1312	new_slot_info = slot_ctx->dev_info;
1313
1314	xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
1315
1316	xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x, new slot info = %#x\n",
1317			(unsigned int) ep->desc.bEndpointAddress,
1318			udev->slot_id,
1319			(unsigned int) new_drop_flags,
1320			(unsigned int) new_add_flags,
1321			(unsigned int) new_slot_info);
1322	return 0;
1323}
1324
1325/* Add an endpoint to a new possible bandwidth configuration for this device.
1326 * Only one call to this function is allowed per endpoint before
1327 * check_bandwidth() or reset_bandwidth() must be called.
1328 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1329 * add the endpoint to the schedule with possibly new parameters denoted by a
1330 * different endpoint descriptor in usb_host_endpoint.
1331 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1332 * not allowed.
1333 *
1334 * The USB core will not allow URBs to be queued to an endpoint until the
1335 * configuration or alt setting is installed in the device, so there's no need
1336 * for mutual exclusion to protect the xhci->devs[slot_id] structure.
1337 */
1338int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1339		struct usb_host_endpoint *ep)
1340{
1341	struct xhci_hcd *xhci;
1342	struct xhci_container_ctx *in_ctx, *out_ctx;
1343	unsigned int ep_index;
1344	struct xhci_ep_ctx *ep_ctx;
1345	struct xhci_slot_ctx *slot_ctx;
1346	struct xhci_input_control_ctx *ctrl_ctx;
1347	u32 added_ctxs;
1348	unsigned int last_ctx;
1349	u32 new_add_flags, new_drop_flags, new_slot_info;
1350	int ret = 0;
1351
1352	ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1353	if (ret <= 0) {
1354		/* So we won't queue a reset ep command for a root hub */
1355		ep->hcpriv = NULL;
1356		return ret;
1357	}
1358	xhci = hcd_to_xhci(hcd);
1359
1360	added_ctxs = xhci_get_endpoint_flag(&ep->desc);
1361	last_ctx = xhci_last_valid_endpoint(added_ctxs);
1362	if (added_ctxs == SLOT_FLAG || added_ctxs == EP0_FLAG) {
1363		/* FIXME when we have to issue an evaluate endpoint command to
1364		 * deal with ep0 max packet size changing once we get the
1365		 * descriptors
1366		 */
1367		xhci_dbg(xhci, "xHCI %s - can't add slot or ep 0 %#x\n",
1368				__func__, added_ctxs);
1369		return 0;
1370	}
1371
1372	in_ctx = xhci->devs[udev->slot_id]->in_ctx;
1373	out_ctx = xhci->devs[udev->slot_id]->out_ctx;
1374	ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
1375	ep_index = xhci_get_endpoint_index(&ep->desc);
1376	ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1377	/* If the HCD has already noted the endpoint is enabled,
1378	 * ignore this request.
1379	 */
1380	if (ctrl_ctx->add_flags & xhci_get_endpoint_flag(&ep->desc)) {
1381		xhci_warn(xhci, "xHCI %s called with enabled ep %p\n",
1382				__func__, ep);
1383		return 0;
1384	}
1385
1386	/*
1387	 * Configuration and alternate setting changes must be done in
1388	 * process context, not interrupt context (or so documenation
1389	 * for usb_set_interface() and usb_set_configuration() claim).
1390	 */
1391	if (xhci_endpoint_init(xhci, xhci->devs[udev->slot_id],
1392				udev, ep, GFP_NOIO) < 0) {
1393		dev_dbg(&udev->dev, "%s - could not initialize ep %#x\n",
1394				__func__, ep->desc.bEndpointAddress);
1395		return -ENOMEM;
1396	}
1397
1398	ctrl_ctx->add_flags |= added_ctxs;
1399	new_add_flags = ctrl_ctx->add_flags;
1400
1401	/* If xhci_endpoint_disable() was called for this endpoint, but the
1402	 * xHC hasn't been notified yet through the check_bandwidth() call,
1403	 * this re-adds a new state for the endpoint from the new endpoint
1404	 * descriptors.  We must drop and re-add this endpoint, so we leave the
1405	 * drop flags alone.
1406	 */
1407	new_drop_flags = ctrl_ctx->drop_flags;
1408
1409	slot_ctx = xhci_get_slot_ctx(xhci, in_ctx);
1410	/* Update the last valid endpoint context, if we just added one past */
1411	if ((slot_ctx->dev_info & LAST_CTX_MASK) < LAST_CTX(last_ctx)) {
1412		slot_ctx->dev_info &= ~LAST_CTX_MASK;
1413		slot_ctx->dev_info |= LAST_CTX(last_ctx);
1414	}
1415	new_slot_info = slot_ctx->dev_info;
1416
1417	/* Store the usb_device pointer for later use */
1418	ep->hcpriv = udev;
1419
1420	xhci_dbg(xhci, "add ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x, new slot info = %#x\n",
1421			(unsigned int) ep->desc.bEndpointAddress,
1422			udev->slot_id,
1423			(unsigned int) new_drop_flags,
1424			(unsigned int) new_add_flags,
1425			(unsigned int) new_slot_info);
1426	return 0;
1427}
1428
1429static void xhci_zero_in_ctx(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev)
1430{
1431	struct xhci_input_control_ctx *ctrl_ctx;
1432	struct xhci_ep_ctx *ep_ctx;
1433	struct xhci_slot_ctx *slot_ctx;
1434	int i;
1435
1436	/* When a device's add flag and drop flag are zero, any subsequent
1437	 * configure endpoint command will leave that endpoint's state
1438	 * untouched.  Make sure we don't leave any old state in the input
1439	 * endpoint contexts.
1440	 */
1441	ctrl_ctx = xhci_get_input_control_ctx(xhci, virt_dev->in_ctx);
1442	ctrl_ctx->drop_flags = 0;
1443	ctrl_ctx->add_flags = 0;
1444	slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
1445	slot_ctx->dev_info &= ~LAST_CTX_MASK;
1446	/* Endpoint 0 is always valid */
1447	slot_ctx->dev_info |= LAST_CTX(1);
1448	for (i = 1; i < 31; ++i) {
1449		ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, i);
1450		ep_ctx->ep_info = 0;
1451		ep_ctx->ep_info2 = 0;
1452		ep_ctx->deq = 0;
1453		ep_ctx->tx_info = 0;
1454	}
1455}
1456
1457static int xhci_configure_endpoint_result(struct xhci_hcd *xhci,
1458		struct usb_device *udev, int *cmd_status)
1459{
1460	int ret;
1461
1462	switch (*cmd_status) {
1463	case COMP_ENOMEM:
1464		dev_warn(&udev->dev, "Not enough host controller resources "
1465				"for new device state.\n");
1466		ret = -ENOMEM;
1467		/* FIXME: can we allocate more resources for the HC? */
1468		break;
1469	case COMP_BW_ERR:
1470		dev_warn(&udev->dev, "Not enough bandwidth "
1471				"for new device state.\n");
1472		ret = -ENOSPC;
1473		/* FIXME: can we go back to the old state? */
1474		break;
1475	case COMP_TRB_ERR:
1476		/* the HCD set up something wrong */
1477		dev_warn(&udev->dev, "ERROR: Endpoint drop flag = 0, "
1478				"add flag = 1, "
1479				"and endpoint is not disabled.\n");
1480		ret = -EINVAL;
1481		break;
1482	case COMP_SUCCESS:
1483		dev_dbg(&udev->dev, "Successful Endpoint Configure command\n");
1484		ret = 0;
1485		break;
1486	default:
1487		xhci_err(xhci, "ERROR: unexpected command completion "
1488				"code 0x%x.\n", *cmd_status);
1489		ret = -EINVAL;
1490		break;
1491	}
1492	return ret;
1493}
1494
1495static int xhci_evaluate_context_result(struct xhci_hcd *xhci,
1496		struct usb_device *udev, int *cmd_status)
1497{
1498	int ret;
1499	struct xhci_virt_device *virt_dev = xhci->devs[udev->slot_id];
1500
1501	switch (*cmd_status) {
1502	case COMP_EINVAL:
1503		dev_warn(&udev->dev, "WARN: xHCI driver setup invalid evaluate "
1504				"context command.\n");
1505		ret = -EINVAL;
1506		break;
1507	case COMP_EBADSLT:
1508		dev_warn(&udev->dev, "WARN: slot not enabled for"
1509				"evaluate context command.\n");
1510	case COMP_CTX_STATE:
1511		dev_warn(&udev->dev, "WARN: invalid context state for "
1512				"evaluate context command.\n");
1513		xhci_dbg_ctx(xhci, virt_dev->out_ctx, 1);
1514		ret = -EINVAL;
1515		break;
1516	case COMP_SUCCESS:
1517		dev_dbg(&udev->dev, "Successful evaluate context command\n");
1518		ret = 0;
1519		break;
1520	default:
1521		xhci_err(xhci, "ERROR: unexpected command completion "
1522				"code 0x%x.\n", *cmd_status);
1523		ret = -EINVAL;
1524		break;
1525	}
1526	return ret;
1527}
1528
1529/* Issue a configure endpoint command or evaluate context command
1530 * and wait for it to finish.
1531 */
1532static int xhci_configure_endpoint(struct xhci_hcd *xhci,
1533		struct usb_device *udev,
1534		struct xhci_command *command,
1535		bool ctx_change, bool must_succeed)
1536{
1537	int ret;
1538	int timeleft;
1539	unsigned long flags;
1540	struct xhci_container_ctx *in_ctx;
1541	struct completion *cmd_completion;
1542	int *cmd_status;
1543	struct xhci_virt_device *virt_dev;
1544
1545	spin_lock_irqsave(&xhci->lock, flags);
1546	virt_dev = xhci->devs[udev->slot_id];
1547	if (command) {
1548		in_ctx = command->in_ctx;
1549		cmd_completion = command->completion;
1550		cmd_status = &command->status;
1551		command->command_trb = xhci->cmd_ring->enqueue;
1552
1553		/* Enqueue pointer can be left pointing to the link TRB,
1554		 * we must handle that
1555		 */
1556		if ((command->command_trb->link.control & TRB_TYPE_BITMASK)
1557				== TRB_TYPE(TRB_LINK))
1558			command->command_trb =
1559				xhci->cmd_ring->enq_seg->next->trbs;
1560
1561		list_add_tail(&command->cmd_list, &virt_dev->cmd_list);
1562	} else {
1563		in_ctx = virt_dev->in_ctx;
1564		cmd_completion = &virt_dev->cmd_completion;
1565		cmd_status = &virt_dev->cmd_status;
1566	}
1567	init_completion(cmd_completion);
1568
1569	if (!ctx_change)
1570		ret = xhci_queue_configure_endpoint(xhci, in_ctx->dma,
1571				udev->slot_id, must_succeed);
1572	else
1573		ret = xhci_queue_evaluate_context(xhci, in_ctx->dma,
1574				udev->slot_id);
1575	if (ret < 0) {
1576		if (command)
1577			list_del(&command->cmd_list);
1578		spin_unlock_irqrestore(&xhci->lock, flags);
1579		xhci_dbg(xhci, "FIXME allocate a new ring segment\n");
1580		return -ENOMEM;
1581	}
1582	xhci_ring_cmd_db(xhci);
1583	spin_unlock_irqrestore(&xhci->lock, flags);
1584
1585	/* Wait for the configure endpoint command to complete */
1586	timeleft = wait_for_completion_interruptible_timeout(
1587			cmd_completion,
1588			USB_CTRL_SET_TIMEOUT);
1589	if (timeleft <= 0) {
1590		xhci_warn(xhci, "%s while waiting for %s command\n",
1591				timeleft == 0 ? "Timeout" : "Signal",
1592				ctx_change == 0 ?
1593					"configure endpoint" :
1594					"evaluate context");
1595		/* FIXME cancel the configure endpoint command */
1596		return -ETIME;
1597	}
1598
1599	if (!ctx_change)
1600		return xhci_configure_endpoint_result(xhci, udev, cmd_status);
1601	return xhci_evaluate_context_result(xhci, udev, cmd_status);
1602}
1603
1604/* Called after one or more calls to xhci_add_endpoint() or
1605 * xhci_drop_endpoint().  If this call fails, the USB core is expected
1606 * to call xhci_reset_bandwidth().
1607 *
1608 * Since we are in the middle of changing either configuration or
1609 * installing a new alt setting, the USB core won't allow URBs to be
1610 * enqueued for any endpoint on the old config or interface.  Nothing
1611 * else should be touching the xhci->devs[slot_id] structure, so we
1612 * don't need to take the xhci->lock for manipulating that.
1613 */
1614int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
1615{
1616	int i;
1617	int ret = 0;
1618	struct xhci_hcd *xhci;
1619	struct xhci_virt_device	*virt_dev;
1620	struct xhci_input_control_ctx *ctrl_ctx;
1621	struct xhci_slot_ctx *slot_ctx;
1622
1623	ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
1624	if (ret <= 0)
1625		return ret;
1626	xhci = hcd_to_xhci(hcd);
1627
1628	xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
1629	virt_dev = xhci->devs[udev->slot_id];
1630
1631	/* See section 4.6.6 - A0 = 1; A1 = D0 = D1 = 0 */
1632	ctrl_ctx = xhci_get_input_control_ctx(xhci, virt_dev->in_ctx);
1633	ctrl_ctx->add_flags |= SLOT_FLAG;
1634	ctrl_ctx->add_flags &= ~EP0_FLAG;
1635	ctrl_ctx->drop_flags &= ~SLOT_FLAG;
1636	ctrl_ctx->drop_flags &= ~EP0_FLAG;
1637	xhci_dbg(xhci, "New Input Control Context:\n");
1638	slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
1639	xhci_dbg_ctx(xhci, virt_dev->in_ctx,
1640			LAST_CTX_TO_EP_NUM(slot_ctx->dev_info));
1641
1642	ret = xhci_configure_endpoint(xhci, udev, NULL,
1643			false, false);
1644	if (ret) {
1645		/* Callee should call reset_bandwidth() */
1646		return ret;
1647	}
1648
1649	xhci_dbg(xhci, "Output context after successful config ep cmd:\n");
1650	xhci_d

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